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On Thu, 25 Jun 2009 18:01:02 +0000, Steve Pope wrote: > Eric Jacobsen <eric.jacobsen@ieee.org> wrote: > >>You seem to be looking for a UHF to 70MHz downconverter. There are >>lots of UHF tuners with 70MHz outputs, but many/most are for broadcast >>applications and only support bandwidths up to about 8MHz. > >>You may be able to find something with a bandwidth as wide as you're >>asking (80MHz), but I suspect you'll have to look around and it won't be >>cheap. That's a pretty wide bandwidth and most applications don't need >>or support that much. > > This is why I suggested a quadrature mixer down to baseband. Then the > output bandwidth is only ~40 MHz. A little googling suggests such a > connectorized component exists. Dunno about the cost though. > > Steve The quoted 80MHz bandwidth is the 3dB point, so they probably need more than 40MHz. Which doesn't much change your conclusion, aside from the fact that they need to pay attention to their _real_ bandwidth constraints. -- www.wescottdesign.comArticle: 141501
On Jun 25, 3:00=A0pm, rickman <gnu...@gmail.com> wrote: > On Jun 25, 2:49 pm, gabor <ga...@alacron.com> wrote: > > > > > On Jun 25, 7:22 am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On Jun 25, 2:12 pm, "Nial Stewart" > > > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > > > Everybody knows that from user point of view Flash based FPGA are > > > > > better because they are nonvvolatile, tolerable to radiation, do = not > > > > > consume high current at startup and better secure intellectual > > > > > property. On the other hand SRAM FPGA are much easier to manufact= ure. > > > > > > That's it? > > > > > No. > > > > > All I'll say is that if you're used to the sort of P&R results you = get > > > > with Altera/Xilinx tools and devices be wary of committing to a tra= nsfer > > > > to a Flash based device without a _lot_ of experimenting first. > > > > > Nial. > > > > well that counts for ACTEL yes!!!! > > > > Lattice is almost like Xilinx, even has distributed RAM (only SRL16 > > > mode is missing) > > > ic65L is like old Xilinx LUT4FF > > > > but in generic yes, need run real P&R and compare actual designs > > > before > > > doing any decisions > > > > Antti > > > Lattice's mixed flash / SRAM parts also don't have the same > > instant-on and radiation tolerance features of the Actel parts. > > So in essence you lose some of the features to gain better > > density and architecture. > > Certainly radiation tolerance is a seldom used feature that has use > only in very specialized applications. =A0When is the "instant on" > feature needed really? =A0I don't think I have had an app that needed > "instant on" in the 30 years I have been designing electronics. > Digital stuff always has a reset to hold it off until all power, etc > is ready for operation. =A0When I use an FPGA, I use one of the FPGA > outputs to hold the rest of the circuit in reset so the FPGA is the > first thing to come alive. =A0Even if the FPGA is on a PCI bus, I > believe they have provision to give devices time to boot themselves > before they have to respond, no? > > Is "instant on" another seldom needed feature? > > Rick The point I was trying to make is that all "Flash-based" FPGA's are not the same. Lattice's are really SRAM-based using a mixed SRAM / Flash process with backup storage in the on-chip flash. Xilinx's 3AN series are multi-die solutions with a standard SRAM-based part and a SPI flash packaged together. The OP seemed to like some of the Actel features that don't exist in these hybrid devices. "Instant" on may not be needed often, but there are many applications where the startup delay time matters. As the OP was referring to "the largest parts" in the various series, these delays are not trivial, and can screw up a system that needs the FPGA resources before a PCI starts is enumeration, for example. Getting a large Virtex 5 to start up in under 1 second is not a simple task. There's no indication of flash-based devices being anything more than a side line for Xilinx, but if Virtex 5 or 6 comes out in a Spartan 3AN-like hybrid version, you can be sure it won't come up "instantly." Cheers, GaborArticle: 141502
Eric Jacobsen wrote: > On 6/25/2009 5:10 AM, recoder wrote: >> On 25 Haziran, 10:59, "Sebastien @ Sundance" >> <maury.sebast...@gmail.com> wrote: >>> On Jun 24, 11:15 pm, recoder<kurtulmeh...@gmail.com> wrote: >>> >>>> We are used to process 70 Mhz IF by using ADC boards to interface to >>>> our fpga boards. >>>> Now we have to process the following signal: >>>> 720 Mhz IF >>>> qpsk modulated >>>> 80 mhz bandwith (3 dB) >>>> Can anybody recommend a board to interface the 720 Mhz IF to a FPGA >>>> board? >>> If you are looking at a complete system, you can check the SMT702 that >>> may do the job >>> :http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT702 >>> >>> - Sebastien >> >> Thank you for your recommendation but I think downconverting 720 mhz >> to 140 or 70 Mhz would be a better solution. I am looking for a board >> that can do the job. > > You seem to be looking for a UHF to 70MHz downconverter. There are > lots of UHF tuners with 70MHz outputs, but many/most are for broadcast > applications and only support bandwidths up to about 8MHz. > > You may be able to find something with a bandwidth as wide as you're > asking (80MHz), but I suspect you'll have to look around and it won't be > cheap. That's a pretty wide bandwidth and most applications don't need > or support that much. A bandwidth of 80 XHz at a frequency of 70 XHz is pretty extreme at for any value of X. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 141503
Antti wrote: > Bitstreams must not contain a sync word followed by all 1s. This > condition might > cause damage to the device. > > Is this an feature or bug? should this go into ERRATA and be fixed > ASAP?? > > Antti This has been confirmed to be an error in the document and will be updated in the next revision. It is possible to damage an FPGA with a badly corrupted bitstream, but it takes more than a sync word followed by ones to do this. Ed McGettigan -- Xilinx Inc.Article: 141504
On 25 June, 23:31, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Antti wrote: > > Bitstreams must not contain a sync word followed by all 1=92s. This > > condition might > > cause damage to the device. > > > Is this an feature or bug? should this go into ERRATA and be fixed > > ASAP?? > > > Antti > > This has been confirmed to be an error in the document and will be > updated in the next revision. > > It is possible to damage an FPGA with a badly corrupted bitstream, but > it takes more than a sync word followed by ones to do this. > > Ed McGettigan That could potentially be an interesting feature. I can't remember exactly now, but Motorola - now Freescale - had a DSP that can blow itself up if you overdrive the PLL and some security folks did use that to some end. -MArticle: 141505
Jerry Avins wrote: > Eric Jacobsen wrote: >> On 6/25/2009 5:10 AM, recoder wrote: >>> On 25 Haziran, 10:59, "Sebastien @ Sundance" >>> <maury.sebast...@gmail.com> wrote: >>>> On Jun 24, 11:15 pm, recoder<kurtulmeh...@gmail.com> wrote: >>>> >>>>> We are used to process 70 Mhz IF by using ADC boards to interface to >>>>> our fpga boards. >>>>> Now we have to process the following signal: >>>>> 720 Mhz IF >>>>> qpsk modulated >>>>> 80 mhz bandwith (3 dB) >>>>> Can anybody recommend a board to interface the 720 Mhz IF to a FPGA >>>>> board? >>>> If you are looking at a complete system, you can check the SMT702 that >>>> may do the job >>>> :http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT702 >>>> >>>> - Sebastien >>> >>> Thank you for your recommendation but I think downconverting 720 mhz >>> to 140 or 70 Mhz would be a better solution. I am looking for a board >>> that can do the job. >> >> You seem to be looking for a UHF to 70MHz downconverter. There are >> lots of UHF tuners with 70MHz outputs, but many/most are for broadcast >> applications and only support bandwidths up to about 8MHz. >> >> You may be able to find something with a bandwidth as wide as you're >> asking (80MHz), but I suspect you'll have to look around and it won't >> be cheap. That's a pretty wide bandwidth and most applications don't >> need or support that much. > > A bandwidth of 80 XHz at a frequency of 70 XHz is pretty extreme at for > any value of X. > That's a pretty normal scenario for us ultrasound guys :-) Well, ok, technically I have ventured away from ultrasound a bit the last year. Did some industrial electronics design, almost feels like a vacation. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 141506
On Thu, 25 Jun 2009 02:29:39 -0700 (PDT), Poojan Wagh <poojanwagh@gmail.com> wrote: >Went to a Xilinx class yesterday. Apparently, ISE 11.2 got released >yesterday. (Instructor said we should have an email in our Inbox.) >Also, ML605 (Virtex-6) and equivalent Spartan-6 eval boards are on >Xilinx' site: http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm. >However, it says that Virtex-6 boards will be available "in July". See >also: http://www.pldesignline.com/products/218101026 It also says the Spartan-6 boards ARE available, and has a cute little "buy it now" button to take you to Avnet. Whose site says... no stock 6 week leadtime... Is this the sort of "available" we can expect for the V6 boards in July? - BrianArticle: 141507
On Jun 26, 2:28=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 25 Jun 2009 02:29:39 -0700 (PDT), Poojan Wagh <poojanw...@gmail.c= om> > wrote: > > >Went to a Xilinx class yesterday. Apparently, ISE 11.2 got released > >yesterday. (Instructor said we should have an email in our Inbox.) > >Also, ML605 (Virtex-6) and equivalent Spartan-6 eval boards are on > >Xilinx' site:http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm. > >However, it says that Virtex-6 boards will be available "in July". See > >also:http://www.pldesignline.com/products/218101026 > > It also says the Spartan-6 boards ARE available, and has a cute little "b= uy it > now" button to take you to Avnet. Whose site says... > > no stock > 6 week leadtime... > > Is this the sort of "available" we can expect for the V6 boards in July? > > - Brian it was 12 weeks when i looked? AnttiArticle: 141508
This is ridiculous I have been contacted lately like, can you download this xyz for me because I cant login, and usually I have managed to help such request but EVERY other day my accounts also do not work there is not even possible to click on "recover" password or browse projects, everything fails opencores USED to MUCH better and easier to access when it was driven by the old domain owners. Now its real PITA :( AnttiArticle: 141509
On 10 Jun., 10:44, recoder <kurtulmeh...@gmail.com> wrote: > Dear All, > =A0We have implemented a high speed qpsk demodulator in a FPGA > demodulator board. > Until now we fed the I and Q inputs from another board by wire. > Now we are looking for an IF board that can take a 70 Mhz RF signal > and output the I and Q signals to be fed to our FPGA board. > Can anybody recommend one? > Thanx in advance We will have a Virtex-5 PCIe boards with a 4 channel 10 Bit ADC with up to 5 Gsps soon: http://cronologic.de/products/ Kolaj SulimmaArticle: 141510
On 25 Haziran, 21:07, "langw...@fonz.dk" <langw...@fonz.dk> wrote: > On 25 Jun., 14:10, recoder <kurtulmeh...@gmail.com> wrote: > > > > > > > On 25 Haziran, 10:59, "Sebastien @ Sundance" > > > <maury.sebast...@gmail.com> wrote: > > > On Jun 24, 11:15=A0pm, recoder <kurtulmeh...@gmail.com> wrote: > > > > > =A0We are used to process 70 Mhz IF by using ADC boards to interfac= e to > > > > our fpga boards. > > > > Now we have to process the following signal: > > > > 720 Mhz IF > > > > qpsk modulated > > > > =A080 mhz bandwith (3 dB) > > > > > Can anybody recommend a board to interface the 720 Mhz IF to a FPGA > > > > board? > > > > If you are looking at a complete system, you can check the SMT702 tha= t > > > may do the job :http://www.sundance.com/web/files/productpage.asp?STR= Filter=3DSMT702 > > > > - Sebastien > > > Thank you for your recommendation but I think downconverting 720 mhz > > to 140 or 70 Mhz would be a better solution. I am looking for a board > > that can do the job. > > something like a combo of =A0 ad8348 and adf4360-7 =A0eval boards ? > > -Lasse- Al=FDnt=FDy=FD gizle - > > - Al=FDnt=FDy=FD g=F6ster - Thank you, this seems to be a viable solution. The ad8348 has a Demodulation bandwidth of 75 MHz. As our signal is 82 Mhz wide we are not sure if this IC will be good for us. Maybe ADL5387 will help.Article: 141511
On Wed, 24 Jun 2009 10:45:55 +0100, Jonathan Bromley wrote: >I've encountered what seems to me to be a bug >in XST (all versions from 8 to 11 inclusive) [...] >Given that the whole point of memory inference from >HDL code is that you get a convenient, readable, >accurate simulation model as part of your design >code, this behaviour by the synthesis tools is >incomprehensible to me. Can anyone clarify? Lots of interesting responses - thanks! - but the executive summary seems to be: anyone who understands VHDL well enough to do simulation would never dream of using the idiotic wrong template. I've raised Webcase 788437 requesting that XST should error out on the offending code. It seems to me that anyone trying to use RAM inference without intending to simulate is a Silly Billy (tm) who would greatly benefit from the mild shock administered by a suitable error message. Now it's time to fight the same problem in Quartus :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141512
Antti wrote: > http://news.prnewswire.com/ViewContent.aspx?ACCT=109&STORY=/www/story/03-31-2009/0004998410&EDATE= > > already 2 weeks? > > but how come there can exist 1000 designs, when first shipments made > 31 march? > also the number of EA customers 700 seems unlikely, if so then > logistic has made > miracles shipping to 700 customers in NO time and those already used > the parts > in 1000 designs? > > oh, well it only the news the xilinx way, it is still be seen whe ISE > support for > S6-V6 comes > > Antti Be careful with Avnet boards, We bought once Virtex-4 LX Evaluation Boards equipped with "engineering samples" that have dozens of "undocumented features" that are quite painful to figure out. Thats something for early adaptors but not really reliable for common use. We dumped more than a thousand EURO by this. DirkArticle: 141513
Hi Antti, I'm not sure if you sent your email to the right address since we have not received any emails from you lately, but lets try and find out what causing the problem. If you send me your OC-username I will check in the database. Send your info to: oc-team@opencores.org regards, Marcus ErlandssonArticle: 141514
"Muzaffer Kal" <kal@dspia.com> wrote in message news:csq445t6012cnufggai343t9jqptbe2pnd@4ax.com... > On Wed, 24 Jun 2009 18:57:29 +0100, Jonathan Bromley > <jonathan.bromley@MYCOMPANY.com> wrote: > >>I'm trying to assemble a complete and accurate list >>of the _synthesizable_ templates for all common types >>of FPGA memory, and I have discovered a template >>that synthesizes to dual-clock RAM in two FPGA >>vendors' tools but is a complete nonsense for >>simulation. I want to know why this has happened, >>what we can do about it, and why the vendors haven't >>already been beaten to pulp over it by users. > > Originally coming from ASIC side I find this incredible but it seems > that majority of people doing FPGA design don't simulate. I was at an > FPGA infomercial the other day about two new device families coming > out from a vendor to stay nameless and only %20 or so people raised > their hands when asked this question. This might explain how these > templates survived as is for such a long time. At the same time blind reliance of simulators is just as bad. There is the old saying garbage in = garbage out. Personally I choose a mix as an early misunderstanding can otherwise waste an inordinate amount of time. In the past I have also come across instances where simulation has taken so long, and created such large files, that reality has been quicker with a few debugging flags in the code! Each to their own.Article: 141515
On Jun 25, 1:53=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > > Getting software folk and digital designers > talking to each other would be a big step in > the right direction. =A0Sometimes that works well, > but certain project management styles (as in Rick's > story) go a long way towards preventing it. > > Re-skilling, as often as you get the chance, is > a pretty good antidote to belief that you know > it all. =A0Career circumstances don't usually make > that easy to do, sadly. Most of the time when I mention that FPGA/ASIC engineers could learn a trick or three from their SW brethren, I get bombarded with "FPGA/ASIC design is not SW!" True enough, but the discipline of code design, and to a lesser extent testing, is very much the same between the two. The requirements for the code are much different (usually), but the method in which complex requirements must be analyzed, broken down, designed into code and verified are incredibly similar. SW has developed over the years many techniques for dealing with the complexity of all things coded, and we HW engineers can learn an awful lot from them about at least that. I have worked with some SW engineers that fairly quickly grasped the HW nature of HDL code, and some that didn't ever get it. I have also worked with some HW engineers that grasped the SW nature of their design, and some that didn't. Those that do understand the similarities and the differences between the two, and exploit the similarities while observing the limitations of the differences, are the ones I want on my team. There are often organizational turf battles that get in the way of honest exchange of ideas and solutions between SW and HW. It seems to be the mavericks from both camps that tend to understand the common ground and then exploit it, to the benefit of both. AndyArticle: 141516
Hello, I am on pin count design on my Spartan-3an !!! I have a bank1 with vccio @ 1.8V. Could I use two IOs of this bank1 as an open-drain output. This open- dain output will force '0' to a 5V signal. Not the signal has a pull- up of 2.2k -> I will not need to get the Input as input but as a simple open-drain. Please let me know if I can do this, or if I will stress the SPARTAN-3AN. Best regards, Laurent http://www.amontec.comArticle: 141517
Larry <job@amontec.com> wrote: > Hello, > I am on pin count design on my Spartan-3an !!! > I have a bank1 with vccio @ 1.8V. > Could I use two IOs of this bank1 as an open-drain output. This open- > dain output will force '0' to a 5V signal. Not the signal has a pull- > up of 2.2k -> I will not need to get the Input as input but as a > simple open-drain. > Please let me know if I can do this, or if I will stress the > SPARTAN-3AN. Not quite sure what you mean. However DS557 specifies in the > DC Electrical Characteristics (p. 11) .. > VIN > Voltage applied to all User I/O pins and Driver in a high-impedance state > Dual-Purpose pins -0.95 4.6 V So a pullup to 5 V is destructive... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 141518
On Jun 26, 4:01=A0pm, OC-team <marcus.erlands...@gmail.com> wrote: > Hi Antti, > I'm not sure if you sent your email to the right address since we have > not received any emails from you lately, but lets try and find out > what causing the problem. If you send me your OC-username I will check > in the database. > > Send your info to: oc-t...@opencores.org > > regards, > Marcus Erlandsson I TRIED well i another PC on my desk worked ok but this one, it does not login, and it does not show the project and it does not allow to request new password it means i tried to request new password, but your system did not send the emails and did not do anything something is messed up with cookies well, not a big problem, i just make a notice that opencores eventually work if you try from enough different PC's to access it sorry that I do not how to help you, something is wrong defenetly, but as my account works from different PC I do not want anything to be done AnttiArticle: 141519
On Jun 26, 4:54=A0pm, Larry <j...@amontec.com> wrote: > Hello, > > I am on pin count design on my Spartan-3an !!! > > I have a bank1 with vccio @ 1.8V. > Could I use two IOs of this bank1 as an open-drain output. This open- > dain output will force '0' to a 5V signal. Not the signal has a pull- > up of 2.2k -> I will not need to get the Input as input but as a > simple open-drain. > > Please let me know if I can do this, or if I will stress the > SPARTAN-3AN. > > Best regards, > Laurent > =A0http://www.amontec.com Hi Laurent, do no try oversmart with such things dead FPGA's on board are no fun (I do have some that asfaik are dead because of series resistor from io to 5V well not 100% confirmed but better be cautios) if FPGA is not 5V tolerant then do not connect it to wire that has pullup to 5V no matter the pullup resistor value S3A datasheet does say that ABSOLUTE MAX rating is 4.6 if not driving (regardless of VCCIO bank) but hm, I would still not go designing systems where input on FPGA pin is 2X higher then VCCIO of that bank (maybe i am too scared, and it is ok) add a dual digital sc-70 packaged transistor and you have 2 perfectly safe open-drain outputs AnttiArticle: 141520
Hello, I was wondering if anyone has any advice on ways to use the Xilinx tools such as Impact, EDK, and Chipscope with a custom board that uses a ft2232 chip connected to JTAG? I have a custom open source board, http://www.gadgetfactory.net/gf/project/butterfly_main/, that uses a ft2232 chip for jtag communication. I am currently able to load svf files using urjtag but I am trying to work out a way to use the Xilinx tools with this custom board. Searching through the forums seems to indicate that there are no official Xilinx published API's to support custom programming cables. The only thing I can find is the libusb-driver project at http://www.rmdir.de/~michael/xilinx/. It looks like this will allow me to accomplish what I am trying to do under Linux but I'm not sure if this will work under windows with cygwin or mingw. So my two questions are: 1) Does anyone know of another or better way to use the Xilinx tools with a custom FT2232 based board? 2) Does the Windows version of the tools support the environment variable that tells it to use the libusb driver? If it does then I should be able to compile under cygwin/mingw and support using the tools in both environments. Thank you, Jack Gassett http://www.GadgetFactory.net Home of the ButterFly Platform, an open source FPGA circuit design.Article: 141521
On Jun 24, 12:14=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > Bitstreams must not contain a sync word followed by all 1=92s. This > condition might > cause damage to the device. > > Is this an feature or bug? should this go into ERRATA and be fixed > ASAP?? > > Antti Hmm, I put this in the same category as a warning stating "DO NOT CRAWL ACROSS BROKEN GLASS." What are the odds of "accidentally" sending a sync. word followed by a few million '1' bits? I'm sure that someone must have done it, hence the errata notice. I'm not sure this would be worth a $1M mask spin to fix (unless there are more important issues as well). You can damage lots of semi's by misprogramming them. Have the outputs from two interface devices fight on a bus and just watch the gladiatorial fun! -- Steve Knapp Prevailing Technology, Inc. www.prevailing-technology.cmArticle: 141522
On Jun 26, 6:49=A0pm, "jack.gassett" <jack.gass...@gadgetfactory.net> wrote: > Hello, > > I was wondering if anyone has any advice on ways to use the Xilinx > tools such as Impact, EDK, and Chipscope with a custom board that uses > a ft2232 chip connected to JTAG? > > I have a custom open source board,http://www.gadgetfactory.net/gf/project= /butterfly_main/, > that uses a ft2232 chip for jtag communication. I am currently able to > load svf files using urjtag but I am trying to work out a way to use > the Xilinx tools with this custom board. Searching through the forums > seems to indicate that there are no official Xilinx published API's to > support custom programming cables. The only thing I can find is the > libusb-driver project athttp://www.rmdir.de/~michael/xilinx/. It > looks like this will allow me to accomplish what I am trying to do > under Linux but I'm not sure if this will work under windows with > cygwin or mingw. > > So my two questions are: > > 1) Does anyone know of another or better way to use the Xilinx tools > with a custom FT2232 based board? > > 2) Does the Windows version of the tools support the environment > variable that tells it to use the libusb driver? If it does then I > should be able to compile under cygwin/mingw and support using the > tools in both environments. > > Thank you, > > Jack Gassetthttp://www.GadgetFactory.net > Home of the ButterFly Platform, an open source FPGA circuit design. SHORT NO WAY the linux version is WIN DRIVER EMULATION driver most likely pretty much illegal actually, there are windriver internals emulated and included in the linux emulation driver, well it is very likely windriver will not try send C&D but they could, it is of course DOABLE for windows too, all you need is to replace windrv6.sys in windows\system32\drivers with new driver emulating windriver, then yes you could use 3rd party cable with xilinx tools, otherwise no AnttiArticle: 141523
On Jun 26, 7:04=A0pm, Prevailing over Technology <steve.kn...@prevailing- technology.com> wrote: > On Jun 24, 12:14=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > Bitstreams must not contain a sync word followed by all 1=92s. This > > condition might > > cause damage to the device. > > > Is this an feature or bug? should this go into ERRATA and be fixed > > ASAP?? > > > Antti > > Hmm, I put this in the same category as a warning stating "DO NOT > CRAWL ACROSS BROKEN GLASS." > > What are the odds of "accidentally" sending a sync. word followed by a > few million '1' bits? =A0I'm sure that someone must have done it, hence > the errata notice. =A0I'm not sure this would be worth a $1M mask spin > to fix (unless there are more important issues as well). > > You can damage lots of semi's by misprogramming them. =A0Have the > outputs from two interface devices fight on a bus and just watch the > gladiatorial fun! > > -- Steve Knapp > =A0 =A0Prevailing Technology, Inc. > =A0 =A0www.prevailing-technology.cm its not that, only 11's you did not read all the fine print scenarion 1: start programming, erase, write sync written, POWER OFF, POWER ON FPGA ---> PUFFFF BLOW UP the above is not 1:MIO odds case or is it? now, i did include partial info, not only 11111 but also "just bad" bit file can damage i mean bit files that are INVALID, without proper CRC and trailer and this seems to be so SEVERE and common to happen, that xilinx issued special case HOW TO WRITE FLASH (in order to prevent blow up) so from Xilinx docs for S-6 procedure for writing nv memories for S-6 ERASE skip over sync (do not write it), WRITE the bitstream seek back, write SYNC for any other FPGA except S-6 this like procedure for configuration memory is not required or recommended ASFAIK at least of course it is possible to write KNOWN BLOW UP MY FPGA bitstream, but those would be valid bitstreams that will overstress the silicon, but INVALID bitstreams (that should not release the FPGA to be functional) should not damage the FPGA... imho AnttiArticle: 141524
jack.gassett <jack.gassett@gadgetfactory.net> wrote: > Hello, > I was wondering if anyone has any advice on ways to use the Xilinx > tools such as Impact, EDK, and Chipscope with a custom board that uses > a ft2232 chip connected to JTAG? > I have a custom open source board, > http://www.gadgetfactory.net/gf/project/butterfly_main/, > that uses a ft2232 chip for jtag communication. I am currently able to > load svf files using urjtag but I am trying to work out a way to use > the Xilinx tools with this custom board. Searching through the forums > seems to indicate that there are no official Xilinx published API's to > support custom programming cables. The only thing I can find is the > libusb-driver project at http://www.rmdir.de/~michael/xilinx/. It > looks like this will allow me to accomplish what I am trying to do > under Linux but I'm not sure if this will work under windows with > cygwin or mingw. For programming, verify and readback, look at sourceforge xc3sprog SVN. No help for Chipscope. It's a pity, that Xilinx keeps both sides of the interface under the hood. Bug the Xilinx people at all exhibitions on this subject... > So my two questions are: > 1) Does anyone know of another or better way to use the Xilinx tools > with a custom FT2232 based board? I don't know of any existing solution. As it's all USB traffic, that can be captured and is partially reversed enginnered, one could think of a program that mimics a DLC10 cable but would trannslater the FX2 commands into MPSSE commands. Probably a major effort > 2) Does the Windows version of the tools support the environment > variable that tells it to use the libusb driver? If it does then I > should be able to compile under cygwin/mingw and support using the > tools in both environments. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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