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Svenn Are Bjerkem wrote: > Hi, <snip> > I'm wondering how other VHDL programmers solve their CSR bookkeeping, > or maybe there is a tool out there that I haven't found. It doesn't > need to be open source, if it is any good we will buy it. From the > efforts by Wilson Snyder on Vregs I take that this is not a tool that > I can write overnight myself. Maybe it is portable since it is written > in perl, but Verilog and VHDL does think differently, and I am not a > perl savvy. (Can't even read my own code after six weeks) That's a very interesting question, one that can play a big role in a product or project design. After running into troubles in the past, I have decided to generate both VHDL and documentation from a single definition file. The trick is that I do most things in JavaScript, which is roughly as powerful as Perl but with the added benefit of enabling "clickodromes". The defined parts are not registers (yet) but the instruction set. The desing is not advanced enough for the definition of the configuration registers (interrupt, I/O, integrated peripherals) but at least, my assembler (in JS) is mostly in synch with the VHDL code. If you have Mozilla (or any decent JS-handling browser except MSIE), have a look at http://f-cpu.seul.org/whygee/yasep/ http://f-cpu.seul.org/whygee/yasep/tools/opcode_map.html http://f-cpu.seul.org/whygee/yasep/tools/generate_VHDL.html (note that some parts are broken, such as the disassembler). I have found a lot of advantages to this approach. However it is better applied /after/ the architecture is defined and stable, or else the generation tools must be changed (which happens more often that we would want). In the case of YASEP, I have found that it's not too bad, it forces me to think further than the problem that I want to solve, I have to anticipate and plan my actions. Over the last years, it has paid :-) Hope this helps, > Svenn yg -- http://ygdes.com / http://yasep.orgArticle: 141626
On Jun 30, 5:53=A0am, John Eaton <z3qmt...@gmail.com> wrote: > On Jun 29, 7:35=A0am, radarman <jsham...@gmail.com> wrote: > > > > > On Jun 28, 4:45=A0pm, james <geo...@washington.edu> wrote: > > > > On Sun, 28 Jun 2009 06:42:25 -0700 (PDT), > > > > "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > > > > |On Jun 28, 3:42=A0pm, CMOS <manusha1...@gmail.com> wrote: > > > |> hi, > > > |> im plannining to buy a vertex 2 based FPGA board. this is the link= . > > > |> > > > |>http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,453&= Prod... > > > |> > > > |> does this board worthy for the price of $299? > > > |> > > > |> CMOS > > > | > > > |absolutly, if you get it for $299! > > > | > > > |too bad Xilinx is no longer supporting Virtex-II with their ISE > > > | > > > |ISE 10.1 is the last version that offered V-II support, > > > | > > > |Antti > > > |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > $299 is the acedemic pricing. > > > > james > > > I really wish more companies didn't specifically target "academic", > > and would offer a more broad "non-industrial" price. I'm not in > > college anymore, but I still try to keep my skills honed at home - > > thus, I don't have a student ID, but I still consider myself to be a > > "student". > > That's the problem when your a "hobbiest". You don't get any of the > breaks that you got as a student and the IRS frowns on letting you > write off any of your toys. Bummer. > > I do have a couple of digilent boards and they are quality products. > They are a good deal if you can get the academic price. hello all, thanks for all the advice and info. i think i will go ahead and buy one, as its for fun, not for commercial stuff. CMOSArticle: 141627
Why would you think it would not be possible or even hard? FM is a very simple modulation scheme and using an NCO should produce very acceptable results. Rick On Jul 1, 11:11=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > It is really possible to use FPGA to generate FM Radio signal DIRECTLY > in most cases there radio will pickup signal from PCB trace already > > i did only a very little experiments (wrote in june issue also a > little) > > even using audio signal to invert phase will produce signal that is > received > as FM modulation (with low modulation index) using simple NCO gives > much better results. > > AnttiArticle: 141628
On Jul 1, 7:09=A0pm, rickman <gnu...@gmail.com> wrote: > Why would you think it would not be possible or even hard? =A0FM is a > very simple modulation scheme and using an NCO should produce very > acceptable results. > > Rick > > On Jul 1, 11:11=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > It is really possible to use FPGA to generate FM Radio signal DIRECTLY > > in most cases there radio will pickup signal from PCB trace already > > > i did only a very little experiments (wrote in june issue also a > > little) > > > even using audio signal to invert phase will produce signal that is > > received > > as FM modulation (with low modulation index) using simple NCO gives > > much better results. > > > Antti yes, after thinking a little yes funny eveb PHASE inversion produces audible results, with nco should be possible get yes, maybe quite acceptable results, i did just a few tests, and i only had 1 bit audio to use as modulation, and the result was pretty good actually, much better than small piezo buzzer would do... maybe I assumed that real modulation is required but using nco clocked at 2x the output and modulating around mid frequency, hm maybe even that isnt required the receiver should overage it all and receive anyway AnttiArticle: 141629
Sharanbr wrote: > On Jul 1, 3:05 pm, "Symon" <symon_bre...@hotmail.com> wrote: >> http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0140_101.htm... > > Thanks, but I was not asking about the setting up the constraints for > fpga pinouts, it was a larger question. > How do I ensure that I have got a fairly accurate pinout (assuming > meeting timing is not an issue) when > the design is still under development. Do people create dummy FPGA top > and use special tools that only > check the validity of the pinouts wrt to the selected device? > > Look at it this way - people in S/W world exchange information about > each other's module > by providing the class prototypes and this happens much before the > code has been developed. > > Regards, There are comprehensive IO Planning tools in the ISE software. There is an overview here for both pre-synthesis and post-synthesis: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_pin_assignment_overview.htm Ed McGettigan -- Xilinx Inc.Article: 141630
In article <7avf62F20okpmU1@mid.individual.net>, Mike Treseler <mtreseler@gmail.com> writes: >Svenn Are Bjerkem wrote: > >> I'm wondering how other VHDL programmers solve their CSR bookkeeping, >> or maybe there is a tool out there that I haven't found. > >I don't automate any process until I've proven to >myself that the manual process warrants the automation time. Yes, but there are two reasons to (semi-) automate something. One is to save time. The other is to reduce the chances of errors. I'm often willing to spend a few hours writing some hack code if it will help prevent errors. >If I did decide to automate register documentation, I think I would >make the script read my code, not write it. I find it simpler to write complicated formats rather than read them. I'd (probably) put the data into an extra file with a simple format, read that, and write a skeleton of the code. >I would also make sure there was an audience for my pretty printing, >before I went to the trouble generating it. Again, yes, but I can be a good-enough audience all by myself. There may be two parts to this discussion. One is getting started where you have to type in lots of stuff. The same info shows up in several places. The other is making changes where you have to be sure to update all those places. If you have a formal release process, and you get compare-them on the check list, it's not too hard to verify that things are in sync. (I find it easier with more than one person.) But that doesn't cover the debugging stage. There is a similar problem with coordinating pin assignments. The code inside the FPGA needs to match the signal names where the pins hit the PCB. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 141631
Antti.Lukats@googlemail.com wrote: > maybe I assumed that real modulation is required > but using nco clocked at 2x the output and modulating around > mid frequency, hm maybe even that isnt required the > receiver should overage it all and receive anyway of course, you won't make a commercial product out of this hack, right ? your system certainly makes so many out-of-band noise that it won't pass any certification... radio is black magic for me... But computers and radios have had a long story of love & hate. On some old IBM tube-based mainframes, there was a radio reciever that picked up the internal noise, which the operators were used to. When the machine hung, the operator would instantly "hear" it... Also, I've read that the Alta=EFr computer kit (was it this one ?) was once used to run a specific program that disturbed a close radio so music would be heard... Have fun anyway, > Antti yg --=20 http://ygdes.com / http://yasep.orgArticle: 141632
Dave <dhschetz@gmail.com> wrote:
>On Jul 1, 9:40=A0am, Sharanbr <sharan.basa...@gmail.com> wrote:
>> On Jul 1, 3:05 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>>
>> >http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0140_101.htm...
>>
>> Thanks, but I was not asking about the setting up the constraints for
>> fpga pinouts, it was a larger question.
>> How do I ensure that I have got a fairly accurate pinout (assuming
>> meeting timing is not an issue) when
>> the design is still under development. Do people create dummy FPGA top
>> and use special tools that only
>> check the validity of the pinouts wrt to the selected device?
>>
>> Look at it this way - people in S/W world exchange information about
>> each other's module
>> by providing the class prototypes and this happens much before the
>> code has been developed.
>>
>> Regards,
>
>You should look at the datasheet and user guide for the device you're
>using, and understand the functionality of the different types of pins
>it has. Then, you can start deciding which pins can go where. Board
>layout concerns and I/O standards come into play as well.
Indeed, but you may still encounter surpises that are not in the
datasheet but can be found in appnotes. For instance: Xilinx has fast
clock sharing between IOBs on Spartan3 devices. These only work for
the top and botton IOBs, not the IOBs on the side. Also, many IOBs
share clock inputs. You can't use 2 different clocks for
inputs/outputs which share those clock lines.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 141633So far, I have only been able to find Spartan6 ( which isn't really available yet) from Xilinx and some small FPGA from Actel ( Igloo family ?). Trouble is, Spartan has only two lanes, which is enough only for PCI-e x1. Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. Is there anything else worth looking at ? I'm looking for chip with decent PCI-e interface ( say at least 8 lanes for PCI-e x4 ) in the cost range $10-20 or so...Article: 141634
On Jul 1, 3:04=A0pm, Brane2 <bran...@avtomatika.com> wrote: > So far, I have only been able to find Spartan6 ( which isn't really > available yet) from Xilinx =A0and some small FPGA from Actel ( Igloo > family ?). > > Trouble is, Spartan has only two lanes, which is enough only for PCI-e > x1. > Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > > Is there anything else worth looking at ? > > I'm looking for chip with decent PCI-e interface ( say at least 8 > lanes for PCI-e x4 ) in the cost range $10-20 or so... No Actel Igloo that I know of supports PCI-e in any shape or form. If act, I'm not sure what Actel FPGA supports any form of multigigabit serialization. Consider looking at Altera Arria GX, which is in production, or Arria II GX, which will be in production in the near future. Your statement that Spartan-6 has only two lanes is incorrect; although the integrated endpoint only supports one lane, there's nothing stopping you from using all 8 transceivers in the design for an 8 lane link. It just means you need to do a bit more work. - NathanArticle: 141635
whygee <whygee@yg.yg> wrote: < But computers and radios have had a long story of love & hate. < On some old IBM tube-based mainframes, there was a radio reciever < that picked up the internal noise, which the operators were used to. < When the machine hung, the operator would instantly "hear" it... I use to hear stories about computers with speakers actually connected to some internal signal. The same idea, when the sound was repetitive the program was in a loop, and the operator would kill it. My father had problems with programs that were supposed to have long loops getting killed too early. -- glenArticle: 141636
On Jul 2, 3:11=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > It is really possible to use FPGA to generate FM Radio signal DIRECTLY > in most cases there radio will pickup signal from PCB trace already > > i did only a very little experiments (wrote in june issue also a > little) > > even using audio signal to invert phase will produce signal that is > received > as FM modulation (with low modulation index) using simple NCO gives > much better results. Interesting, but it will have a fat spectrum...? You could get (somewhere) into the FM band easily enough with a ring oscillator, and the average frequency could tell you the die temperature ;) Modulate one gate in that chain,and you get FM, Modulate Vcc, and you also get FM ... Next thing to do, is look at the Traffic Data information some radios can receive, and send real messages to your FM radio... You could give the spooks a real fright with that one.. -jgArticle: 141637
Sharanbr wrote: > How do I ensure that I have got a fairly accurate pinout (assuming > meeting timing is not an issue) when > the design is still under development. Do people create dummy FPGA top > and use special tools that only > check the validity of the pinouts wrt to the selected device? The most simplistic method is just to create dummy toplevel design, and do pinmapping to that file with the help of the tools and manual, and run the basic DRC checks. In bigger designs that is not usually enough. If complex clocking or big amount of special blocks (serdes for example) are used I at least recommend a toplevel that has clocking structures and the special blocks instantiated. That file can be then run with the pinmapping trough the normal P&R flow to make sure that it is implementable. And for good PCB layout the pinmapping has to be loaded into PCB level tools (Mentor I/O Designer etc.) and the new pinmapping has to be verified again in the P&R flow after each modification. --KimArticle: 141638
On Jul 2, 1:30=A0am, Nathan Bialke <nat...@bialke.com> wrote: > On Jul 1, 3:04=A0pm, Brane2 <bran...@avtomatika.com> wrote: > > > So far, I have only been able to find Spartan6 ( which isn't really > > available yet) from Xilinx =A0and some small FPGA from Actel ( Igloo > > family ?). > > > Trouble is, Spartan has only two lanes, which is enough only for PCI-e > > x1. > > Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > > > Is there anything else worth looking at ? > > > I'm looking for chip with decent PCI-e interface ( say at least 8 > > lanes for PCI-e x4 ) in the cost range $10-20 or so... > > No Actel Igloo that I know of supports PCI-e in any shape or form. If > act, I'm not sure what Actel FPGA supports any form of multigigabit > serialization. > > Consider looking at Altera Arria GX, which is in production, or Arria > II GX, which will be in production in the near future. > > Your statement that Spartan-6 has only two lanes is incorrect; > although the integrated endpoint only supports one lane, there's > nothing stopping you from using all 8 transceivers in the design for > an 8 lane link. It just means you need to do a bit more work. > > - Nathan Hi cheap PCIe is still a problem, a 2 chip solution in price range $20 is possible but one chip one is harder lattice promises 1K$LUT so ECP3-17 should be around 17$ altera has promised arria iiggx as low as 10$ but that the real life is still a little different, yesterday it looked that cheapes FPGA with PCIe cost 240$ ? (arria) hm maybe some virtex is cheaper than arria maybe s-6 changes this, and becomes first available AND cheap FPGA with PCIe but it assumed still a year til that AnttiArticle: 141639
Brane2 schrieb: > So far, I have only been able to find Spartan6 ( which isn't really > available yet) from Xilinx and some small FPGA from Actel ( Igloo > family ?). > > Trouble is, Spartan has only two lanes, which is enough only for PCI-e > x1. > Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > > Is there anything else worth looking at ? > > I'm looking for chip with decent PCI-e interface ( say at least 8 > lanes for PCI-e x4 ) in the cost range $10-20 or so... $10 - $20 is probably not that easy. Lattice ECP2M / ECP3M comes close though. I have done three customer designs in the last year or so. Two using ECP2M20 and one with ECP2M35. The Lattice web-shop lists a price of about $50 for the ECP2M20 but you can probably do much better through a distributor. I don't know exactly what price my customers are paying but I have the sound impression that it's around or below €30. Lattice, at least here in central Europe, give you very flexible IP licencing rates. I also do local training for the Lattice PCIe core. I would estimate at least a dozen of the course participants in the last two years have or are in the process of using Lattice for their PCIe design. (x1 or x4 configurations) The core isn't all that difficult to integrate. You just have to understand how to build and decode PCIexpress packets. If you are looking for direct attachment to Wishbone for instance or are in need of a device driver, drop me a mail.Article: 141640
Antti.Lukats@googlemail.com wrote: > cheap PCIe is still a problem, a 2 chip solution in price range $20 is > possible > but one chip one is harder Getting to $20 range without external phy with pipe interface is almost impossible currently I would say, even with big volumes. And x4 softcore and user transaction logic takes considerable space from the FPGA. > but that the real life is still a little different, yesterday it > looked > that cheapes FPGA with PCIe cost 240$ ? (arria) > hm maybe some virtex is cheaper than arria Everything depends on volumes... I would say that small V5LXT might be the best match, using the PCIe hardcore to save space. Another option depending on the schedule might be ArriaIIGX, it has also integrated PCIe endpoint. S6 might not be that good match, because it has only x1 hard PCIe EP. In the original message there is some kind of mixup, it speaks about 4x PCIe, but 8 lanes, or did he want 2*4x PCIe. 4xPCIe with lowcost FPGAs might also be quite challenging design. --KimArticle: 141641
OpenCores continues to grow rapidly and we are pleased to announce that we have just passed 50,000 registered users. We have also noticed a large increase in activity on the site, in both downloading cores/ projects and creation of new cores/projects. Check out the latest newsletter from OpenCores with the link below: http://www.opencores.org/?do=newsletter&2009=06Article: 141642
The OpenCores-team wants to define and start a new multimedia project pursued within the OpenCores community. The long term goal is to be able to support various multimedia standards and products by expanding our collection of media IP cores. Read more here: http://opencores.org/?do=newsletter&2009=06#n3Article: 141643
Hi, guys, I have been several years experience on FPGA networking application design, but I come up with the a question about math operation in FPGA. I need to perform Integral operation. I don't know if there is existing library which offer this function, or DSP? I think the last option is to run the integral library in the embedded PowerPC in Xilinx FPGA, but don't know how the performance is. Could anybody indicate how to achieve this goal? Many thanks, YixuanArticle: 141644
On Jul 2, 7:59=A0am, Simon <wlpstx...@gmail.com> wrote: > Hi, guys, > > I have been several years experience on FPGA networking application > design, but I come up with the a question about math operation in > FPGA. I need to perform Integral operation. I don't know if there is > existing library which offer this function, or DSP? I think the last > option is to run the integral library in the embedded PowerPC in > Xilinx FPGA, but don't know how the performance is. Could anybody > indicate how to achieve this goal? > > Many thanks, > > Yixuan An integral using continuous variables is essentially a multiply operation with a continuous sum performed by an "integrator" circuit. When using discrete time variable in digital logic, the multiply is straight forward and often omitted since that is just a scale factor and can be done elsewhere. The sum is now discrete and is a simple matter of a continuous accumulation using an... accumulator. If you can provide some details of your signal and exactly what you want to do, maybe we can give some additional advice? RickArticle: 141645
On Jul 2, 7:16=A0am, OC-team <marcus.erlands...@gmail.com> wrote: > The OpenCores-team wants to define and start a new multimedia project > pursued within the OpenCores community. The long term goal is to be > able to support various multimedia standards and products by expanding > our collection of media IP cores. > > Read more here: =A0http://opencores.org/?do=3Dnewsletter&2009=3D06#n3 I would ask that you change your page layout so that it does not require a screen width of 1400 pixels to be able to view it without panning right and left. I thought that it was standard to layout the page so that it will adapt to the width of the browser window? To be honest, this would help your advertisers since I currently pan right so that all the ads on the left side of the screen are not viewable. RickArticle: 141646
On Jul 2, 3:35=A0pm, rickman <gnu...@gmail.com> wrote: > On Jul 2, 7:16=A0am, OC-team <marcus.erlands...@gmail.com> wrote: > > > The OpenCores-team wants to define and start a new multimedia project > > pursued within the OpenCores community. The long term goal is to be > > able to support various multimedia standards and products by expanding > > our collection of media IP cores. > > > Read more here: =A0http://opencores.org/?do=3Dnewsletter&2009=3D06#n3 > > I would ask that you change your page layout so that it does not > require a screen width of 1400 pixels to be able to view it without > panning right and left. =A0I thought that it was standard to layout the > page so that it will adapt to the width of the browser window? > > To be honest, this would help your advertisers since I currently pan > right so that all the ads on the left side of the screen are not > viewable. > > Rick Hi Rick, I think ORSOC.SE is only fishing for customers from companies where company does not allow any displays to be used with less than 1600 pixels horisontal resolution. so the ORSOC ADVERTIZEMENTS are targeted properly AnttiArticle: 141647
Hi guys, I am working on a project where a need to map a given vhdl code into adders and multipliers. On generating the edif netlist using synplify, I get the instances in the form of gates. I tried setting syn_netlist_hierarchy attribute in sdc file, to generate a hierarchical netlist, but it didnt help. Is it possible to do it by writing libraries which are used for the technology mapping. How can that be done?Article: 141648
Hi How we will convert I/O pads in ASIC to FPGA ( Virtex-5 ). If we have around 200 I/O pads how will do . Pls give me some reference reading for this conversion. THanks PradeepArticle: 141649
Hi everybody, I have to develop in quite a short time a quite complicated USB IP core. Can any body advice me which books to buy? I began studying the USB2.0 spec but as you understand it's a spec and it's quitly complicated to read for a newcomer Thanks in advance!
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