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On Jul 3, 3:46 pm, "MM" <mb...@yahoo.com> wrote: > "rickman" <gnu...@gmail.com> wrote in message > > news:7c6c7876-8296-41e1-8ec9-b2a13f6da403@a36g2000yqc.googlegroups.com... > On Jul 3, 1:47 pm, "MM" <mb...@yahoo.com> wrote: > > > > >I have not seen anything about points on LinkedIn. I think the only > >way to "improve" your image at LinkedIn is what you put in your > >profile. LinkedIn does not rate anyone that I am aware of. > > >I think you may be remembering a different site than LinkedIn. They > >don't limit the time to reply to a discussion and I am not a paid > >member and I can send private messages. If I could find you, I would > >send you a private message to demonstrate, but there are a lot of > >Mikhails on LinkedIn. > > I should have put points in quote marks. There is no rating, but there is an > option to see all the answers by a person. I am not confusing LinkedIn with > another site but I might be confusing discussions in its groups with its > Answers section though. With regards to the private mail, it seems as they > have recently changed their policy. It used to be that you could only send a > message to someone in your network, for anyone else the only type of message > you could send was an invitation to join your network. > > /Mikhail I believe you are correct about the change. I don't use it that often so I don't recall all the details, but I seem to recall that when I tried to contact someone a while back I had to "invite" them to my network. Fortunately that has changed now. I'm not at all familiar with the Answers section. I guess I just have not explored it a lot. I find the interface to be a bit less than obvious, but then I think that about a lot of web sites like Facebook and Twitter. For example, I can't find a way to reach a human at Twitter to report spam to or to ask to block emails to my domain. I keep getting form emails back about using their support web pages. I guess I will have to resort to the post office. Speaking of Twitter, I got some spam (an invitation to join as one of their "twits") from someone there and I can't find a way to report them. There used to be a law here in Maryland that would allow you to sue a spammer for $500 for each email they knowingly sent to a Maryland state resident. A guy decided to fight back by taking an email address at <marylandstateresident.com> and started suing spammers. He snared a couple of small time spammers selling BS assembly projects that you could assemble and then get paid for. Of course no one ever made them good enough to get through "quality control". Then a spammer fought back and won in court with the ruling that it would be next to impossible for a spammer to "know" he was spamming a Maryland state resident. Otherwise participation by the State Attorney General is required in order to sue a spammer if I understand the current law. RickArticle: 141701
luudee wrote: > This should probably go in to the funny error messages folder: > > =============== (running make bits within xps) =============== > ChipScope Core Generator command: coregen -b > /home/rudi/reference_designs/ml507_satah/implementation/ > chipscope_icon_0_wrapper > /implementation/chipscope_ila_0.xco > ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx > CORE > Generator K.39 (lin64) > Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. > All runtime messages will be recorded in > /home/rudi/reference_designs/ml507_satah/implementation/ > chipscope_icon_0_wrap > per > /implementation/chipscope_ila_0_wrapper/coregen.log > Regenerating IP... > Gathering HDL files for chipscope_ila_0 root... > Creating XST project for chipscope_ila_0... > Creating XST script file for chipscope_ila_0... > Creating XST instantiation file for chipscope_ila_0... > Running XST for chipscope_ila_0... > Not generating a VHDL simulation model > Not generating a Verilog simulation model > Skipping VHDL instantiation template for chipscope_ila_0... > Skipping Verilog instantiation template for chipscope_ila_0... > Finished Regenerating. > Successfully generated chipscope_ila_0. > WARNING: verilog is not supported as a language. Using usenglish. > while executing > "error $errMsg" > (procedure "::hw_chipscope_ila_v1_02_a::ila_generate" line 121) > invoked from within > "::hw_chipscope_ila_v1_02_a::ila_generate 94898336" > ERROR:MDT - platgen failed with errors! > make: *** [implementation/sata_host.bmm] Error 2 > Done! > ================================================================ > > This is on the Latest Fedora (11) release, x86_64. > > Anybody knows where this error is coming from ? Didn't have that > on previous Fedora releases ... > A message like this is coming from a language localization routine. It looks like ChipScope core generator is being called from within EDK and somehow verilog was passed as the local language selection instead of an accepted value. Ed McGettigan -- Xilinx Inc.Article: 141702
"The Lord of War" <maa105.aub@gmail.com> wrote in message news:c7ednaKS573X9NPXnZ2dnUVZ_oidnZ2d@giganews.com... > >"The Lord of War" <maa105.aub@gmail.com> wrote in message >>news:lIqdnYYs39EeWtDXnZ2dnUVZ_sGdnZ2d@giganews.com... >>> eh no for what no for I cant use the sram that is onboard or no I have > to >>> do some fancy stuff and calls to be able to use them? and if so what do > i >>> need to do? >> >>No, the fpga doesn't of itself know about the board. It doesn't know > about >>the devices on the board. And it doesn't know the minutiae of operation > of >>the devices on the board. >> >>As to what to do, it depends on what you're trying to do. An embedded > system >>can use the Xilinx EDK to interface with the device, attach it to the >>peripheral bus, assign it room in the memory space, and build drivers to > >>access and control the device from software. For a hardware only > solution, >>start with the device's datasheet, and build the interface circuitry in > the >>fpga. The "process" you can "call" to work with the device might already > >>exist. They're more generally referred to as IP Cores. I expect you'll > find >>the required IP Cores in the Xilinx tools. >> >>"Fancy stuff" on the fpga is more properly thought of as describing and >>connecting circuitry. It is not software "calls" using a strange new >>programming language. I hope you'll find that distinction helpful. >> >> >> > > I dont know but maybe (or definitely) you guys are way more advanced than > me that's why I'm getting nothing, so to be clear I have an fpga board on > it is the virtex 4 and lots of other chips including an sram module and a > flash (scan disk) and something called linear flash all this is on the > SAME > board as the FPGA and what I'm trying to do is to use these modules to > save > information temporarily, so I need to save data in the sram (the one > ONboard) to be able to use later. I'm using VHDL to code my project, and > my > question is; HOW can I use these resources which are on the same board. > > please help the declaring big array did not work. > any tutorials or sample code is greatly appreciated > > thanks a lot guys and best of regards It sounds like the ML405 board. www.xilinx.com is where I would look first for sample code and tutorials. You'll find there as many application notes and documents as you would care to read. The memory manufacturers' websites will also have vitally useful information. With that said, I think it's way too much all at once to tackle as a first effort. If you care to, back up a few steps, tell us what you're doing and why, and what your expectations are. If it's a school project, stick with their program, of course. But, if you're on your own, maybe someone here can suggest a more reasonable progression to get you rolling. It won't be a short journey, but you might find it more satisfying and worthwhile than immediate gratification on your near term goal.Article: 141703
On Jul 4, 8:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > luudee wrote: > > This should probably go in to the funny error messages folder: > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D (running make bits within= xps) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > ChipScope Core Generator command: coregen -b > > /home/rudi/reference_designs/ml507_satah/implementation/ > > chipscope_icon_0_wrapper > > /implementation/chipscope_ila_0.xco > > ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx > > CORE > > =A0 =A0Generator K.39 (lin64) > > =A0 =A0Copyright (c) 1995-2008 Xilinx, Inc. =A0All rights reserved. > > =A0 =A0All runtime messages will be recorded in > > =A0 =A0/home/rudi/reference_designs/ml507_satah/implementation/ > > chipscope_icon_0_wrap > > =A0 =A0per > > =A0 =A0/implementation/chipscope_ila_0_wrapper/coregen.log > > =A0 =A0Regenerating IP... > > =A0 =A0Gathering HDL files for chipscope_ila_0 root... > > =A0 =A0Creating XST project for chipscope_ila_0... > > =A0 =A0Creating XST script file for chipscope_ila_0... > > =A0 =A0Creating XST instantiation file for chipscope_ila_0... > > =A0 =A0Running XST for chipscope_ila_0... > > =A0 =A0Not generating a VHDL simulation model > > =A0 =A0Not generating a Verilog simulation model > > =A0 =A0Skipping VHDL instantiation template for chipscope_ila_0... > > =A0 =A0Skipping Verilog instantiation template for chipscope_ila_0... > > =A0 =A0Finished Regenerating. > > =A0 =A0Successfully generated chipscope_ila_0. > > =A0 =A0WARNING: verilog is not supported as a language. =A0Using usengl= ish. > > =A0 =A0 =A0 =A0while executing > > =A0 =A0"error $errMsg" > > =A0 =A0 =A0 =A0(procedure "::hw_chipscope_ila_v1_02_a::ila_generate" li= ne 121) > > =A0 =A0 =A0 =A0invoked from within > > =A0 =A0"::hw_chipscope_ila_v1_02_a::ila_generate 94898336" > > ERROR:MDT - platgen failed with errors! > > make: *** [implementation/sata_host.bmm] Error 2 > > Done! > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > This is on the Latest Fedora (11) release, x86_64. > > > Anybody knows where this error is coming from ? Didn't have that > > on previous Fedora releases ... > > A message like this is coming from a language localization routine. > > It looks like ChipScope core generator is being called from within EDK > and somehow verilog was passed as the local language selection instead > of an accepted value. > > Ed McGettigan > -- > Xilinx Inc. Hi Ed, thanks for your reply. I investigated it a bit further. If I run "coregen -b /home/rudi/reference_designs/ml507_satah/implementation/ chipscope_icon_0_wrapper" from the terminal, it completes without an error. In my environment, I have a variable "LANGUAGE" that is set to an empty string. If I unset it, before starting xps, everything completes without an error. I did a search for that, and it appears to have been a minor bug in the xilinx tools since about ISE 7. Best Regards, luudeeArticle: 141704
On Jul 2, 5:53=A0pm, OC-team <marcus.erlands...@gmail.com> wrote: > OpenCores continues to grow rapidly and we are pleased to announce > that we have just passed 50,000 registered users. We have also noticed > a large increase in activity on the site, in both downloading cores/ > projects and creation of new cores/projects. > > Check out the latest newsletter from OpenCores with the link below:http:/= /www.opencores.org/?do=3Dnewsletter&2009=3D06 I wonder how many of those "new registered users" are students that have to sign up as part of a curse work, and will never login in again. What would be more interesting, would be to know how many *active* participants there really are. And with active I mean people who log in at least 3 times per week and upload project files. I would also filter out the "active users" that only participate in the forum discussions. I get about a million hits to my web site every months, but I guess half of those hits are looking for the shoe company "asics" ... Cheers, luudeeArticle: 141705
On Jul 4, 8:09=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > On Jul 2, 5:53=A0pm, OC-team <marcus.erlands...@gmail.com> wrote: > > > OpenCores continues to grow rapidly and we are pleased to announce > > that we have just passed 50,000 registered users. We have also noticed > > a large increase in activity on the site, in both downloading cores/ > > projects and creation of new cores/projects. > > > Check out the latest newsletter from OpenCores with the link below:http= ://www.opencores.org/?do=3Dnewsletter&2009=3D06 > > I wonder how many of those "new registered users" are students > that have to sign up as part of a curse work, and will never > login in again. > > What would be more interesting, would be to know how many > *active* participants there really are. And with active I mean > people who log in at least 3 times per week and upload project > files. I would also filter out the "active users" that only > participate in the forum discussions. > > I get about a million hits to my web site every months, but I > guess half of those hits are looking for the shoe company "asics" ... > > Cheers, > luudee ORSOC will only publish BIG marketing numbers, like 50.000 the number of active projects, where number of _weekly_ changes to IP sources is more then 3 times well, I would be surprised if that number would be above 25 it is possible to confirm that if somebody makes some script to analyze the complete svn data hm, 25:50000 is 1:2000 sounds about right, well maybe 25 is too much and should be less ;) AnttiArticle: 141706
Sadly I'm on my own, and what I'm trying to do is sample an analog signal save is in digital form in some kind of buffer (here comes the sram role) and then read it back after some time and convert it back to analog, thus producing a delay that can be controlled. and I need to do long delays so I nee a big buffer or memory. I checked the xilinx website there is no mention on the use of the onboard ram, so if any one have a lead on the subject please help, I need to know HOW to do this, a tutorial is good too. I'll keep searching and I'll post if I find anything new. regardsArticle: 141707
Here are some interesting statistics: I counted a total of - 457 Projects - 12 are NEW (not so bad !) BUT, only 127 (about 1/3) are completed ! Some of the not completed more than 5 years old ... luudeeArticle: 141708
>On Jul 2, 11:08 pm, "Sundar S" <krishna....@gmail.com> wrote: >> >On Jul 2, 7:59=A0am, Simon <wlpstx...@gmail.com> wrote: >> >> Hi, guys, >> >> >> I have been several years experience on FPGA networking application >> >> design, but I come up with the a question about math operation in >> >> FPGA. I need to perform Integral operation. I don't know if there is >> >> existing library which offer this function, or DSP? I think the last >> >> option is to run the integral library in the embedded PowerPC in >> >> Xilinx FPGA, but don't know how the performance is. Could anybody >> >> indicate how to achieve this goal? >> >> >> Many thanks, >> >> >> Yixuan >> >> >An integral using continuous variables is essentially a multiply >> >operation with a continuous sum performed by an "integrator" circuit. >> >When using discrete time variable in digital logic, the multiply is >> >straight forward and often omitted since that is just a scale factor >> >and can be done elsewhere. The sum is now discrete and is a simple >> >matter of a continuous accumulation using an... accumulator. >> >> >If you can provide some details of your signal and exactly what you >> >want to do, maybe we can give some additional advice? >> >> >Rick >> >> Integration is not just about summation of the discrete values. It could >> also mean finding the area of the region encompassed by the given numbers >> in Cartesian coordinates. Yixuan, if that's what you are looking for, you >> may have to implement some adaptive quadrature algorithm. >> The simplest way is to calculate the area as the curve builds for each and >> every clock signal. Assuming that clock goes at the rate of one unit in >> x-axis, you would need to evaluate int(n) = int(n-1) + 0.5 * diff(f(n), >> f(n-1)) + min(f(n), f(n-1)), where f(n) is your function value at the nth >> clock. >> >> http://sunnyeves.blogspot.com/ > >That calculation looks complex, but isn't it really just > >int(n) = int(n-1) + 0.5 * (f(n) - f(n-1)) > >The 0.5 times the difference assumes that the function is a straight >line between the two end points and when added to the min value is >just the average of the two points. This is an approximation, but >depending you your needs will be adequate. > >I would argue that for an arbitrary function, there is no advantage to >using the average of each two points over just summing the points. >Consider points 0 to N where N is a large number. > >N >< f(n) = f(1) + f(2) + ... + f(N) >< >1 > >N >< avg(f(n),f(n-1) = 0.5 f(0) + f(1) + f(2) + ... + 0.5 * f(N) >< >1 > >Notice that the only difference is that the average needs an extra >input point to calculate the first average and that the two end points >of the summation are halved. Numerically the difference between the >two calculations is 0.5 * (f(n) - f(0)). It appears to me to be a >very minuscule error to just add all the points without the complexity >of averaging. I would bet that for any value of N, 256 or over, this >error in the integral is much less than the error you get by the >original straight line average approximation. > >In fact, whether you the average is correct or not depends on how you >picture the error formation. This is too complex to draw here, but if >you picture the sample as being centered in the region being >integrated by adding that value, then the error is only a function of >the second order components of f(x). To require an average >calculation you are assuming that the area being calculated for a >given point is the area *between* two points. > >I could explain this more fully, but it is very hard to do without a >drawing. > > >Rick > @Rick, 0.5 * (f(n) - f(0)) is the straight line approximation of the entire function. It gives the area of a triangle with base equal to 1 and height equals to f(n) - f(0). But that's not the actual area as f(0) is somewhere hanging above x-axis. So we have to consider the square that is formed between the zeroth position and nth position so that you can get area below the curve. The calculation that I put up look complex, but if I assume that f(n) > f(n-1), what I get is: for every clock tic: int(n) = int(n-1) + (f(n) - f(n-1))>> 1 + f(n). Here as the curve grows by unit distance, the area is calculated as the area of the rising triangle plus the area of the rectangle that supports the triangle above x-axis. @Yixuan, You gave a vital information by telling that you use quadl of Matlab. quadl is actually an implementation of lobatto quadrature. Implementing that in FPGA may be really difficult. But what lobatto gives as output is the area under the curve with certain approximation. In FPGA that approximation anyway comes in terms of discretisation. Also in FPGA you would not get a function to integrate; you usually get the values of the function. In this case, the triangle-rectangle method would do. http://sunnyeves.blogspot.com/Article: 141709
On Jul 4, 3:19=A0am, "The Lord of War" <maa105....@gmail.com> wrote: > Sadly I'm on my own, and what I'm trying to do is sample an analog signal > save is in digital form in some kind of buffer (here comes the sram role) > and then read it back after some time and convert it back to analog, thus > producing a delay that can be controlled. and I need to do long delays so= I > nee a big buffer or memory. I checked the xilinx website there is no > mention on the use of the onboard ram, so if any one have a lead on the > subject please help, I need to know HOW to do this, a tutorial is good to= o. > I'll keep searching and I'll post if I find anything new. > > regards Maybe I missed something, but what board are you using? Are you asking for help with the board you have or ZBT ram in general, or are you asking for help with the HDL? Or maybe all three? RickArticle: 141710
On Fri, 03 Jul 2009 09:28:49 -0700, Mike Treseler <mtreseler@gmail.com> wrote: >MM wrote: > >> Sometimes "recompile all modules" may not work first time if the order of >> compilation has not been set properly. > >With vhdl-mode, > >right-click, Speedbar, Generate Makefile >right-click, Speedbar, Make > >does the trick. because VHDL sources contain all the information necessary to determine the (or rather, a ) correct order of compilation, and vhdl-mode simply translates it. There is really no excuse for other tools being unable to do the same. (Mixed language projects may be another matter) - BrianArticle: 141711
On Jul 4, 4:50 am, "Sundar S" <krishna....@gmail.com> wrote: > >On Jul 2, 11:08 pm, "Sundar S" <krishna....@gmail.com> wrote: > >> >On Jul 2, 7:59=A0am, Simon <wlpstx...@gmail.com> wrote: > >> >> Hi, guys, > > >> >> I have been several years experience on FPGA networking application > >> >> design, but I come up with the a question about math operation in > >> >> FPGA. I need to perform Integral operation. I don't know if there > is > >> >> existing library which offer this function, or DSP? I think the > last > >> >> option is to run the integral library in the embedded PowerPC in > >> >> Xilinx FPGA, but don't know how the performance is. Could anybody > >> >> indicate how to achieve this goal? > > >> >> Many thanks, > > >> >> Yixuan > > >> >An integral using continuous variables is essentially a multiply > >> >operation with a continuous sum performed by an "integrator" circuit. > >> >When using discrete time variable in digital logic, the multiply is > >> >straight forward and often omitted since that is just a scale factor > >> >and can be done elsewhere. The sum is now discrete and is a simple > >> >matter of a continuous accumulation using an... accumulator. > > >> >If you can provide some details of your signal and exactly what you > >> >want to do, maybe we can give some additional advice? > > >> >Rick > > >> Integration is not just about summation of the discrete values. It > could > >> also mean finding the area of the region encompassed by the given > numbers > >> in Cartesian coordinates. Yixuan, if that's what you are looking for, > you > >> may have to implement some adaptive quadrature algorithm. > >> The simplest way is to calculate the area as the curve builds for each > and > >> every clock signal. Assuming that clock goes at the rate of one unit > in > >> x-axis, you would need to evaluate int(n) = int(n-1) + 0.5 * > diff(f(n), > >> f(n-1)) + min(f(n), f(n-1)), where f(n) is your function value at the > nth > >> clock. > > >>http://sunnyeves.blogspot.com/ > > >That calculation looks complex, but isn't it really just > > >int(n) = int(n-1) + 0.5 * (f(n) - f(n-1)) > > >The 0.5 times the difference assumes that the function is a straight > >line between the two end points and when added to the min value is > >just the average of the two points. This is an approximation, but > >depending you your needs will be adequate. > > >I would argue that for an arbitrary function, there is no advantage to > >using the average of each two points over just summing the points. > >Consider points 0 to N where N is a large number. > > >N > >< f(n) = f(1) + f(2) + ... + f(N) > >< > >1 > > >N > >< avg(f(n),f(n-1) = 0.5 f(0) + f(1) + f(2) + ... + 0.5 * f(N) > >< > >1 > > >Notice that the only difference is that the average needs an extra > >input point to calculate the first average and that the two end points > >of the summation are halved. Numerically the difference between the > >two calculations is 0.5 * (f(n) - f(0)). It appears to me to be a > >very minuscule error to just add all the points without the complexity > >of averaging. I would bet that for any value of N, 256 or over, this > >error in the integral is much less than the error you get by the > >original straight line average approximation. > > >In fact, whether you the average is correct or not depends on how you > >picture the error formation. This is too complex to draw here, but if > >you picture the sample as being centered in the region being > >integrated by adding that value, then the error is only a function of > >the second order components of f(x). To require an average > >calculation you are assuming that the area being calculated for a > >given point is the area *between* two points. > > >I could explain this more fully, but it is very hard to do without a > >drawing. > > >Rick > > @Rick, > 0.5 * (f(n) - f(0)) is the straight line approximation of the entire > function. It gives the area of a triangle with base equal to 1 and height > equals to f(n) - f(0). But that's not the actual area as f(0) is somewhere > hanging above x-axis. So we have to consider the square that is formed > between the zeroth position and nth position so that you can get area below > the curve. > > The calculation that I put up look complex, but if I assume that f(n) > > f(n-1), what I get is: for every clock tic: int(n) = int(n-1) + (f(n) - > f(n-1))>> 1 + f(n). Here as the curve grows by unit distance, the area is > calculated as the area of the rising triangle plus the area of the > rectangle that supports the triangle above x-axis. I understand perfectly your original calculations. They are not complex to understand. However, they are much more complex than required. That is why I made my post explaining how in the infinite series, your approach approximates the simple sum of the input values. The only difference is that your approach can only produce (N-1) output values for N input values and as a consequence, the final output will not include the area of one column because you are always subtracting out the first one. Your approach errs in the thinking that the area is defined by the points "surrounding" the area. What it is ignoring that the points are *included* in the area. I suppose that initial int(0) could be accounting for this somehow, without specifying how that initialization is to be done. I made a typo in my original equation which is equivalent to your more complex calculation. int(n) = int(n-1) + 0.5 * (f(n) - f(n-1)) should have been int(n) = int(n-1) + 0.5 * (f(n) + f(n-1)) If you need me to, I can show you in a step wise manner how this is equivalent to your equation, int(n) = int(n-1) + 0.5 * diff(f(n), f(n-1)) + min(f(n), f(n-1)) Other than the end points of a series, your equation adds in half of each data point at two separate times. So each point is summed to produce the integral. Your calculation simply omits half of each end point. The mistake that is often made when dealing with discrete time samples is thinking that they are the same as the instantaneous values of a continuous function. In reality they are already integrals of the amplitude and the sample period (1/f). That is why you only need to sum them to obtain the integral over a series. A simple sum is the correct way to calculate the integral of a discrete time data series. RickArticle: 141712
On Jul 4, 4:26=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > Here are some interesting statistics: > > I counted a total of > > - 457 Projects > - 12 are NEW (not so bad !) > > BUT, only 127 (about 1/3) are completed ! Some of the > not completed more than 5 years old ... > > luudee That is the single biggest issue with oc.org that I find, separating the wheat from the chaff. Antti started on an effort to document processor cores. In fact, I think I owe him a reply on that topic. RickArticle: 141713
On Jul 4, 7:19=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Fri, 03 Jul 2009 09:28:49 -0700, Mike Treseler <mtrese...@gmail.com> w= rote: > >MM wrote: > > >> Sometimes "recompile all modules" may not work first time if the order= of > >> compilation has not been set properly. > > >With vhdl-mode, > > >right-click, Speedbar, Generate Makefile > >right-click, Speedbar, Make > > >does the trick. > > because VHDL sources contain all the information necessary to determine t= he (or > rather, a ) correct order of compilation, and vhdl-mode simply translates= it. > > There is really no excuse for other tools being unable to do the same. > > (Mixed language projects may be another matter) > > - Brian The Lattice software has a mode of compiling that evaluates the order to compile the modules and remembers it for subsequent builds. That was not an issue with my build. I was just restarting my simulation before I recompiled. RickArticle: 141714
On Jul 4, 3:11=A0pm, rickman <gnu...@gmail.com> wrote: > On Jul 4, 4:26=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > > > Here are some interesting statistics: > > > I counted a total of > > > - 457 Projects > > - 12 are NEW (not so bad !) > > > BUT, only 127 (about 1/3) are completed ! Some of the > > not completed more than 5 years old ... > > > luudee > > That is the single biggest issue with oc.org that I find, separating > the wheat from the chaff. =A0Antti started on an effort to document > processor cores. =A0In fact, I think I owe him a reply on that topic. > > Rick Hi Rick, I am still doing the "IP Core Report"... i have plenty of cores that are not so known hm, like X32! too bad i havent yet evaluated that one, it does execute LCC bytecode in hardware !! my evaluation in most cases is limited to the following 1) OotB Yes/No - if the design files pass synthesis/implementation "Out of the Box" i.e. WITHOUT HDL modifications (only minor tweaking is allowed like setting verilog include dir, etc..) 2) if I need to spend more than 30 minutes and FAIL to get the HDL code to pass synthesis, then my rank is "P o S" in this category is as example PIC10 IP core, it has NICE webpage and HDL code that just doesnt want to pass synthesis if implementation passes, i just recored the slice/lut/ff/bram then i add my commentary, etc etc.. AnttiArticle: 141715
I wonder to know how much guys that used to complain some free service, nevertheless did use and still are using that service cheers SandroArticle: 141716
Antti.Lukats@googlemail.com wrote: > I am still doing the "IP Core Report"... The draft that I have seen last time was very very interesting and encouraging. I hope that you can fill all the blanks in the near future, it can be a precious tool for many people. > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 141717
On Jul 4, 4:21=A0pm, Sandro <sdro...@netscape.net> wrote: > I wonder to know how much guys that used to complain some free > service, nevertheless did use and still are using that service > > cheers > Sandro Sandro WHO is complaining? and about what? has some one here said something about FREE IP cores, and/or developers? the FIRST post was PURE ADVERTIZEMENT (for ORSOC.SE) there are some replies, from two _contributors_ of opencores (luudee, Antti the later in much lesser degree but still) I am not sure if Rick has placed any of his ip cores to oc or not, but I'd say he is in any case entitled to spell our some critical views here. it leaves, that the one that is complaining is you sandro? spelling out things that could/should be improved isnt always "complaining"... AnttiArticle: 141718
>On Jul 4, 3:19=A0am, "The Lord of War" <maa105....@gmail.com> wrote: >> Sadly I'm on my own, and what I'm trying to do is sample an analog signal >> save is in digital form in some kind of buffer (here comes the sram role) >> and then read it back after some time and convert it back to analog, thus >> producing a delay that can be controlled. and I need to do long delays so= > I >> nee a big buffer or memory. I checked the xilinx website there is no >> mention on the use of the onboard ram, so if any one have a lead on the >> subject please help, I need to know HOW to do this, a tutorial is good to= >o. >> I'll keep searching and I'll post if I find anything new. >> >> regards > >Maybe I missed something, but what board are you using? Are you >asking for help with the board you have or ZBT ram in general, or are >you asking for help with the HDL? Or maybe all three? > >Rick > i'm using virtex 4 board 405/6 and on the board is a sram chip and it is ZBT, this sram is on the same board so I need not wire any external circuit since the sram module is on the same board, I'm coding using VHDL and all I need to know is HOW can I use this sram module -which is on the same board :). so HOW e.g. a function call or a built in library with some entity that uses the onboard ram or how can I access this ram?? (what do i need to do) thanks in advanceArticle: 141719
"The Lord of War" <maa105.aub@gmail.com> wrote in message news:4s-dneXSpOHjn9LXnZ2dnUVZ_v-dnZ2d@giganews.com... > Sadly I'm on my own, and what I'm trying to do is sample an analog signal > save is in digital form in some kind of buffer (here comes the sram role) > and then read it back after some time and convert it back to analog, thus > producing a delay that can be controlled. and I need to do long delays so > I > nee a big buffer or memory. I checked the xilinx website there is no > mention on the use of the onboard ram, so if any one have a lead on the > subject please help, I need to know HOW to do this, a tutorial is good > too. > I'll keep searching and I'll post if I find anything new. The help we give can only be as specific as the information you give us. We don't know the sample rate from your ADC; we don't know anything about your board; we don't know anything about the synchronous RAM on your board. Research this: Find the documentation for your board. Identify the memory device you are trying to read and write. Make note of what signals connect to the fpga. Identify the pins on the fpga that connect to the memory device. Find the documentation for the memory device. Make note of the functions of the signals connected to the fpga. Make note of the timing information. You will program the fpga to generate the signals to read and write the device. Begin forming in your mind the operations the fpga must perform to do this. You will read and write one or possibly more data words on each ADC sample. How many bits in a data sample? How many bits in a memory data word? Does the data sample fit in a memory word? Does the sample rate leave enough time to read one sample and write a new sample on each cycle? A ring buffer is suitable for use as a delay line. Define the delay time in terms of sample time. For each sample, read the old sample value, and overwrite it with the new sample. Advance to the next memory location. A modulo-N counter can be used to drive the memory address lines. It counts up to N-1 and then starts over at 0. The memory device has a number of control lines. What are their functions? What signals will you drive to read a memory location? What signals will you drive to write a memory location? The ADC sample rate will almost certainly be different from this circuit's clock rate. How will you signal the start of a sample period? Since you didn't ask about the ADC or DAC, I presume you have this part under control. The memory is only moderately more complex than reading and writing those other devices. You will also need a one time reset to initialize the ring buffer contents to an unobnoxious value. Alternatively, consider just not sending the garbage values read during the first delay cycle. I would go about building things in this order: Write the HDL for the modulo-N counter. Simulate and verify its operation. Add the memory control lines. Add this to the simulation and verify its operation. Write a testbench to generate data samples and simulate the memory device. Verify the module's operation in the simulator. Wire the module to your (presumably) already working ADC and DAC modules. Good luck.Article: 141720
On Jul 4, 5:58=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: >... > WHO is complaining? > and about what? > > has some one here said something about FREE IP cores, and/or > developers? noone said that... did I ? > > the FIRST post was PURE ADVERTIZEMENT (for ORSOC.SE) you are right > there are some replies, from two _contributors_ of opencores (luudee, > Antti the later in much lesser degree but still) me too... ( then at least three _contributors_ ;-) ) > I am not sure if Rick has placed any of his ip cores to oc or not, but > I'd say he is in any case entitled to spell our some critical views > here. noone said that... did I ? > > it leaves, that the one that is complaining is you sandro? yes... I'm complaining about people are complaining... then I'm complaining against myself too ;-) > > spelling out things that could/should be improved isnt always > "complaining"... right but... maybe wrong target! maybe is better to send an e-mail to the opencores mantainers... isn't ? Anyway I didn't want to hurt anyone... if I did then my sincere excuse SandroArticle: 141721
On Jul 4, 7:47=A0pm, Sandro <sdro...@netscape.net> wrote: > On Jul 4, 5:58=A0pm, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > >... > > WHO is complaining? > > and about what? > > > has some one here said something about FREE IP cores, and/or > > developers? > > noone said that... did I ? > > > > > the FIRST post was PURE ADVERTIZEMENT (for ORSOC.SE) > > you are right > > > there are some replies, from two _contributors_ of opencores (luudee, > > Antti the later in much lesser degree but still) > > me too... ( then at least three _contributors_ =A0;-) ) > > > I am not sure if Rick has placed any of his ip cores to oc or not, but > > I'd say he is in any case entitled to spell our some critical views > > here. > > noone said that... did I ? > > > > > it leaves, that the one that is complaining is you sandro? > > yes... I'm complaining about people are complaining... then > I'm complaining against myself too ;-) > > > > > spelling out things that could/should be improved isnt always > > "complaining"... > > right but... maybe wrong target! maybe is better to send > an e-mail to the opencores mantainers... isn't ? > > Anyway I didn't want to hurt anyone... > if I did then my sincere excuse > > Sandro welcome u r (I should have guessed, actually i assumed that 2->3 the very instant i posted..) it's not always possible to fix things in all places we see them, some times just "bringing" up the issue may help, as those who can (or should) fix the issue just arent aware of it. well unfortunatly it looks like all that orsoc wants to fix is the issue in their pockets. its a noble goal of course. 2 yg: yes, i think it will become something of a value itself the report, already seeing things i did not know (or wasnt so aware of) AnttiArticle: 141722
"The Lord of War" <maa105.aub@gmail.com> wrote in message news:yISdnXeWqNid4NLXnZ2dnUVZ_oednZ2d@giganews.com... > >On Jul 4, 3:19=A0am, "The Lord of War" <maa105....@gmail.com> wrote: >>> Sadly I'm on my own, and what I'm trying to do is sample an analog > signal >>> save is in digital form in some kind of buffer (here comes the sram > role) >>> and then read it back after some time and convert it back to analog, > thus >>> producing a delay that can be controlled. and I need to do long delays > so= >> I >>> nee a big buffer or memory. I checked the xilinx website there is no >>> mention on the use of the onboard ram, so if any one have a lead on > the >>> subject please help, I need to know HOW to do this, a tutorial is good > to= >>o. >>> I'll keep searching and I'll post if I find anything new. >>> >>> regards >> >>Maybe I missed something, but what board are you using? Are you >>asking for help with the board you have or ZBT ram in general, or are >>you asking for help with the HDL? Or maybe all three? >> >>Rick >> > > i'm using virtex 4 board 405/6 and on the board is a sram chip and it is > ZBT, this sram is on the same board so I need not wire any external > circuit since the sram module is on the same board, I'm coding using VHDL > and all I need to know is HOW can I use this sram module -which is on the > same board :). so HOW e.g. a function call or a built in library with some > entity that uses the onboard ram or how can I access this ram?? (what do i > need to do) Google on "zbt sram", among the first few hits: http://www.xilinx.com/support/documentation/application_notes/xapp136.pdf Also for the same search: http://www.opencores.org/?do=project&who=zbt_sram_controllerArticle: 141723
WOW thanks Mike I'll start working on that and update this post when I find new stuff. regards The Lord of WarArticle: 141724
"rickman" <gnuarm@gmail.com> wrote > > For example, I can't find a way to reach a human at Twitter Why on earth a grown man would want to use Twitter? :) /Mikhail
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