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On Jul 2, 6:18=A0am, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi everybody, > I have to develop in quite a short time a quite complicated USB IP > core. > Can any body advice me which books to buy? > I began studying the USB2.0 spec but as you understand it's a spec and > it's quitly complicated to read for a newcomer > > Thanks in advance! Take a look at http://www.beyondlogic.org/usbnutshell/usb1.htm This is a pretty good primer/reference. John ProvidenzaArticle: 141651
On Jul 2, 8:45=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 2, 3:35=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Jul 2, 7:16=A0am, OC-team <marcus.erlands...@gmail.com> wrote: > > > > The OpenCores-team wants to define and start a new multimedia project > > > pursued within the OpenCores community. The long term goal is to be > > > able to support various multimedia standards and products by expandin= g > > > our collection of media IP cores. > > > > Read more here: =A0http://opencores.org/?do=3Dnewsletter&2009=3D06#n3 > > > I would ask that you change your page layout so that it does not > > require a screen width of 1400 pixels to be able to view it without > > panning right and left. =A0I thought that it was standard to layout the > > page so that it will adapt to the width of the browser window? > > > To be honest, this would help your advertisers since I currently pan > > right so that all the ads on the left side of the screen are not > > viewable. > > > Rick > > Hi Rick, > > I think ORSOC.SE is only fishing for customers from companies > where company does not allow any displays to be used with less > than 1600 pixels horisontal resolution. > > so the ORSOC ADVERTIZEMENTS are targeted properly > > Antti Yeah, I think I detect a note of sarcasm... But honestly, I don't typically surf the web with my browser window taking up the entire screen! I do get your point though. What started out as a grassroots effort to share IP seems to have turned into a commercial venture. We'll see how well that works for them. I would draw a parallel to geocaching. This is a sport that requires nothing but a GPS to participate. It was started by an individual who used a newsgroup to invite others to participate. The idea was commercialized by groundspeak (geocaching.com) who runs the largest (by far) web site for sharing caching info. But geocaching.com has put the emphasis on inclusion and allowed quality to be sacrificed for quantity. Now there are literally 100's of thousands of caches around the world, but the vast majority of them are not really much fun to hunt. There are other, newer caching sites with an emphasis on quality rather than automatically including everyone. They are growing and if geocaching.com doesn't continue to serve the caching community, they may become the has-been of the caching community. I think there is a parallel to oc.com. They have taken a grassroots effort and are attempting to turn it to produce a profit. If they are not very careful about how they do that, they can lose the grassroots support and undermine their own organization. We'll see how successfully they manage this. RickArticle: 141652
This should probably go in to the funny error messages folder:
=============== (running make bits within xps) ===============
ChipScope Core Generator command: coregen -b
/home/rudi/reference_designs/ml507_satah/implementation/
chipscope_icon_0_wrapper
/implementation/chipscope_ila_0.xco
ERROR:MDT - chipscope_ila_0 (chipscope_ila) - Release 10.1 - Xilinx
CORE
Generator K.39 (lin64)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
All runtime messages will be recorded in
/home/rudi/reference_designs/ml507_satah/implementation/
chipscope_icon_0_wrap
per
/implementation/chipscope_ila_0_wrapper/coregen.log
Regenerating IP...
Gathering HDL files for chipscope_ila_0 root...
Creating XST project for chipscope_ila_0...
Creating XST script file for chipscope_ila_0...
Creating XST instantiation file for chipscope_ila_0...
Running XST for chipscope_ila_0...
Not generating a VHDL simulation model
Not generating a Verilog simulation model
Skipping VHDL instantiation template for chipscope_ila_0...
Skipping Verilog instantiation template for chipscope_ila_0...
Finished Regenerating.
Successfully generated chipscope_ila_0.
WARNING: verilog is not supported as a language. Using usenglish.
while executing
"error $errMsg"
(procedure "::hw_chipscope_ila_v1_02_a::ila_generate" line 121)
invoked from within
"::hw_chipscope_ila_v1_02_a::ila_generate 94898336"
ERROR:MDT - platgen failed with errors!
make: *** [implementation/sata_host.bmm] Error 2
Done!
================================================================
This is on the Latest Fedora (11) release, x86_64.
Anybody knows where this error is coming from ? Didn't have that
on previous Fedora releases ...
Thanks,
luudee
Article: 141653
On Jul 2, 3:13=A0pm, "designer_india" <pradeep...@gmail.com> wrote:
> Hi
>
> How we will convert I/O pads in ASIC to FPGA ( Virtex-5 ). If we have
> around 200 I/O pads how will do .
>
> Pls give me some reference reading for this conversion.
>
> THanks
> Pradeep
for each pad in {ASIC_io_pad} do {
Virtex5PAD vpad =3D new Virtex5PAD();
vpad =3D convertASIC2Virtex5(pad);
}
or BETTER http://www.xilinx.com/
;-)
Article: 141654I have written a PCIe module with 3 parameterized abilities. # of input paths, # of output paths, and # of interrupts. Each of these is controlled by a relevant NUM_xxx parameter in the top level pcie.v module. Currently the pcie.v module requires each of these values to be at least 1 due to how the module is built. For example the output and input paths data bits are declared each as: input [(NUM_INPUTS * 64) - 1:0] input_data, output [(NUM_OUTPUTS * 64) - 1:0] output_data, The interrupts are declared as input [NUM_INTERRUPTS - 1:0] interrupt I would like to be able to set any of these 3 parameters to 0, but I can't see how to generate the ports correctly. It would be very painful to split this module to 3 separate modules (input, output, interrupt) where each would be instantiated only if there was at least 1 instance of the desired type. I can think of many different hacks which would workaround this problem, for example always building the ports with at least 1 and just ignoring it, or some such things, but that seems ugly. I'm curious whether Verilog has the ability to use a generate / if statement in the top level ports which would be very helpful for this kind of situation? Thanx, nachumArticle: 141655
On Thu, 2 Jul 2009 08:42:01 -0700 (PDT), nachum wrote: >I'm curious whether Verilog has the ability to use a generate / if >statement in the top level ports which would be very helpful for this >kind of situation? No. You're right, it's tiresome. This has been raised in the SystemVerilog committees on more than one occasion, but there is no solution in sight at present. One of the mechanisms that has been suggested is exactly what you say: generate constructs in the module's port list. Personally I find that rather distasteful, but it may be the easiest way out. Don't hold your breath; the feature set for the 2009 standard was frozen some time ago, and we won't get another new version of (System)Verilog until around 2013 or 2014. In any case, it's a tricky problem; ports are strange beasts in the Verilog language, and using any kind of "generate" to control their existence is likely to have many awkward wrinkles. Sorry to be the bearer of bad news. At least, on this occasion, we can comfort ourselves that the situation is no better in VHDL :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141656
On Wed, 1 Jul 2009 15:04:26 -0700 (PDT), Brane2 <brankob@avtomatika.com> wrote: >So far, I have only been able to find Spartan6 ( which isn't really >available yet) from Xilinx and some small FPGA from Actel ( Igloo >family ?). > >Trouble is, Spartan has only two lanes, which is enough only for PCI-e >x1. >Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > >Is there anything else worth looking at ? > >I'm looking for chip with decent PCI-e interface ( say at least 8 >lanes for PCI-e x4 ) in the cost range $10-20 or so... What about buying a PCIe interface chip (say from PLX) and connecting that chip to your FGPA? Using the chip is one less thing to design and debug. -Dave PollumArticle: 141657
On Jul 2, 1:29=A0pm, Dave P <vze24...@verizon.net> wrote: > On Wed, 1 Jul 2009 15:04:26 -0700 (PDT), Brane2 <bran...@avtomatika.com> > wrote: > > >So far, I have only been able to find Spartan6 ( which isn't really > >available yet) from Xilinx =A0and some small FPGA from Actel ( Igloo > >family ?). > > >Trouble is, Spartan has only two lanes, which is enough only for PCI-e > >x1. > >Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > > >Is there anything else worth looking at ? > > >I'm looking for chip with decent PCI-e interface ( say at least 8 > >lanes for PCI-e x4 ) in the cost range $10-20 or so... > > What about buying a PCIe interface chip (say from PLX) and connecting tha= t > chip to your FGPA? =A0Using the chip is one less thing to design and debu= g. > -Dave Pollum Gennum also makes x1 and x4 interface chips. The PLX chip is actually a MCM with a PCIE/PCI bridge and a PCI/local bridge. You could also go with an IP core in a Spartan3, with an external PHY chip. DaveArticle: 141658
On Jul 2, 1:29=A0pm, Dave P <vze24...@verizon.net> wrote: > On Wed, 1 Jul 2009 15:04:26 -0700 (PDT), Brane2 <bran...@avtomatika.com> > wrote: > > >So far, I have only been able to find Spartan6 ( which isn't really > >available yet) from Xilinx =A0and some small FPGA from Actel ( Igloo > >family ?). > > >Trouble is, Spartan has only two lanes, which is enough only for PCI-e > >x1. > >Actel had more lanes- AFAIK enough for PCI-e x4, but was very small. > > >Is there anything else worth looking at ? > > >I'm looking for chip with decent PCI-e interface ( say at least 8 > >lanes for PCI-e x4 ) in the cost range $10-20 or so... > > What about buying a PCIe interface chip (say from PLX) and connecting tha= t > chip to your FGPA? =A0Using the chip is one less thing to design and debu= g. > -Dave Pollum Last time I checked, the PLX chips were not under $20 either...Article: 141659
In article <4a4bd06d$0$291$7a628cd7@news.club-internet.fr>, whygee <whygee@yg.yg> writes: |> |> Also, I've read that the Alta=EFr computer kit (was it this one ?) was |> once used to run a specific program that disturbed a close radio |> so music would be heard... No idea about the Altair, but I had a similar program on my ZX81/TS1000. RainerArticle: 141660
"Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com> writes: > I think ORSOC.SE is only fishing for customers from companies > where company does not allow any displays to be used with less > than 1600 pixels horisontal resolution. My display is 2560 pixels across, and I still have to scroll on that page. Why? Because I don't make my browser that wide. If I make the browser wide enough to not scroll, the text becomes difficult to read as the paragraph lines are too wide. Designing for a display size is stupid. You have to design for a readable size. The worst part of that page is that I *can't* make the paragraphs narrow enough to be easily readable.Article: 141661
On Jul 2, 3:04=A0pm, DJ Delorie <d...@delorie.com> wrote: > "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> writes: > > I think ORSOC.SE is only fishing for customers from companies > > where company does not allow any displays to be used with less > > than 1600 pixels horisontal resolution. > > My display is 2560 pixels across, and I still have to scroll on that > page. =A0Why? =A0Because I don't make my browser that wide. =A0If I make = the > browser wide enough to not scroll, the text becomes difficult to read > as the paragraph lines are too wide. > > Designing for a display size is stupid. =A0You have to design for a > readable size. =A0The worst part of that page is that I *can't* make the > paragraphs narrow enough to be easily readable. BINGO! That is exactly the issue I have often on *many* web pages (including Google Groups). Sometimes I think that web designers think the world revolves around them rather than revolving around FPGA designers... ;^) RickArticle: 141662
I have been using Active-HDL (AHDL) for over a year now and I am pretty happy with it. For one thing, it doesn't have the apparently unfix-able, tool crashing, memory leak that every version of Modelsim I have ever used seems to have. I find that as I go through the edit-compile-simulate cycle I use the toolbar buttons to 1) Restart the simulation, 2) recompile all modules 3) use a right click menu to clear the waveform display. But this mostly does not actually recompile the code or does not recompile it fully or does not use the recompiled code. After a source change I have to run around this cycle twice to get the new code to actually simulate. What am I missing? I find that if I *don't* recompile and try to run again, I get a dialog telling me the source is out of date and I can recompile if I want. If I say yes, it recompiles and *always* seems to do it correctly. I would say that was a clue, but I am not being Hercule Poirot today it seems. RickArticle: 141663
Have a look at the tool from Duolog called Bitwise. Is a commercial product http://www.duolog.com/ Gui that allows you enter register definition. You can then program the tool to generate anything you want. Examples with the tool generate VHDL CSR type code, Word documents and C header files. Very powerful and very quick to enter register definitions. Svenn Are Bjerkem wrote: > Hi, > > found two tools for Verilog which is supposed to keep documentation > and implementation of control and status registers in sync. Vregs on > www.veripool.com and csrGen.pl on asics.chuckbenz.com. (Actually > csrGen.pl was not downloadable due to an internal error, but the > documentation made it look interesting). I also found a commercial > tool from PDTi which is probably doing the same but I haven't got as > far as getting a demo license. > > So far the documentation of the register map is in Word. Many pages > with text and tables and functional description that needs to be kept > in sync. Currently a reorganization of this register map is happening > in OpenOffice calc to be able to see the bits and pieces of the > register map, and to be able to move them around. The VHDL code is > then modified manually according to the spreadsheet and the Word > document is then modified again. In the end the application programmer > is going to take that Word document and type a lot of #defines in his > C-files and I bet we will spend some weeks looking for those nasty > bugs that all this manual work will produce. The project is running on > an FPGA so it is too easy to just add registers and bits as new > features come up, or to move them when they doesn't fit the access > model of the application that is later going to access the registers > (via PCI) > > Vregs solves this problem by creating VHDL and C-headers from HTML > exported from a text processor that can export HTML. csrGen.pl will > take input from a definition file. I found both solutions charming, > except from the fact that they generate Verilog instead of VHDL, and > that one wasn't available anymore. > > I'm wondering how other VHDL programmers solve their CSR bookkeeping, > or maybe there is a tool out there that I haven't found. It doesn't > need to be open source, if it is any good we will buy it. From the > efforts by Wilson Snyder on Vregs I take that this is not a tool that > I can write overnight myself. Maybe it is portable since it is written > in perl, but Verilog and VHDL does think differently, and I am not a > perl savvy. (Can't even read my own code after six weeks) > > -- > SvennArticle: 141664
On Jul 2, 3:17=A0pm, rickman <gnu...@gmail.com> wrote: > I have been using Active-HDL (AHDL) for over a year now and I am > pretty happy with it. =A0For one thing, it doesn't have the apparently > unfix-able, tool crashing, memory leak that every version of Modelsim > I have ever used seems to have. > > I find that as I go through the edit-compile-simulate cycle I use the > toolbar buttons to 1) Restart the simulation, 2) recompile all modules > 3) use a right click menu to clear the waveform display. =A0But this > mostly does not actually recompile the code or does not recompile it > fully or does not use the recompiled code. =A0After a source change I > have to run around this cycle twice to get the new code to actually > simulate. > > What am I missing? =A0I find that if I *don't* recompile and try to run > again, I get a dialog telling me the source is out of date and I can > recompile if I want. =A0If I say yes, it recompiles and *always* seems > to do it correctly. > > I would say that was a clue, but I am not being Hercule Poirot today > it seems. > > Rick Don't know about AHDL, but in ModelSim you definitely need to do steps 1 and 2 in the reverse error to use the newly recompiled code. The last time I touched Aldec stuff was when Xilinx Foundation (4.1 and prior) had it bundled together. Regards, GaborArticle: 141665
rickman <gnuarm@gmail.com> wrote: >On Jul 2, 7:16 am, OC-team <marcus.erlands...@gmail.com> wrote: > >> Read more here: http://opencores.org/?do=newsletter&2009=06#n3 > > >I would ask that you change your page layout so that it does not >require a screen width of 1400 pixels to be able to view it without >panning right and left. OC-team, if you're actually reading this thread, I suggest that you edit your "main.css" file, and in lines 23 and 28 change "width: 1250px;", to something sensible like "width: 960px;". And while we're on the subject of open standards, check this out: http://960.gs/ -- Dave FarranceArticle: 141666
On Jul 2, 3:49=A0pm, gabor <ga...@alacron.com> wrote: > On Jul 2, 3:17=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I have been using Active-HDL (AHDL) for over a year now and I am > > pretty happy with it. =A0For one thing, it doesn't have the apparently > > unfix-able, tool crashing, memory leak that every version of Modelsim > > I have ever used seems to have. > > > I find that as I go through the edit-compile-simulate cycle I use the > > toolbar buttons to 1) Restart the simulation, 2) recompile all modules > > 3) use a right click menu to clear the waveform display. =A0But this > > mostly does not actually recompile the code or does not recompile it > > fully or does not use the recompiled code. =A0After a source change I > > have to run around this cycle twice to get the new code to actually > > simulate. > > > What am I missing? =A0I find that if I *don't* recompile and try to run > > again, I get a dialog telling me the source is out of date and I can > > recompile if I want. =A0If I say yes, it recompiles and *always* seems > > to do it correctly. > > > I would say that was a clue, but I am not being Hercule Poirot today > > it seems. > > > Rick > > Don't know about AHDL, but in ModelSim you definitely need to > do steps 1 and 2 in the reverse error to use the newly > recompiled code. =A0The last time I touched Aldec stuff was > when Xilinx Foundation (4.1 and prior) had it bundled together. > > Regards, > Gabor Duh! Now that you say that, I see how obvious that is. I guess pushing buttons makes it so easy to forget what is going on. I was thinking that restart the simulation was ending it and the compile would start the new one, but obviously "restart" means restart! Would have thought that would happen??? That is what happens when you don't use a tool for a few months. I do still remember which end of the hammer to hold... Thanks, RickArticle: 141667
On Jul 2, 6:18=A0am, GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi everybody, > I have to develop in quite a short time a quite complicated USB IP > core. > Can any body advice me which books to buy? > I began studying the USB2.0 spec but as you understand it's a spec and > it's quitly complicated to read for a newcomer > > Thanks in advance! I recommend "USB Architectuure" book from MindShare : http://www.amazon.com/Universal-Serial-Bus-System-Architecture/dp/020130975= 0/ref=3Dsr_1_1?ie=3DUTF8&s=3Dbooks&qid=3D1246572483&sr=3D1-1 - Evgeni http://OutputLogic.comArticle: 141668
On Mon, 29 Jun 2009 23:08:16 +0800, rickman wrote (in article <68320efd-477b-4818-95dd-d4639d7e2cd1@n19g2000vba.googlegroups.com>): > On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" > <Antti.Luk...@googlemail.com> wrote: >> On Jun 28, 5:09=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: >> >> >> >>> Group for People Involved In the Design and Verification of FPGA's, >>> other Programmable Logic , and CPLD's to Exchange Idea's and >>> Techniques. You should have FPGA / CPLD Design / Verification on your >>> Profile. (The focus is more on FPGA/CPLD in the product as opposed to >>> FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC >>> and other HDL's as well. Vendors included: Xilinx, Altera, Actel, >>> Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, >>> Synopsys, Aldec, NI, Altium, and Many Others. >> >>> Networking on LinkedIn can be a way to get technical questions >>> answered. It can also be a way to meet contacts with expertise in >>> other domains of knowledge other than your own. Additionally, many >>> career enhancing contacts, and mentors can potentially found >>> especially if one is at a smaller company that lacks the resources for >>> extensive internal networking. >> >>> http://www.linkedin.com/groups?about=3D&gid=3D56713 >> >>> Website:https://sites.google.com/site/fpgacpldgroup/ >> >> could you describe the last technical FPGA related question >> that your linkedin networking group solved? >> >> unless you are able todo that, i see you repeated postings >> to c.a.f. as complete spam >> >> Antti > > Hi, I am one of the moderators at this group and I must be honest > about it. It is not a very technically oriented group. I have tried > to make some technically oriented posts there with few responses. > This did not seem to stimulate much in the way of subsequent new > topics either. I have also made an effort to separate the technical > content from the recruiting content and gotten feedback that the > recruiters are the ones paying the way for LinkedIn and cutting them > out would be a mistake. > > So I have given up on this group as well as other FPGA related groups > at LinkedIn. I have not removed myself from membership, but I can't > say I recommend them unless you wish to use it for employment or self > promotion. > > Rick I'm completely confused as to how you can have a FPGA group that is not "technically orientated" , it would be like having a flower arranging class without the flowers.Article: 141669
hi all i'm new to the fpga field i was wondering how do i use the onboard sram, i need to create a big memory structure so do i just do: type dataout is array (0 to 1048576) of std_logic_vector(15 downto 0); signal mem_struct : dataout; and the fpga knows what to do and where to save the stuff and then use mem_struct as my memory structure or is there a way (a procedure) to use the onboard sram or flash for what matters. i hope i'm clear enough if it helps i am using virtex 4 xc4vfx20 and xilinx ise 9.2, and i have 512M scan disk flash and SRAM module (ZBT Synchronous SRAM) on the board itself thanks in advance regards The Lord of WarArticle: 141670
Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development
board. I am working on image filtering where I have to transfer the image
file to the SDRAM and then filter it by bring the data to the BRAM's. I am
struck off into following steps:
1. How can I send a whole image file to the SDRAM. I can put some data on
the SDRAM using the EDK C code which is as follows
#define XPS_MEM_RAM 0x60000000 // this was the starting address of the
SDRAM as
//provided by the EDK when I added it to my
system
Xuint32 *RAM;
RAM=XPS_MEM_RAM;
RAM[i]=0x12345678;
but how to send a full file... Also I am not sure whether the procedure i
followed is completely correct???
2.How can i bring my data(which is in SDRAM) to the BRAM. Can i add BRAM
to my EDK system as i added SDRAM... If so how??? I also tried to access
the SDRAM with VHDL code but it was quiet complicated. I also heard about
SDRAM controller but didn't found any for my SDRAM.
Please suggest me something for any of the two problems.
Article: 141671>On Jul 2, 7:59=A0am, Simon <wlpstx...@gmail.com> wrote: >> Hi, guys, >> >> I have been several years experience on FPGA networking application >> design, but I come up with the a question about math operation in >> FPGA. I need to perform Integral operation. I don't know if there is >> existing library which offer this function, or DSP? I think the last >> option is to run the integral library in the embedded PowerPC in >> Xilinx FPGA, but don't know how the performance is. Could anybody >> indicate how to achieve this goal? >> >> Many thanks, >> >> Yixuan > >An integral using continuous variables is essentially a multiply >operation with a continuous sum performed by an "integrator" circuit. >When using discrete time variable in digital logic, the multiply is >straight forward and often omitted since that is just a scale factor >and can be done elsewhere. The sum is now discrete and is a simple >matter of a continuous accumulation using an... accumulator. > >If you can provide some details of your signal and exactly what you >want to do, maybe we can give some additional advice? > >Rick Integration is not just about summation of the discrete values. It could also mean finding the area of the region encompassed by the given numbers in Cartesian coordinates. Yixuan, if that's what you are looking for, you may have to implement some adaptive quadrature algorithm. The simplest way is to calculate the area as the curve builds for each and every clock signal. Assuming that clock goes at the rate of one unit in x-axis, you would need to evaluate int(n) = int(n-1) + 0.5 * diff(f(n), f(n-1)) + min(f(n), f(n-1)), where f(n) is your function value at the nth clock. http://sunnyeves.blogspot.com/Article: 141672
"The Lord of War" <maa105.aub@gmail.com> wrote in message news:arGdnTDYRLmL69DXnZ2dnUVZ_vmdnZ2d@giganews.com... > hi all i'm new to the fpga field > > i was wondering how do i use the onboard sram, i need to create a big > memory structure so do i just do: > > type dataout is array (0 to 1048576) of std_logic_vector(15 downto 0); > signal mem_struct : dataout; > > and the fpga knows what to do and where to save the stuff and then use > mem_struct as my memory structure or is there a way (a procedure) to use > the onboard sram or flash for what matters. > > i hope i'm clear enough > > if it helps i am using virtex 4 xc4vfx20 and xilinx ise 9.2, and i have > 512M scan disk flash and SRAM module (ZBT Synchronous SRAM) on the board > itself > thanks in advance > > regards > The Lord of War Me personally, I find (1024 * 1024 - 1) more easily readable for intent, and small mistakes harder to miss. As to your question, simply: No, but it can be "taught". The beauty of a blank canvas is it doesn't presume to know the brush's intent.Article: 141673
eh no for what no for I cant use the sram that is onboard or no I have to do some fancy stuff and calls to be able to use them? and if so what do i need to do? thanksArticle: 141674
How can I tell Modelsim that when I right-click and choose Simulate it should automatically search certain libraries. For example I'm using Xilinx libs, and I need it to run like this: vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -lib work my_module glbl When I double click my_module for simulation, it runs: vsim work.my_module This causes all sorts of errors because it can't find the components needed. I understand how to get it to run by using a .do file, but I'd like to understand how to modify the modelsim.ini / mpf file or how to set Modelsim settings such that it automatically uses these parameters when double clicked. I also know that if I choose Simulate->Start Simulation I will have the option to add those parameters in, but that still doesn't help if I want a simple double-click to work. Thanx, nachum
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