Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I have forgotten to mention that the traces between the FPGA and the transceiver are routed as very loosely coupled traces where each trace has a 50 ohm characteristic impedance. Each trace is about 5 cm long. Best regards, JFArticle: 87876
Hallo, I am a newbie evaluating xilinx tools & FPGAs for our project.Our company traditionally uses altera.We have bought a j83 ac modulator IPcore from Xilinx.In the ISE I have implemented the design. Now the manual says I must import the EDIF netlist generated by ISE into a new project and use it as blackbox. I couldnt find any importing button in ISE to import EDIF netlist. I read some answers on xilinx website and this news groups.They simply say "import the netlist into ISE project". can anybody help me how to do it?What is file extension for EDIF netlist? Sorry if it is a trivial query. Thank you. Monica, Germany PS:I would like to use the modulator(IP core) and DUC(IP core) and interface them on top level.Article: 87877
JF, What sets the DC bias of the CML receiver? I.e. where R2 is. Syms. "jfh" <j-f.hasson@fr.thalesgroup.com> wrote in message news:1123057746.417694.225400@z14g2000cwz.googlegroups.com... > Hi, > > I have forgotten to mention that the traces between the FPGA and the > transceiver are routed as very loosely coupled traces where each trace > has a 50 ohm characteristic impedance. Each trace is about 5 cm long. > > Best regards, > > JF >Article: 87878
Monica schrieb am 03.08.2005 11:28: > Hallo, > > I am a newbie evaluating xilinx tools & FPGAs for our project.Our > company traditionally uses altera.We have bought a j83 ac modulator > IPcore from Xilinx.In the ISE I have implemented the design. > > Now the manual says I must import the EDIF netlist generated by ISE > into a new project and use it as blackbox. > > I couldnt find any importing button in ISE to import EDIF netlist. > > I read some answers on xilinx website and this news groups.They simply > say "import the netlist into ISE project". > > can anybody help me how to do it?What is file extension for EDIF > netlist? Du musst im HDL-Code für das Toplevel den Core wie jede andere Entity deklarieren und instanziieren. Durch die Instanziierung merkt ISE, dass dieser Core gebraucht wird. Wenn für diese Entity kein HDL-Quellcode im ISE-Projekt vorhanden ist, wird sie im "Project Workspace" mit einem Fragezeichen vorne markiert, und ISE versucht dann bei der Implementierung, eine Netzliste dafür nachzuladen. Dabei durchsucht es das aktuelle Verzeichnis und das, das im Projekt als "Macro Search Path" angegeben ist (den kann man in den Properties für den "Translate"-Schritt einstellen, das ist der Suchpfad für Netzlisten von IP-Cores), dort muss dann das EDF-File liegen. Also: EDIF-Netzliste ins Projektverzeichnis kopieren, Core im Toplevel instanziieren, den Rest macht ISE. cu, SeanArticle: 87879
Hi, R2 is inside the transceiver so I do not know how to answer this question. All i know is that normally everything inside the transceiver is taken care of so I do not have to worry about it (anyway I hope so !!!). Best regards, JF Symon a =E9crit : > JF, > What sets the DC bias of the CML receiver? I.e. where R2 is. > Syms. > "jfh" <j-f.hasson@fr.thalesgroup.com> wrote in message > news:1123057746.417694.225400@z14g2000cwz.googlegroups.com... > > Hi, > > > > I have forgotten to mention that the traces between the FPGA and the > > transceiver are routed as very loosely coupled traces where each trace > > has a 50 ohm characteristic impedance. Each trace is about 5 cm long. > > > > Best regards, > > > > JF > >Article: 87880
Brian Dam Pedersen wrote:
> Amir Tabatabaei wrote:
>
>> Thanks Brian, but
>
>> mkdir -p /lib/modules/2.6.12/kernel/drivers/misc
>> cp LINUX.2.6.12/windrvr6.ko /lib/modules/2.6.12/kernel/drivers/misc
>> ./wdreg windrvr6
>> FATAL: Error inserting windrvr6
>> (/lib/modules/2.6.12/kernel/drivers/misc/windrvr6.ko): Invalid module
>> formatmake: *** [install] Error 1
>>
> Hm. Normally this would indicate that the kernel version that the module
> is compiled for is not the one that is actually running.
Hello,
Note that the WinDriver software assumes a not too new gcc compiler.
I got it working with adding
CC = gcc-3.3
to the beginning of
WinDriver/redist/makefile
E.g. debian/unstable already uses gcc-4.0.
Greetings,
Sietse Achterop
Article: 87881Sean Durkin wrote: > Du musst im HDL-Code f=FCr das Toplevel den Core wie jede andere Entity > deklarieren und instanziieren. Durch die Instanziierung merkt ISE, dass > dieser Core gebraucht wird. Wenn f=FCr diese Entity kein HDL-Quellcode im > ISE-Projekt vorhanden ist, wird sie im "Project Workspace" mit einem > Fragezeichen vorne markiert, und ISE versucht dann bei der > Implementierung, eine Netzliste daf=FCr nachzuladen. Dabei durchsucht es > das aktuelle Verzeichnis und das, das im Projekt als "Macro Search Path" > angegeben ist (den kann man in den Properties f=FCr den > "Translate"-Schritt einstellen, das ist der Suchpfad f=FCr Netzlisten von > IP-Cores), dort muss dann das EDF-File liegen. > > Also: EDIF-Netzliste ins Projektverzeichnis kopieren, Core im Toplevel > instanziieren, den Rest macht ISE. > > cu, > Sean Hallo Sean, Vielen Dank.Thank you very much. regards, Grusse, MonicaArticle: 87882
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3l7hslF10tsq8U1@individual.net... > Brad Smallridge wrote: >> Up to now, I have been doing much of my work with ModelSim and >> a BMP file reader and writer. Most of my VHDL designs have clk >> and reset. I know where to attach the clk but what do I use for >> reset. An external pin? The Done pin? Or a DCM lock signal? > > I drive reset from a cpu running on > the fpga clock. Pulse it after the > binary image is loaded. > This is vendor independent > and synchronous. > -- Mike Treseler Mike, Do you then code that reset signal using the normal asynchronous reset at the start of a clocked process model, or do you code it as a synchronous reset? Or do you treat it on a case by case basis? Nial.Article: 87883
jfh wrote: > [...] the swing seems to be correct out of the Rocketio > (500 mV single ended swing => 1000mv differential swing). Howdy JF, Did you measure this differentially, or just one leg at a time? If you don't have a differential probe, get one. In the mean time, you can get an approximation by using two probes, placed at the transceiver, and attempt to verify that the edges of each leg transistion at exactly the same time. If the scope has a "Difference mode", where it subtracts one probe from another, it can come in handy here. > The question is am I doing anything wrong in this implementation ? In your other message, you mentioned that the nets "are routed as very loosely coupled traces where each trace has a 50 ohm characteristic impedance". I'd think you'd want a fairly tightly coupled 100 ohm differential pair. How loosely are they coupled? Are the _p and _n legs close to the same length? > The reason for this is that the optical transceiver does not seem to drive > the correct power ie the extinction ratio is very poor (close to 4) > with the low level being around 300uW which is high. If anybody has an > idea or can tell me what I did wrong I would be very thankfull Do you have an optical scope so you can look at the eye diagram? Good luck, MarcArticle: 87884
I'm experiencing an error using XST during synthesis involving a type conversion on a port instance: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18188 Is this legal syntax in the vhdl standard? I was told by a Xilinx applications engineer that they don't have a fix and I have to do the workaround. What a pain... Do the other synthesis tools support this syntax?Article: 87885
Hi, I have measured differentially and single ended. The single ended signal is somehow poorer than the differential one but still the results are satisfying. I did look at the optical eye diagram and it is quite closed because of the low ER of the transceiver on my board. BTW, th _p and _m are closely matched in terms of length but they are quite far away from each other compared to the height above the reference planes. Best regards, JF Marc Randolph a =E9crit : > jfh wrote: > > [...] the swing seems to be correct out of the Rocketio > > (500 mV single ended swing =3D> 1000mv differential swing). > > Howdy JF, > > Did you measure this differentially, or just one leg at a time? If you > don't have a differential probe, get one. In the mean time, you can > get an approximation by using two probes, placed at the transceiver, > and attempt to verify that the edges of each leg transistion at exactly > the same time. If the scope has a "Difference mode", where it > subtracts one probe from another, it can come in handy here. > > > The question is am I doing anything wrong in this implementation ? > > In your other message, you mentioned that the nets "are routed as very > loosely coupled traces where each trace has a 50 ohm characteristic > impedance". I'd think you'd want a fairly tightly coupled 100 ohm > differential pair. How loosely are they coupled? Are the _p and _n > legs close to the same length? > > > The reason for this is that the optical transceiver does not seem to dr= ive > > the correct power ie the extinction ratio is very poor (close to 4) > > with the low level being around 300uW which is high. If anybody has an > > idea or can tell me what I did wrong I would be very thankfull > > Do you have an optical scope so you can look at the eye diagram? >=20 > Good luck, >=20 > MarcArticle: 87886
Yeah. We decided to go the Xilinx route. Apparently no one thought it would be wise to ask me what synthesis tool to license.. Now we are stuck with XST, which I'd rather have avoided. I find it to be fairly dumbed down... makefiles.. ugh.. i'm running away! I suppose I'll have to dig around the Xilinx documentation to get into the nitty gritty details. Thanks all.Article: 87887
Hello, I couldn't find a single newsgroup to post my question, but I needed a good group of people to post my question to. So let me apologize if you don't think should be in your newsgroup. My question is regarding the value (or importance) of System Engineering practices in the R/D World. I work for the government and there are about 40 people in my branch. We do a lot of R/D projects as well as projects for the testing groups. I would like to know from people in the R/D world how important do you feel System Engineering practices are on your job? Many of my co-workers say, "oh that's for really big programs, we don't do that hear". Do you agree? Some believe System engineering only pertains to the integration of the pieces of the design. To me that is only part of SE, there's so much more. Without being long winded, can those who work in the R/D world, could you please give your opinions of SE in your workplace? Is it important or a waste of time? What practices do you feel are necessary? Is SE only for the production people? I appreciate any responses and hope I don't offend anyone for posting my question. My intention is to gain enough information to convince my coworkers to use some of the SE practices I've read about. thanks, joeArticle: 87888
"Marc Randolph" <mrand@my-deja.com> wrote in message news:1123071787.753397.21140@z14g2000cwz.googlegroups.com... > > In your other message, you mentioned that the nets "are routed as very > loosely coupled traces where each trace has a 50 ohm characteristic > impedance". I'd think you'd want a fairly tightly coupled 100 ohm > differential pair. How loosely are they coupled? Are the _p and _n > legs close to the same length? > Hi Marc, The coupling between them doesn't matter if the individual lines are 50 ohms and the propagation time. How can the electricity know the difference between that and a 100 ohm diff pair, or indeed, all the hybrid combinations in between? JF, You should check the datasheet or call the manufacturer to make sure you don't need the put any DC bias on the optics' rx CML port. Normally it's something like Vicm, input common mode voltage. Cheers, Syms.Article: 87889
"Symon" <symon_brewer@hotmail.com> wrote in message news:42f0d979$0$18645$14726298@news.sunsite.dk... > The coupling between them doesn't matter if the individual lines are 50 > ohms and the propagation time is the same for each. Whoops, typo!Article: 87890
It would help if you gave your definition of System Engineering I spent my career in R/D, mostly with small companies, but am not sure what you mean by "System Eng Practices" Dan -- Dan Hollands 1120 S Creek Dr Webster NY 14580 585-872-2606 QuickScore@USSailing.net www.QuickScoreRace.com <jjlindula@hotmail.com> wrote in message news:1123080462.346149.178820@o13g2000cwo.googlegroups.com... > Hello, I couldn't find a single newsgroup to post my question, but I > needed a good group of people to post my question to. So let me > apologize if you don't think should be in your newsgroup. My question > is regarding the value (or importance) of System Engineering practices > in the R/D World. I work for the government and there are about 40 > people in my branch. We do a lot of R/D projects as well as projects > for the testing groups. I would like to know from people in the R/D > world how important do you feel System Engineering practices are on > your job? Many of my co-workers say, "oh that's for really big > programs, we don't do that hear". Do you agree? Some believe System > engineering only pertains to the integration of the pieces of the > design. To me that is only part of SE, there's so much more. Without > being long winded, can those who work in the R/D world, could you > please give your opinions of SE in your workplace? Is it important or a > waste of time? What practices do you feel are necessary? Is SE only for > the production people? I appreciate any responses and hope I don't > offend anyone for posting my question. My intention is to gain enough > information to convince my coworkers to use some of the SE practices > I've read about. > > thanks, > joe >Article: 87891
The other solution is bras. I was told about this yesterday. I've never used it, but it's a tcl build tool (like make, only not so messy). http://bras.berlios.de/ Other folks have said that at least it's way better than make. It's good for all of those EDA folk who love their tcl. -ArlenArticle: 87892
Mike Harrison wrote: > > but what do you mean by 'store 400 bits'...? > and Jim Granville wrote: > > Of ROM or RAM ? > I mean 400 flip-flops (or 400 bits of RAM), for implementing control registers, base address and end address registers, and if possible, a mini buffer. Mike and Jim, thanks for the advice. I'll take a better look in these devices. Thanks. M=E1rcio.Article: 87893
jjlindula@hotmail.com wrote: > Hello, I couldn't find a single newsgroup to post my question, but I > needed a good group of people to post my question to. So let me > apologize if you don't think should be in your newsgroup. My question > is regarding the value (or importance) of System Engineering practices > in the R/D World. I work for the government and there are about 40 > people in my branch. We do a lot of R/D projects as well as projects > for the testing groups. I would like to know from people in the R/D > world how important do you feel System Engineering practices are on > your job? Many of my co-workers say, "oh that's for really big > programs, we don't do that hear". Do you agree? Some believe System > engineering only pertains to the integration of the pieces of the > design. To me that is only part of SE, there's so much more. Without > being long winded, can those who work in the R/D world, could you > please give your opinions of SE in your workplace? Is it important or a > waste of time? What practices do you feel are necessary? Is SE only for > the production people? I appreciate any responses and hope I don't > offend anyone for posting my question. My intention is to gain enough > information to convince my coworkers to use some of the SE practices > I've read about. > > thanks, > joe > In the companies where I've worked, and in most other companies, if no one knew exactly what you did but they knew you were valuable they called you a "systems engineer". Some of these people ended up either doing or coordinating the design tradeoffs between hardware, software, mechanical, etc.; others couldn't engineer their way out of a paper bag, but were good for dealing with certain esoteric problems that required large brains. So you'll have to define "systems engineering practices" for us. In most places where it needs to be done the design tradeoffs between disciplines that I'm speaking of tend to be done by the project manager, or they happen by committee, with electrical, software and mechanical engineers getting together and hashing things out. If the project manager is smart and/or if the committee gets together well then this can make for some very good systems designs. Unfortunately it's a chain that's weaker than its weakest link, so you have to be careful. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 87894
> Altera have the MAX II, tho they 'forgot' to put RAM in that (unlike > the lattice MachXO), so that will struggle on 400 bits, and also on > the 5V aspect. MAX II EPM1270 can easy store the 400 bits in the 1270 available registers and has 3V3 I/O combined with PCI clamp diodes in 1 of the 4 I/O banks that can make the input 5V tolerant with a single resistor. Price could be an issue, contact your local disti for that.Article: 87895
Hello, to be brief SE involves requirements analysis, risk managment, controlling your design processes, interface control, supportability, realiability, maintainability, reproducability, peer reviews and technical reviews, test planning, integration planning. SE is used to manage a project to control costs, schedule, and performance. I"m still learning all the areas and probablity left out a ton of stuff. Although, I'm more interested in the technical side of SE, rather than counting the money stuff.Article: 87896
On 3 Aug 2005 07:47:42 -0700, jjlindula@hotmail.com wrote: >Hello, I couldn't find a single newsgroup to post my question, but I >needed a good group of people to post my question to. So let me >apologize if you don't think should be in your newsgroup. My question >is regarding the value (or importance) of System Engineering practices >in the R/D World. I work for the government and there are about 40 >people in my branch. We do a lot of R/D projects as well as projects >for the testing groups. I would like to know from people in the R/D >world how important do you feel System Engineering practices are on >your job? Many of my co-workers say, "oh that's for really big >programs, we don't do that hear". Do you agree? Some believe System >engineering only pertains to the integration of the pieces of the >design. To me that is only part of SE, there's so much more. Without >being long winded, can those who work in the R/D world, could you >please give your opinions of SE in your workplace? Is it important or a >waste of time? What practices do you feel are necessary? Is SE only for >the production people? I appreciate any responses and hope I don't >offend anyone for posting my question. My intention is to gain enough >information to convince my coworkers to use some of the SE practices >I've read about. > >thanks, >joe What is "System Engineering" anyhow? If you mean someone who plans high-level designs without detailed knowledge of the underlying technology, my company certainly has nobody like that, and my customers, gigabuck big-science projects and aerospace companies, don't seem to either, as far as I can tell. The people who do the highest-level thinking, the grand architectures and the new ideas, seem to be just the best of the technologists. JohnArticle: 87897
<usenet_10@stanka-web.de> wrote in message news:1123053054.887144.273240@o13g2000cwo.googlegroups.com... > HI, > > based on your other answer I understand you have a .adb file. I do have a .adb file - along with a host of others. I've got subdirectories labeled "design_definition", "simulator_build", etc. > This is the actel database which should be useable in the newer > versions of actel designer software (When having a very old version you > might lost your pinout). > I hope you didn't mean a .afm file which is only the programming file > for the Fpga and will be (nearly [1]) complete useless. I do have a .afm file which I sent off to the Actel distributor when I ordered more chips. > > The designer software is available as silver edition for free. This > edition is OK for smaller devices. Well, how small? I'm using the eX64 (64 dedicated flip-flops, 3000 system gates) > The database contains the netlist which can be exported. But without > having any knowledge of rtl and netlist you out yourself as someone who > should not even think to modify the netlist to get the desired results. No "outing" about it - I'm a raw beginner at embedded programming. I'm trying to make sense of what I've got and to determine what I need to do. Among other things, I'm trying to determine if I should continue with this basic design or to switch to an entirely different chip. (a business decision based on technical aspects.) > > Start searching .vhd or .v files containing the rtl code (register > transfer level). > The IMHO better way for you would be starting to learn how to design > digital cirquits and rebuild the design from scratch. I've got the book "VDHL Programming by example". I don't know if any of the book's tools would be useable. > > bye Thomas > > [1] Buying a good support from Actel As I indicated, the ROI is VERY bad at this point.Article: 87898
I think the bigger the project the more you will need systems engineers, in smaller projects the typical system tasks (requirements definition, interface specifications, trade studies, test plans procedures, spec compliance verification, test equipment integration, debugging high level field integration problems) usuallly are integrated into the software/hardware engineers work schedule. If you tried to force the creation of a systems engineer position is a small project you probably would need to create unnecessary busy work to keep him/her employed (forcing the generation of unneeded documents). As projects get bigger these functions are too much for the software/hardware engineers to support and the creation of a formalized system engineering function becomes necessary. The majority of systems work is customer/production related, so R/D has much less need for dedicated systems people, just my opinion.Article: 87899
Tim Wescott wrote: > In most places where it needs to be done the design tradeoffs > between disciplines that I'm speaking of tend to be done by the > project manager, or they happen by committee, with electrical, > software and mechanical engineers getting together and hashing > things out. If the project manager is smart and/or if the > committee gets together well then this can make for some very > good systems designs. Unfortunately it's a chain that's weaker > than its weakest link, so you have to be careful. What do you mean by that, "weaker than its weakest link"? -- Quidquid latine dictum sit, altum viditur.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z