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Would be nice if more Lattice FAEs would participate n the discussions on this board ... Rgds Andr=E9Article: 88126
<ALuPin@web.de> schrieb im Newsbeitrag news:1123664591.723711.148300@g44g2000cwa.googlegroups.com... Would be nice if more Lattice FAEs would participate n the discussions on this board ... Rgds André there are people with Lattice and Actel experience around, but yes there seem to be no public comments from anyone directly from Lattice of Actel. This could actually be corporate policy of those companies. ? AnttiArticle: 88127
Hi Steven, Since you're back, can you refresh us on Spartan3E availability? Luiz Carlos. P.S. Supposing "Steve Knapp" and "Steven K. Knapp" are the same person, which one is right?Article: 88128
On Tue, 09 Aug 2005 19:16:32 -0500, jeff.holley@latticesemi-dot-com.no-spam.invalid (jholley) wrote: >> Javier Castillowrote: >Hello, >> >> I am working on cryptographic application over VirtexII FPGAs. I >> need to store a simmetric key inside a reg of the FPGA, but I dont >> want that someboy could read it analizyng the bitstream. The >bitstream >> could not be encrypted. Has anybody experience about hide data >inside >> a FPGA?. Anyone knows some papers about this topic? >> >> Regards >> >> Javier > >Javier, > >If you use the new Lattice XP devices, the need for an external PROM >is eliminated and read back can be disabled. They do this by having >the Flash internal. Just offering another way to "skin the cat". > >Regards, >Jeff Holley >Lattice FAE >(yes, I work for Lattice) Hello, Thank you for your answer. I am not familiar with those type of FPGAs and I dont know the configuration mechanism. Is it possible to on-the-field reprogram a FLASH based FPGA using a external microprocessor connected to Internet as in Xilinx IRL scheme? Best Regards Javier CastilloArticle: 88129
Dear
Due to lack of experience, I am having a hard time :) to debug the
following with ChipScope Pro.
My goal is to see "0 -> 1 -> 2 -> 3 -> 4 -> 0 -> 0 -> ..." in waveform
of Analyzer. I wonder if this is possible.
Problem is that I only see "4 -> 4 -> 4 -> 4 -> ...".
It seems that the starting time of data capture and the starting time
in my mind are different each other.
In addition, the problem is maybe because of the "Read period" in VIO,
which is 250 ms. What I want to see only "0 ns -> 100 ns" !
Many trials have been done with no luck. Thankyou for the help.
Regards.
Configuration is
---------------------------------
* ICON :
- 2 Control port,
* ILA :
- One 2-bit trigger port (reset, en),
- 4-bit data (counter(0),...,counter(3))
* VIO :
- 4-bit sync. input (counter(0),...,counter(3)),
- 2-bit async. output (reset, en)
* Analyzer :
- setting reset='0', en='1' in console.
- Trigger condition (reset=0,en=1)
---------------------------------
----------------------------------------------
-- 4 bit Counter
-- Expected behavior : 0 -> 1 -> 2 -> 3 -> 4 -> 0 -> 0 -> ...
----------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
( clk : in std_logic;
cnt : out std_logic_vector(3 downto 0));
end top;
architecture behave of top is
signal counter : std_logic_vector(3 downto 0);
signal rst_tmp : std_logic;
signal clk_tmp : std_logic;
signal en : std_logic;
begin
clk_tmp <= clk;
process(en,rst_tmp,clk_tmp)
begin
if en='0' then -- enable
counter <= (others => '0');
elsif rst_tmp='1' then -- reset
counter <= (others => '0');
elsif counter <= "0011" then
if ( clk_tmp'event and clk_tmp = '1') then
counter <= counter + 1;
end if;
end if;
end process;
cnt <= counter(3 downto 0);
end behave;
----------------------------------------------
Article: 88130Hi Philip, That does the job. However, I have a few concerns: - I cannot implement XDL compilation on an FPGA. Maybe JBits would be an alternative for the Virtex-II. Do you know whether JBits can be run under the JOP java core? - XDL is depreciated, as is JBits. Which technology do you think will be around longer? Which one to prefer? - There used to be XDL documentation in Xilinx/help/data/xdl.html, according to postings in this group. This is definitely no longer true for the WebPack 7.1. Does anyone have a copy of this xdl.html and mail it to me? Or is it available somewhere else? (Not at xilinx.com as far as I can see) Thank you! TobyArticle: 88131
"Javier Castillo" <jcastillo@opensocdesign.com> schrieb im Newsbeitrag news:0lrjf1hssrhj01m0f3e4miu6rd6a3l5b92@4ax.com... > On Tue, 09 Aug 2005 19:16:32 -0500, > jeff.holley@latticesemi-dot-com.no-spam.invalid (jholley) wrote: > > >> Javier Castillowrote: > >Hello, > >> > >> I am working on cryptographic application over VirtexII FPGAs. I > >> need to store a simmetric key inside a reg of the FPGA, but I dont > >> want that someboy could read it analizyng the bitstream. The > >bitstream > >> could not be encrypted. Has anybody experience about hide data > >inside > >> a FPGA?. Anyone knows some papers about this topic? > >> > >> Regards > >> > >> Javier > > > >Javier, > > > >If you use the new Lattice XP devices, the need for an external PROM > >is eliminated and read back can be disabled. They do this by having > >the Flash internal. Just offering another way to "skin the cat". > > > >Regards, > >Jeff Holley > >Lattice FAE > >(yes, I work for Lattice) > > Hello, > Thank you for your answer. I am not familiar with those type of FPGAs > and I dont know the configuration mechanism. Is it possible to > on-the-field reprogram a FLASH based FPGA using a external > microprocessor connected to Internet as in Xilinx IRL scheme? > > Best Regards > > Javier Castillo yes it is. the Actel PA3 also allows non volatile secure keys for encrypted bitstream (I thínk that is not possible for LatticeXP) AnttiArticle: 88132
"Tobias Weihmann" <listen@fomalhaut.de> schrieb im Newsbeitrag news:1123677719.977524.94260@f14g2000cwb.googlegroups.com... > > Hi Philip, > > That does the job. However, I have a few concerns: > > - I cannot implement XDL compilation on an FPGA. Maybe JBits would > be an alternative for the Virtex-II. Do you know whether JBits can > be run under the JOP java core? > > - XDL is depreciated, as is JBits. Which technology do you think > will be around longer? Which one to prefer? it looks like the XDL will be around for a while - JBits was never an option at all, it was always, 'maybe.. oneday..' but the day never did arrive > - There used to be XDL documentation in Xilinx/help/data/xdl.html, > according to postings in this group. This is definitely no longer > true for the WebPack 7.1. Does anyone have a copy of this xdl.html > and mail it to me? Or is it available somewhere else? (Not at > xilinx.com as far as I can see) > > Thank you! > Toby > XDL is not advertized much, true but its still is part of ISE 7.x well it the .NCD files created with it are not compatible with ISE 7.x (and with no other version as well) and the Answer Record on this is dated ISE 6.3 and provides no solutions. xdl.html was in the 6.3 at least, in 7.1 it seems to be vanished. AnttiArticle: 88133
<oen_no_spam@yahoo.com.br> schrieb im Newsbeitrag news:1123671627.168041.278640@g49g2000cwa.googlegroups.com... > Hi Steven, > > Since you're back, can you refresh us on Spartan3E availability? > > Luiz Carlos. > > P.S. Supposing "Steve Knapp" and "Steven K. Knapp" are the same person, > which one is right? > Its soon mid August not long til September so I guess a statement made in April/May by "Antti Lukats" (that is me): "no S3e general availability before Sep 2005" is valid. No matter what Xilinx related people have said in the meanwhile. I hoped to be wrong, but there is no prove so far. S3e is not generically avaialble and I dont think the situation is going to change within next weeks, and then its september already what makes my initial statement more correct than the other statements about s3e availability. AnttiArticle: 88134
Hi all,
Can any one tell me what is RAPID PROTOTYPING and how will this
technology help us in faster designing of products in FPGA.
Can you please tell me some source where I can get basics of RAPID
PROTOTYPING.
Thanks in Advance,
Sarath
Article: 88135>> Hi Steven, >> >> Since you're back, can you refresh us on Spartan3E availability? >> >> Luiz Carlos. >> > Its soon mid August not long til September so I guess a statement made in > April/May > by "Antti Lukats" (that is me): "no S3e general availability before Sep > 2005" is valid. > > No matter what Xilinx related people have said in the meanwhile. > > I hoped to be wrong, but there is no prove so far. S3e is not generically > avaialble and I dont > think the situation is going to change within next weeks, and then its > september already > what makes my initial statement more correct than the other statements > about > s3e availability. > > Antti > Hi Antti, Luiz, I can luckily tell that I have a S3-500E running in a own design. There is a ERIC5 inside, executing C-code, everything looks fine up to now :-) However, I do not know how the general situation is (as I did not get as many parts as I wanted, too). Also I do not know how the situation of the other S3Es is. Thomas www.entner-electronics.comArticle: 88136
Your code looks pretty good. To answer your first question: If your answer is found in the first population you just got lucky and you're done! Your correct in the way you check for if the Error == 0 you stop, or the normalized value would be infinite. I have had similar issues with the answer diverging on some iterations. What you need to do is have a fixed number of iterations like 100, That way it won't ever be in an infinite loop. Another thing to try would be use a larger population 6 is pretty small. Another thing to do is keep track of you populations total error, if it is not going down, maybe introduce more mutations. There are a bunch of ways to try and get your population to evolve into the answer faster. Since your know in this particular problem ax + b can not be greater than c, you can use this to evaluate each random number in your population. If you number violates this property, then just throw out that number and get a new random number. This is kind of cheating, since the repopulating should naturally weed out these answers. One other option would be to give numbers that violate the ax+b = c a very large Error, that way they just won't get repopulated. One other thing to check is make sure you repopulation function is running correctly. It is very easy to make a mistake in that function. Good Luck EricArticle: 88137
Another thing to try is make your fitness function non-linear. Error = (1-(ax+b)/c)^4 This will make the Error huge on values that are far away from the answer. EricArticle: 88138
Did you simulated your code before place and route ?
Try this :
process (clk,rst,en)
begin
if rst='1' then
counter <= (others=>'0'); -- Asynch reset
elsif (clk'event and clk='1') then
if en='0' then
counter <= (others=>'0');
else
counter <= counter + 1;
end if;
end if;
end process;
Article: 88139Hello, I know this is a off-the-wall question, but bear with me. In my effort to become more efficient and improve my design process in my FPGA design I always create a top block diagram that is either a Block Design File (.bdf) or a Graphic Design File (.gdf). If you are not familiar with these files, they are basically a schematic where you can graphically add symbols and connect symbols via wires or buses. I believe using these files reduces complexity, and creates documentation while you design. I know it does take some time placing the wires, which is why some don't uses these files in their fpga design. In addition, using these graphical files allows you to create a hierarchical design which again helps manage complexity and makes the design easier to modify/maintain. I'm just wondering how many people use some sort of graphic design in their FPGA programs? I see so many benefits of doing so, but my co-workers see it as a waste of time placing those wires and symbols they would just rather have a design contain lots of .vhdl, .v, and .tdf files. Any thoughts, comments, suggestions, experiences on the topic? I'm not trying to be picky, its just when I see a tool that can help reduce complexity if can't understand why people wouldn't use it. thanks, joeArticle: 88140
Hi Yes the code is simulated and counter value is working : "0->1->2->3->4->0->0->0->0->...", when initially rst=0, en=1. (Your code is working : "0->1->2->3->4->5->.....->14->15->0->1->2->...->14->15->0->......." as far as rst=0, en=1) I did this way because I need to see only "1->2->3->4->0" in the waveform in the analyzer. Anyway, my wish is to see the same waveform of simulation as the waveform of Analyzer, when we initially set rst=0, en=1. Thankyou for comments.Article: 88141
hi anybody knows where did the download for Forge compiler evaluation disappear at www.xilinx.com ??? there are still forums about Forge at Xilinx.com but the no links to the product at all, whats happening ? AnttiArticle: 88142
Georg Acher wrote: > "Monica" <monica_dsz@yahoo.com> writes: > >Hallo all, > > > >I am Monica from Germany working on data transmission over DVB.I > >must implement a MPEG-2 frame generator in the VHDL.But to my surprise > >I couldnt find anything realted to MPEG-2 frame structure and low level > >MPEG-2 signalling details.Every site says MPEG-2 is 188 byte frame and > >nothing more. > > That's the transport stream level... There are other packaging methods... > > >Is MPEG-2 a poprietary standard?If anybody already worked on MPEG-2 > >related projects,kidnly give me some pointers/links reagrding MPEG-2 > >frame structure and low level signalling details. > > Look for the ISO13818-1 specification, everything is explained in it. > > -- > Georg Acher, acher@in.tum.de > http://www.lrr.in.tum.de/~acher > "Oh no, not again !" The bowl of petunias Thanks alot. MonicaArticle: 88143
Hi joe, I use graphical only on top level,that to when I would like to alter the top level components and experiment with the components and their interfacing becausing it is easy for me to alter the connections. If I knew the connections between the components and if am sure that those top level blocks/modules and their interface is fixed then I will code it in HDL. I am also interested to know what others think of this approach. thks & regds, Monica, GermanyArticle: 88144
Hi All, I am looking for a VHDL model for the CY7B923 and CY7B933 Hotlink Transmitter and Receiver. The tech support at Cypress referred me to Synopsys, but I can't get anything from Synopsys because I don't have a site ID (and thus can't register for Synopsys SolvNet). Does anyone know another site where I can obtain the functional models? Thanks ErnieArticle: 88145
Found an issue with the Verilog module please ignore. However, it would be nice if the Xilinx tools gave a big warning saying that nothing was synthesized, placed and routed for module X... Cheers, JOhn On Mon, 8 Aug 2005, John D. Davis wrote: > Hello, > > I have a top level module for a XCV1000. It has a following specified UCF > for the pin and netname mappings. I have instantiated to fo the DLLs and > two user modules. The DLLs are the same as in XAPP132 for a 4X clock > signal generation. When I generate the bit file and look at the design > with FPGA Editor, I don't see any signals or CLBs for one of the two user > defined modules. There are some warnings about clock signals and I am > using "clock_signal" synthesis attribute to tell XST which are the clocks, > basically restricting the clocks and reducing the GCLK usage. When I > comment out one of the modules that is instanitated all the time and > re-synthesize, I see module instantiation. I have put the files online > that I think may be helpful. These files can be found at: > > http://www.stanford.edu/~johnd/Xilinx/ > > The top level module is CP2_FPGA and I instantiate two user modules within > CP2_FPGA: > > R3000Init1 > Test00a > > The R3000Init1 always shows up and Test00a doesn't. If I comment out > R3000Init1, then Test00a shows up in FPGA editor. I have attached the log > files when I synthesize with both modules: R3KandTest00.txt and with just > the Test00a: JustTest00.txt. The CP2_FPGA.ncd is the file for FPGA Editor > for the first case (both modules) and CP2_FPGA_last_par.ncd is the FPGA > Editor file for the latter case, when R3000Init1 is commented out. > > I can include other files, but it is strange that the instantiated module > is not in the FPGA Editor with the related CLB's depending on what other > modules exist. I would like a highly modular design for easy of debugging > and code management. Any idea's why the module doesn't appear in the > FPGA? > > Thanks, > John D. Davis > > John D. Davis PhD Candidate Computer Systems Lab Office # 1.650.723.6891 Stanford University Fax # 1.650.725.6949Article: 88146
jjlindula@hotmail.com wrote: > Hello, I know this is a off-the-wall question, but bear with me. In my > effort to become more efficient and improve my design process in my > FPGA design I always create a top block diagram that is either a Block > Design File (.bdf) or a Graphic Design File (.gdf). If you are not > familiar with these files, they are basically a schematic where you can > graphically add symbols and connect symbols via wires or buses. I > believe using these files reduces complexity, and creates documentation > while you design. I know it does take some time placing the wires, > which is why some don't uses these files in their fpga design. In > addition, using these graphical files allows you to create a > hierarchical design which again helps manage complexity and makes the > design easier to modify/maintain. I'm just wondering how many people > use some sort of graphic design in their FPGA programs? I see so many > benefits of doing so, but my co-workers see it as a waste of time > placing those wires and symbols they would just rather have a design > contain lots of .vhdl, .v, and .tdf files. Any thoughts, comments, > suggestions, experiences on the topic? I'm not trying to be picky, its > just when I see a tool that can help reduce complexity if can't > understand why people wouldn't use it. Funny, I just had a similar conversation with coworkers this morning who asked why I didn't use a schematic for an FPGA design. I never use anything other than VHDL sources in my designs. That's the only way you can guarantee portability between chip vendors, as well as saving your bacon when a vendor decides that he doesn't like the current schematic/block-diagram format/tool and changes it. Plus, commenting in block diagrams and schematics is a pain. Plus also too, I like to have real VHDL testbenches. -aArticle: 88147
patrick.melet@dmradiocom.fr wrote: > Did you simulated your code before place and route ? > > Try this : > > process (clk,rst,en) -------------------^^ Why is this here? > begin > if rst='1' then > counter <= (others=>'0'); -- Asynch reset > elsif (clk'event and clk='1') then > if en='0' then > counter <= (others=>'0'); > else > counter <= counter + 1; > end if; > end if; > end process; --aArticle: 88148
I'm doing the same thing, if your problem is the transport stream (as it is in DVB) may be the ETSI EN 300 468 may be more useful.... doing a google you can find it... -- Luis Vaccaro "Monica" <monica_dsz@yahoo.com> wrote in message news:1123689503.042786.30770@g14g2000cwa.googlegroups.com... > > Georg Acher wrote: > > "Monica" <monica_dsz@yahoo.com> writes: > > >Hallo all, > > > > > >I am Monica from Germany working on data transmission over DVB.I > > >must implement a MPEG-2 frame generator in the VHDL.But to my surprise > > >I couldnt find anything realted to MPEG-2 frame structure and low level > > >MPEG-2 signalling details.Every site says MPEG-2 is 188 byte frame and > > >nothing more. > > > > That's the transport stream level... There are other packaging methods... > > > > >Is MPEG-2 a poprietary standard?If anybody already worked on MPEG-2 > > >related projects,kidnly give me some pointers/links reagrding MPEG-2 > > >frame structure and low level signalling details. > > > > Look for the ISO13818-1 specification, everything is explained in it. > > > > -- > > Georg Acher, acher@in.tum.de > > http://www.lrr.in.tum.de/~acher > > "Oh no, not again !" The bowl of petunias > > Thanks alot. > Monica >Article: 88149
Javier Castillo wrote: > Thank you for your answer. I am not familiar with those type of FPGAs > and I dont know the configuration mechanism. Is it possible to > on-the-field reprogram a FLASH based FPGA using a external > microprocessor connected to Internet as in Xilinx IRL scheme? They use JTAG, so I suppose you could put a JTAG master in your micro. -a
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