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Hi Morpheus And Ben Thanks for your reply but my confusion is 1. In Quartus tool Full Compilation means complete implementation and that generates both .vho and .sdo file for me after fitting and place route. 2. But is there any option to generate a back anotated post synthesis .vhd file or .vho file with a .sdo file after gate level synthesis so after simulating the post synthesis .sdo file can we get only gate delays in simulation and not the net or routing(wire) delays thanks regards KedarArticle: 90301
Hello, I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One of the modules i need is an 16550 compatible UART which has to communicate through an ISA bus (PC104). My question is if somebody has the VHDL code for it, or can tell me where i can find code (i've already asked quotes at core suppliers but this is a little bit expensive). Thanks in advanceArticle: 90302
> So my question is, by utilizing the FPGA resource around 90%, does the > behaviour of FPGA logics becomes unpredictible ? > Any pointers or suggestions in this regard is much appreciated. > Thank you in advance. > -Kiran If your design is _properly_ constrained, and if the timing analysis after a build says everything's OK, then the amount of logic in the device shouldn't have any effect on the performance. Nial. ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 90303
unrelated logic means just what it says .. unrelated.. that means logic which doesn't have an interconnect. It might even be from different parts of the design. The only thing they have in common is they have nothing to do with each other. A bit like reality TV but without the camera :-) Simon "bijoy" <pbijoy@rediffmail.com> wrote in message news:ee90aa5.5@webx.sUN8CHnE... > Hi Antii > > How can i identify the unrelated logic ? what is the meaning of unrelated logic. ? > > could you please explain about it ? > > regards bijoyArticle: 90304
"Duane Clark" <dclark@junkmail.com> wrote in message news:knd%e.1804$Fi3.669@newssvr29.news.prodigy.net... > praveen.kantharajapura@gmail.com wrote: >> Hi all, >> >> I have a question on POR(Power on reset generation ) using FPGA. >> My FPGA does not have a external Power ON reset , i am planning to >> generate a Power ON reset in the FPGA only.Is it really feasible to >> do this in an FPGA, and use this as the reset for my logic. >> Any suggestions appreciated?? > > As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you > want an internal synchronous reset, just create a large counter which is will count down once > after an asynchronous reset. A synchronous reset would be held until the counter finishes (of > course, don't apply the synchronous reset to the countdown counter;) I'd suggest not using "1111...11"s or "000...0"s as the terminal count. If you've no external asynch reset to intiialise this counter you can't be sure what state it'll be configured to power up in. I'd suggest that all '1's or all '0's are the two most likely power up states. Use "101010...1010" as your termninal count and the odds are the flip-flops won't power up to match it. Nial ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 90305
Jackolantern25@gmail.com wrote: > I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One > of the modules i need is an 16550 compatible UART which has to > communicate through an ISA bus (PC104). > My question is if somebody has the VHDL code for it, or can tell me > where i can find code (i've already asked quotes at core suppliers but > this is a little bit expensive). <http://www.opencores.org/projects.cgi/web/uart16550/overview> It's got a wishbone interface, but should be pretty trivial to interface it to ISA.. Regards, MarkArticle: 90306
d...@xess.com wrote: > ... > So the makefiles will work if these are still ASCII in 7.x > ... thanks a lot... I'll try it! SandroArticle: 90307
On 28 Sep 2005 06:45:10 -0700, amyler@eircom.net wrote: >Can anyone recommend a 16-bit microprocessor core to use in an Actel >ProAsic+ device. Actel just announced availability of ARM7 in ProASIC3. There will be a small price premium on the parts - the bitstream (or fusemap or config image or whatever Actel call it) is encrypted so that there's no risk of ARM's jealously-guarded IP leaking out, and the ARM-enabled devices have some kind of internal security key, and you get to pay for that. Software support is, obviously, rather good. Debug support is less clear right now - can they do tracing, single-step etc? Any Actel gurus/AEs/sales-droids out there care to comment? I don't know the devices too well, and the people on the Actel booth at ARM DevCon last week weren't exactly crystal- clear about it all. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90308
On Fri, 30 Sep 2005 15:53:03 -0400, "geoffrey wall" <wallge@eng.fsu.edu> wrote: >I would like to write a parameterizeable component in vhdl >that would do an N element fixed point dot product. I was wondering if there >was a (synthesizable) way to generate a first stage of multiplies (ceil(N/2) >multiply blocks), and >then ceil(log2(N)) - 1 add stages. Forgive my ignorance and/or stupidity, but how can you get away with only N/2 multipliers and logN adders? Is there something special about the values you're processing, or is there some cool math I don't know about? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90309
"Jonathan Bromley" <jonathan.bromley@doulos.com> schrieb im Newsbeitrag news:ev9kk1h98br6a0t1nf1jed4073vuijs864@4ax.com... > On 28 Sep 2005 06:45:10 -0700, amyler@eircom.net wrote: > > >Can anyone recommend a 16-bit microprocessor core to use in an Actel > >ProAsic+ device. > > Actel just announced availability of ARM7 in ProASIC3. > There will be a small price premium on the parts - the bitstream > (or fusemap or config image or whatever Actel call it) is > encrypted so that there's no risk of ARM's jealously-guarded > IP leaking out, and the ARM-enabled devices have some kind of > internal security key, and you get to pay for that. > > Software support is, obviously, rather good. Debug support > is less clear right now - can they do tracing, single-step etc? rather good? nothing=good ? to my knowledge Actel is saying that their tools support the ARM7 for some time already, but if you download and install them, then there is nothing about ARM7 at all. :( also its nothing on the website as well. - so whatever they have announced today or earlier, nothing of it is available as of today. so in this case I would say seeing is believing, and currently there is nothing to see :( AnttiArticle: 90310
Is anyone here doing anything to do with VSIPL? I've been working on a VSIPL project for a few months now, looking at developing a commercial implementation. I've been looking mostly at the system design issues and the hardware specifics. I reckoned it was maybe about time to take another look at the motivations and I'm trying to get more of a feel for what's happening with this standard at this point in time. If you go looking on the internet for what people think of VSIPL, you don't hit on a lot of stuff. There are a good few discussions from a couple of years ago talking about VSIPL as something that never happened. Another failed standard. However, interest in the standard seems to be growing again. My project for example, and this appeared in september: http://www.dna-cs.com/pdf/datasheet_vsipl.pdf At the MAPLD conference in Washington in September I spoke to a number of people in industry who were very interested in VSIPL, senior scientists at the Air Force Research Laboratory for example. I understand that Lockheed Martin have also shown a strong interest in VSIPL implementation development. Any thoughts? ReplyArticle: 90311
Jonathan Bromley wrote: > On 28 Sep 2005 06:45:10 -0700, amyler@eircom.net wrote: > > >>Can anyone recommend a 16-bit microprocessor core to use in an Actel >>ProAsic+ device. > > > Actel just announced availability of ARM7 in ProASIC3. > There will be a small price premium on the parts - the bitstream > (or fusemap or config image or whatever Actel call it) is > encrypted so that there's no risk of ARM's jealously-guarded > IP leaking out, and the ARM-enabled devices have some kind of > internal security key, and you get to pay for that. > > Software support is, obviously, rather good. Debug support > is less clear right now - can they do tracing, single-step etc? > > Any Actel gurus/AEs/sales-droids out there care to comment? > I don't know the devices too well, and the people on the > Actel booth at ARM DevCon last week weren't exactly crystal- > clear about it all. This type of product has to exist mainly for the column-inches the Actel marketing dept can generate. In any practical deployment, the applied cost is very high. Latest ARM microcontrollers are now sub $2, and that's WITH Dual UARTS, SSI, SPI, i2c and ADC peripherals, _and_ FLASH and RAM. So, it makes more sense to connect a ARM uC to a FPGA, via the SSI link, and use both for their optimium tasks. With an IPCore + FPGA, you _still_ have to connect external CODE memory, but with a higher pin cost, and more RFI..... [Small cores, FPGA optimised, that can run in on-fpga resource, make more sense.] The Lattice Mico8 is open source, but presently has 8 bit registers and 18 bit opcodes. The OP could look at extending that ? -jgArticle: 90312
Good day, I'm sorry to start another thread on the notorious NGDBUILD 455 problem while using Xilinx ISE, however I simply can't figure out the solutions based on what I read on the web. My scenario is that I have some sub-sub-modules (SSMs) synthesized with Synplify. I've disabled I/O insertion. Then in ISE 6.1, I use a sub-module (SM?), which is a Verilog file, as the top module for those synthesized SSMs. However there is a real top module (TM, also a Verilog file), which encompasses my SM and other SMs. Therefore TM (.v) ____|___________ | \ \ | \ \ SM-1 SM-2 ... (.v) |_______________ | \ \ SSM-1 SSM-2 ... (.edf) My problem then occurs when ISE tries to translate my design. The major part is that my RESET has NGDBUILD 455 (multiple drivers) and 466 (multiple buffers) errors. And the major reason I can think of is that I do lots of the following: wire reset_xx = RESET; The RESET signal comes externally to TM, and then drives through SM-1 to those SSMs. I've tried to disabled "Add I/O Buffers" in the Synthesis option, but the results remain the same. Is my assignment illegal? I think that it's quite natural to "rename" the RESET signal since each module can be designed by different people. Or should I just stop the maddness and let RESET be RESET? Please give me any comments you have. Thank you :-) Regards, MJArticle: 90313
Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);Article: 90314
Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);Article: 90315
news.hinet.net wrote: > Yes it comes with a linux and solaris cd too not mine, only device files for all plattforms (or I didnot see it anyhow ...) Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 90316
On Mon, 10 Oct 2005 10:59:53 +0200, "Antti Lukats" <antti@openchip.org> wrote: [ARM7] >> Software support is, obviously, rather good. Debug support >> is less clear right now - can they do tracing, single-step etc? > >rather good? nothing=good ? > >to my knowledge Actel is saying that their tools support the ARM7 for some >time already, but if you download and install them, then there is nothing >about ARM7 at all. I said "software support" - I didn't say "Actel software support" :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90317
"Jonathan Bromley" <jonathan.bromley@doulos.com> schrieb im Newsbeitrag news:f3kkk15knfl714j3ao0s5esh9m8su3lui7@4ax.com... > On Mon, 10 Oct 2005 10:59:53 +0200, "Antti Lukats" > <antti@openchip.org> wrote: > > [ARM7] > >> Software support is, obviously, rather good. Debug support > >> is less clear right now - can they do tracing, single-step etc? > > > >rather good? nothing=good ? > > > >to my knowledge Actel is saying that their tools support the ARM7 for some > >time already, but if you download and install them, then there is nothing > >about ARM7 at all. > > I said "software support" - I didn't say "Actel software support" :-) > -- > Jonathan Bromley, Consultant I see. yes that is correct, and that would be the main reason to use ARM7 in first place. AnttiArticle: 90318
Hello, We have released the version 0.5 of the SystemC to Verilog Synthesizable Subset Translator, wich includes support for structures translation from SystemC to Verilog. You can download it from http://www.opencores.org/projects.cgi/web/sc2v/overview Javier CastilloArticle: 90319
Hi, I have routed an input clock from an input pin directecly to an output pin and I used this clock (too) to all my design under a Stratix FPGA. We have encountered a big problem because the input clock signal fall under 0.5 V !!! So for this, we have just divided the input clock to two disctinct input pin (one input pin toward one output pin) and the other input pin to our design and that works fine Why we cannot send an clock signal (from an input pin) to an output pin and to the entire design ? Do you know what's happen ? Thanks.Article: 90320
Why do you not use a PLL within the FPGA ? You could use the output C0 or C1 of the PLL for FPGA "inner" purposes and the output E to route the clock to an output pin. Rgds Andr=E9Article: 90321
You could use some concurrent assignment in which you perform the concatenation. PORT MAP ( data =3D> ls_data_concat ....) ls_data_concat <=3D (CAV & DAV & KDATA); Rgds Andr=E9Article: 90322
Dear poster,
simprim libraries are models for simulation (as in the mame SIM(ulation)
PRIM(imitives))
for synthesis use UNISIM instead.
the netlist you have is for simulation only, as it said in your post
"Simulate Post-translate VHDL Modele..."
and it's not synthesizable
Aurash
Aurash
seabrench@163.com wrote:
>hello!
>When I use ths XST to synthesis(Simulate Post-translate VHDL Modele) a
>project,it tells me errors:
>ERROR:HDLParsers:3317...Library SIMPRIM cannot be found.
>ERROR:HDLParsers:3013...Library SIMPRIM is not declared.
>
>library SIMPRIM;
>use SIMPRIM.VCOMPONENTS.ALL;
>use SIMPRIM.VPACKAGE.ALL;
>
>why?How to do it?
>
>Thanks!
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 90323Duane, Xilinx FPGAs use the prog_b pin to act as an external reset if you prefer. Asserting prog_b to ground will cause the device to hold off configuration. Releasing prog_b will allow the device to configure, and start up. Austin Nial Stewart wrote: > "Duane Clark" <dclark@junkmail.com> wrote in message > news:knd%e.1804$Fi3.669@newssvr29.news.prodigy.net... > >>praveen.kantharajapura@gmail.com wrote: >> >>>Hi all, >>> >>>I have a question on POR(Power on reset generation ) using FPGA. >>>My FPGA does not have a external Power ON reset , i am planning to >>>generate a Power ON reset in the FPGA only.Is it really feasible to >>>do this in an FPGA, and use this as the reset for my logic. >>>Any suggestions appreciated?? >> >>As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you >>want an internal synchronous reset, just create a large counter which is will count down once >>after an asynchronous reset. A synchronous reset would be held until the counter finishes (of >>course, don't apply the synchronous reset to the countdown counter;) > > > > I'd suggest not using "1111...11"s or "000...0"s as the terminal count. If > you've no external asynch reset to intiialise this counter you can't be > sure what state it'll be configured to power up in. I'd suggest that > all '1's or all '0's are the two most likely power up states. > > Use "101010...1010" as your termninal count and the odds are the flip-flops > won't power up to match it. > > > Nial > > > ------------------------------------------------------------- > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk > >Article: 90324
Let me clarify why I am looking for a 3rd party JTAG programming solution. Being relatively new to FPGA design, I am trying to determine if there is a vendor non-specific option available. In other words are there solutions out there that support JTAG programming for Xilinx, Altera, and others? Thanks, Chris
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