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geoffrey wall wrote: > > ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > localhost > java.net.ConnectException: Connection refused: connect > ERROR: Socket communication not open. > Are you using Windows XP? In such case, you should telle the firewall to unblock ChipscopeArticle: 88901
Edit jp2 file and inside the main() delete the call to dbg_test function Regards Javier Castillo On 30 Aug 2005 17:58:49 -0700, "jeff murphy" <jeff.murphy@gmail.com> wrote: >i tried jp2. it doesnt connect at all. more hints welcome! > ># ./jp2 xpc3 9999 >Connected to parallel port at 378 >Dropping root privileges. >JTAG ID = f77db57b >Stall 8051 >RETRY >RETRY >RETRY >RETRY >JTAG ID = f77db57b >RETRY >JTAG ID = f77db57b >RETRY >JTAG ID = f77db57b >RETRY >JTAG ID = f77db57bArticle: 88902
Hi All.. I'm now about to carry a low-power design, I've searched the net for low power design resources, but most of the resources on the web are focused on low power design tactics at the back end. On the other hand, I didn't find any resources about good RTL design techniques for low power, except for the vague 6 pages in the RMM and some other papers that are much concerned with the power estimation rather than power reduction techniques. Anyone has any information, links, or personnal expertise that can share it with me. Best regards, HosniArticle: 88903
Can one use horizontal long lines to pass signals between two modules over a third one in modular-based flow? what about clock nets? how to infer them?Article: 88904
yijun_lily@yahoo.com wrote:
>Hello,
>
>I want to implemented a gated clock signal that is active for only a
>certain period. What is the best way?
>
>I did it like this (I know that is bad)
>
>
then don't (if you know is bad)
leave the clock to run and use CE (chip enable) driven by your counter
to mask the unwanted clock cycles
Aurash
>wire clock_coding;
>assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0;
>
>Thanks,
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 88905I have not seen any material other than device specific marketing push for low power design. Your device choice will likely be the biggest factor. However for low design one the main things to try and do is to either minimise the logic size and compactness. The other area to consider are the amount of flip-flops that toggle, and the toggle rate, and to minimise both these factors. An example of these could be say a state machine where you have choice of the state machine encoding. Using binary, normal incremental, encoding you get an average greater than 1 flip-flop toggling for a machine that transitions to a new state every clock. Now you could use grey encoding for the same machine where only 1 flip-flop toggles. Taking a very simplistic analysis the grey encoded machine is likely to use less power. It isn't a simple area as there are lots of secondary effects when you change something. The area power calculators for both Altera and Xilinx, and probably some others, so best to try out different approaches and see what wins. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <mhosni80@gmail.com> wrote in message news:1125475449.592498.126240@g14g2000cwa.googlegroups.com... > Hi All.. > I'm now about to carry a low-power design, I've searched the net for > low power design resources, but most of the resources on the web are > focused on low power design tactics at the back end. > > On the other hand, I didn't find any resources about good RTL design > techniques for low power, except for the vague 6 pages in the RMM and > some other papers that are much concerned with the power estimation > rather than power reduction techniques. > > Anyone has any information, links, or personnal expertise that can > share it with me. > > Best regards, > Hosni >Article: 88906
On a sunny day (Wed, 31 Aug 2005 01:10:30 +0200) it happened "Pierre de Vos" <pierre.devos@webmail.co.za> wrote in <df2p1d$7bj$1@ctb-nnrp2.saix.net>: >> If you have real _images_ to display then you need some image >> compression, that's quite harder and there is no guarantee that the >> image you'll need to store will be compressible into what space you have. >> >> >> Sylvain >> > >It's a B/W LCD 1 bit per pixel and basically I display line graphics using >an in memory frame buffer and blasting the buffer to the LCD from the CPU. > >Pierre run length encoding?Article: 88907
Although compression seems a good idea... Usually they will take more ram than you save when dealing with a small amount of data. I would suggest connecting to a small static ram or a single DRAM chip... a by anything will do... or even go to a more modern device.. the 1k family is a bit long in the tooth... an EP1C6 will give you ram to spare and is in a 144 TQFP (but has 4 less IO than the 1k30) Simon "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:1125482256.f96740eca6f82634996be6212a89288c@teranews... > On a sunny day (Wed, 31 Aug 2005 01:10:30 +0200) it happened "Pierre de Vos" > <pierre.devos@webmail.co.za> wrote in <df2p1d$7bj$1@ctb-nnrp2.saix.net>: > > >> If you have real _images_ to display then you need some image > >> compression, that's quite harder and there is no guarantee that the > >> image you'll need to store will be compressible into what space you have. > >> > >> > >> Sylvain > >> > > > >It's a B/W LCD 1 bit per pixel and basically I display line graphics using > >an in memory frame buffer and blasting the buffer to the LCD from the CPU. > > > >Pierre > run length encoding?Article: 88908
Hallo, have connected an external signal to my spartan 3. When the external peripheral goes into power down mode, the signal goes into Hi-Z state. I have made a process sensitive to the external signal. if (ext_signal = 'Z') then ... Using this syntax the fpga doesn't "see" the high impdance state and considerthe signal 0 or 1. What could I do? Many Thanks MarcoArticle: 88909
I'm not very fammiliar with the USB protocol, but I think It's an impossible mission.Article: 88910
yijun_lily@yahoo.com wrote: > Hello, > > I want to implemented a gated clock signal that is active for only a > certain period. What is the best way? > > I did it like this (I know that is bad) > > wire clock_coding; > assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0; > > Thanks, This isn't necessarily bad. It's O.K. to gate clocks when they are slow enough to avoid setup or hold issues. The code you wrote would work O.K. if counter increments on negedge clock so you won't glitch when the count changes. In ASIC's you can save power by gating clocks, but in an FPGA you're probably better off using a clock enable, because the clock global routing is already there and flip-flops all come with enable inputs whether you use them or not. Regards, GaborArticle: 88911
Marco wrote: > Hallo, > have connected an external signal to my spartan 3. When the external > peripheral goes into power down mode, the signal goes into Hi-Z state. > > I have made a process sensitive to the external signal. > > if (ext_signal = 'Z') then > ... > > Using this syntax the fpga doesn't "see" the high impdance state and > considerthe signal 0 or 1. > > What could I do? > > Many Thanks > Marco This depends on the normal state of the signal when the peripheral is powered on. For example if it is usually high, you could add a pulldown to the pin and watch for it to go low when the peripheral powers down. If the signal is usually switching, you could add some logic to count time since the last transition and indicate that the signal is inactive if it hasn't changed in some time-out period. You should still place a pullup or pulldown on the I/O to prevent unwanted toggling from noise. If you have several pins connected to the peripheral, you could pull them all down and look for all pins zero. This reduces the chance of mistakenly detecting a powered down peripheral (assuming all pins low is not a typical state of the interface).Article: 88912
Hello, I am looking for an Chipscope-command to put in an Batch-file. I want to read out Data´s over night with CS and write this Data´s in ASCII trough an File. Is there a Command for this? Greetings Peer RoylaArticle: 88913
You need to remember a "Z" is not a third defined state of the signal. The signal will be either 0, 1, or floating between 0 and 1 (that's Z). What you should do is pull the ext_signal either to 0 or 1 and if the external peripheral lets go of the signal you'll know because there will be no activity on the ext_signal for X seconds and the signal will be in a defined 0 or 1 state. You define X. If I knew what your external peripheral was I could help you more. EricArticle: 88914
I wanna implement a digital filter with my XC2S200E, but I'm not very know about DSP theory. I find Xilinx provide MAC FIR and DA FIR cores, but not very know about the difference between them. could anyone give a brief explanation? And, about the coe file. I use Matlab FDATool to design the filter, and know that matlab provide a "coewrite" commond for xilinx FIR core use. but it seems that it could only be used in the DA FIR design. then, how do MAC FIR get the coe file? In my experiment, I generated a MAC FIR core(v3.1 in ISE 7.1iSP3), using the coe file generated by Matlab. I do not know if this coe file is the right one coz I get it from System Generator --> FDATool --> Export coef to workspace --> generate ISE file. Now I simulate it in the ModelSim and all the answer seems ok. when I implement the design, no output arrives, and even no RFD and RDY signal! I don't know what's wrong... the reason why I do not just use the SysGen is that I could not master the realationship between System Clock, sample rate, and simulation period in SysGen. could anyone give some xilinx fir core experience, thanks.Article: 88915
Hi all I want to use FPGAs in 100 or 144 pin quad flat-pack (QFP) packaging. I really want to be able to socket these somehow. Ideally, I want to have a ZIF socket that is soldered to the circuit board, and can hold the chip without any soldering, by pressure alone. Also, I am hoping for the socket to have a lever such that the chip can be inserted/extracted with no force. This operation would hopefully resemble DIP ZIF sockets. Does anyone know where these can be obtained for >$70? Thanks a lot!Article: 88916
"Eric" <ericjohnholland@hotmail.com> wrote in message news:1125496434.910312.279590@g49g2000cwa.googlegroups.com... > You need to remember a "Z" is not a third defined state of the signal. > The signal will be either 0, 1, or floating between 0 and 1 (that's Z). > > What you should do is pull the ext_signal either to 0 or 1 and if the > external peripheral lets go of the signal you'll know because there > will be no activity on the ext_signal for X seconds and the signal will > be in a defined 0 or 1 state. > > You define X. > > If I knew what your external peripheral was I could help you more. > > Eric > It is a 16 bit adc with serial interface. The out of the adc is Z when it doesn't send datas. MarcoArticle: 88917
"Pierre de Vos" <pierre.devos@webmail.co.za> wrote in message news:df2g0c$cji$1@ctb-nnrp2.saix.net... > Hi, > > I've been struggeling with a long standing problem driving a 320x240 > graphic LCD display. I've been using a LCD module with an Epson SED1335 > controller chip. In my application the controller is quite susceptible to > noise - it resets for no reason, exibits distortion of the image. > Googling has come up with some other people also having similar symptoms > with this controller. > > I have mostly overcome the problem by adding additional filtering to the > module - extra caps, ferrite on the cable, but the problem sometimes > persists. > > I've been looking at using a controller-less module and driving it > directly from the FPGA I have on the board. The problem is that the Acex > 1k30 I have on the board only has about 24k memory bits and the memory > buffer for the LCD requires 76k bits (320x240). > > I've been thinking lately that maybe I can compress the memory buffer, > then write it to the FPGA and have the FPGA uncompress the buffer spitting > writing the frame out to the LCD. > > Any ideas on this technique or compression techniques? > > Regards > Pierre > > You could use an external dual port ram: 1) connect one port as read/write to system bus. 2) connect the second port to lcd_data as a rom. 3) create into fpga the clock, syncronization line, syncronization frame and connect it to lcd and the "rom" (second port of ram). After, you should map the external memory into processor address space, as a matrix. Then you could use the matrix variable to write/read into. MarcoArticle: 88918
Brian C. Van Essen wrote: > Well, I have tried to find the reset_trigger_process in all of the > libraries vhdl files, but was unable to. I am guessing that it is part > of a library like unisim (which is commented to be a Xilinx library). > If that is the case, then I am not sure how to correct it if the > library is already compiled. > The unisim library source is in $XILINX/vhdl/src/unisims It does not come precompiled, but is compiled by the person that installed your Xilinx software. It does not contain that function.Article: 88919
If you don't know how to code using clock enables, try something like:
wire enable;
assign enable = (counter > 5 && counter < 120);
always @(posedge clk)
if (reset)
begin
// do reset stuff in here
end
else if (enable)
begin
// do real work in here
end
Hope this helps.
John Providenza
Article: 88920
On Wed, 31 Aug 2005 07:19:41 -0700, dima2882 <vadimv@ieee.org> wrote:
>Hi all
>
>I want to use FPGAs in 100 or 144 pin quad flat-pack (QFP) packaging.
>I really want to be able to socket these somehow. Ideally, I want to
>have a ZIF socket that is soldered to the circuit board, and can hold
>the chip without any soldering, by pressure alone. Also, I am hoping
>for the socket to have a lever such that the chip can be
>inserted/extracted with no force. This operation would hopefully
>resemble DIP ZIF sockets. Does anyone know where these can be
>obtained for >$70?
>
>Thanks a lot!
Don't know about the price ( I bet you really meant "<" ) but this
is the company that makes these sockets:
http://www.yamaichi.com/
Look at Series IC149 and IC51
Philip
Article: 88921peer wrote: > Hello, I am looking for an Chipscope-command to put in an Batch-file. > I want to read out Data´s over night with CS and write this Data´s in ASCII > trough an File. > > Is there a Command for this? The ChipScope Analyzer does not support batch mode scripting commands. You can save the results manually in ASCII file for post processing steps using the GUI. EdArticle: 88922
Currently doing a project in school relating to FPGA. Will try to explore more here and hope to interact with the members here. regardsArticle: 88923
Hi - On 31 Aug 2005 06:35:48 -0700, "Gabor" <gabor@alacron.com> wrote: >yijun_lily@yahoo.com wrote: >> Hello, >> >> I want to implemented a gated clock signal that is active for only a >> certain period. What is the best way? >> >> I did it like this (I know that is bad) >> >> wire clock_coding; >> assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0; >> >> Thanks, > >This isn't necessarily bad. It's O.K. to gate clocks when they >are slow enough to avoid setup or hold issues. If you're clocking everything with a single clock edge, hold time violations are not a function of clock speed; there is no "slow enough." Bob Perlman Cambrian Design WorksArticle: 88924
Hello Daniel, > Digi-Key has stock of the HC4051 from Texas Instruments, STMicroelectronics, > Philips, Fairchild Semiconductor, and Toshiba. > > So what is the problem? Thanks. I realized my error, I was looking at the mil spec parts. Regards, Joerg http://www.analogconsultants.com
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