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Messages from 89600

Article: 89600
Subject: Re: how to set OPB EMC for flash use?
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 20 Sep 2005 15:17:18 GMT
Links: << >>  << T >>  << A >>
Athena wrote:
> Hi Joe,
> 
> Thank you very much for your help, but where did you set these
> parameters as follows:
> 
> PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 90000 ...

Those are for an old obsolete version of opb_emc. Is there some reason 
you are not using a newer version? Download the ipcores updates if you 
have not already done so.

Article: 89601
Subject: Re: how to set OPB EMC for flash use?
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 20 Sep 2005 15:33:08 GMT
Links: << >>  << T >>  << A >>
Duane Clark wrote:
> Athena wrote:
>> Hi Joe,
>>
>> Thank you very much for your help, but where did you set these
>> parameters as follows:
>>
>> PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 90000 ...
> 
> Those are for an old obsolete version of opb_emc. Is there some reason 
> you are not using a newer version? Download the ipcores updates if you 
> have not already done so.

Oops, I see that those were the settings suggested by joe4702. So I 
guess that should be directed at him. Hopefully, you are using a more 
current version of opb_emc core.

With a TE28F640-J3 flash mem, and opb_emc v2.00.a, I use:

  PARAMETER INSTANCE = my_flash
  PARAMETER HW_VER = 2.00.a
  PARAMETER C_NUM_BANKS_MEM = 1
  PARAMETER C_OPB_CLK_PERIOD_PS = 10000
  PARAMETER C_MEM0_BASEADDR = 0x94000000
  PARAMETER C_MEM0_HIGHADDR = 0x94FFFFFF
  PARAMETER C_MEM0_WIDTH = 32
  PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
  PARAMETER C_TCEDV_PS_MEM_0 = 120000
  PARAMETER C_TAVDV_PS_MEM_0 = 120000
  PARAMETER C_THZCE_PS_MEM_0 = 35000
  PARAMETER C_THZOE_PS_MEM_0 = 15000
  PARAMETER C_TWC_PS_MEM_0 = 120000
  PARAMETER C_TWP_PS_MEM_0 = 70000

I have no idea what flash is on the "P160", nor even what that is. But 
the parameters are set in the projects system.mhs file. If you are using 
the GUI, I don't know how to help. I edit the files with a text editor. 
The values are mostly taken right out of the data sheet for the flash 
being used.

> And about how to read data from or write data to the flash, is there 
 > any special methods? Do you have any material or example projects and
 > software codes for the flash on P160 module2? could you gave me some?
> 

Reading from a flash is just like reading from any memory device. But 
writing the flash requires a rather complicated process that is usually 
implemented in software. And there are many different procedures for the 
different types of flash, so you will need to read the data sheet for 
whatever flash you have and implement that (or find someone that has 
implemented it for your specific flash).

Article: 89602
Subject: Re: SoC embedded FPGA
From: Joseph <joseph.yiu@somewhere-in-arm.com>
Date: Tue, 20 Sep 2005 17:11:17 +0100
Links: << >>  << T >>  << A >>
Zara wrote:
> kagior wrote:
> 
>>I saw an interesting STmicroelectonics' chip which embed an ARM9 core
>>and a FPGA, this is the STW21000.
>>
>>Did someone heard about this chip or an equivalent (Áproc + FPGA) ?
>>
>>Where can i buy one or more (less than 10)?
>>
>>thanks
>>
> 
> 
> Xilinx: Virtex-4 FX family, embeds one or two PowerPC, take a look at
> www.Xilinx.com
> 
> I suppose ALtera will have a similar porduct, but I am not familiar with it

Altera has Excalibur, which has an ARM 922T.
But it is not recommended for new products.
(http://www.altera.com/products/devices/excalibur/exc-index.html)
http://www.altera.com/products/devices/arm/overview/arm-overview.html)

Or you can look at Actel solution.
It doesn't have a hard ARM core (not fixed/implemented).
But their tool insert the ARM7 into the design for you.
(http://www.actel.com/products/ip/ARM7.html)

Lattice provide an 8-bit open IP core (not an ARM) for their FPGA/CPLD.
It is a soft core (not fix implemented).
http://www.latticesemi.com/products/devtools/ip/refdesigns/mico8.cfm

Regards,
Joseph

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Article: 89603
Subject: picoblaze IDE for Linux
From: "M6" <m6@xs4all.nl>
Date: 20 Sep 2005 09:16:16 -0700
Links: << >>  << T >>  << A >>
I've created an IDE for the picoblaze-3 microcontroller (Xilinx TM).
The IDE is an open-source project (GPL-license) and works under the
Linux operating system.

The IDE supports the following:
- Editor with syntax highlighting,
- Assemble and export to: HEX, VHDL or MEM files,
- Simulate the source code and see/modify the scratchpad, registers and
I/O ports.

For those who are interested, checkout: http://www.xs4all.nl/~marksix

Regards,

Mark Six


Article: 89604
Subject: Core import into ISE
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Tue, 20 Sep 2005 17:13:13 GMT
Links: << >>  << T >>  << A >>
I'm trying to implement a project in ISE which comprises some logic and an 
Aurora core. I generate the Aurora core OK using the Core Generator but I 
cannot figure out how to bring the core into ISE so that I can add my extra 
logic and then implement the whole thing. I've read as much information as I 
can find but still can't get it to work. The Aurora core User Guide just 
goes on about using Perl scripts to implement the core on it's own but 
that's not what I want to do.

If anyone can help, I'd be grateful.

Thanks.

Rog. 



Article: 89605
Subject: Re: Core import into ISE
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 20 Sep 2005 17:14:55 GMT
Links: << >>  << T >>  << A >>
Roger wrote:
> I'm trying to implement a project in ISE which comprises some logic and an 
> Aurora core. I generate the Aurora core OK using the Core Generator but I 
> cannot figure out how to bring the core into ISE so that I can add my extra 
> logic and then implement the whole thing. I've read as much information as I 
> can find but still can't get it to work. The Aurora core User Guide just 
> goes on about using Perl scripts to implement the core on it's own but 
> that's not what I want to do.
> 

The core is generated in source code form, so you simply include the 
source code into your project. I generally include it as a library, but 
it really doesn't matter; you can just include the source code.

Article: 89606
Subject: OPB bus communication
From: "Nitesh" <nitesh.guinde@gmail.com>
Date: 20 Sep 2005 10:24:48 -0700
Links: << >>  << T >>  << A >>
I have designed a small module usilng vhdl.I converted this module
using IPIF and created an IP.Now I added this IP into my design as a
master/slave module to the OPB bus.I have to inititate a transaction
from my module to the OPB busi.e I want to send some data to the slave
module connected to the opb bus.

One thing I have noticed is that there is no M_Dbus as output of IPIF
to OPB bus.

I enable the IP2Bus_Wrreq(user logic to IPIF) high and wait for the
BUS2IP_wrack signal.But nothing happens.Also there is no change in the
M_request signal of the IPIF(on the OPB bus side)which is steady at 0
The following is the IPIF wrapper:
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    OPB_Clk                        : in  std_logic;
    OPB_Rst                        : in  std_logic;
    Sl_DBus                        : out std_logic_vector(0 to
C_OPB_DWIDTH-1);
    Sl_errAck                      : out std_logic;
    Sl_retry                       : out std_logic;
    Sl_toutSup                     : out std_logic;
    Sl_xferAck                     : out std_logic;
    OPB_ABus                       : in  std_logic_vector(0 to
C_OPB_AWIDTH-1);
    OPB_BE                         : in  std_logic_vector(0 to
C_OPB_DWIDTH/8-1);
    OPB_DBus                       : in  std_logic_vector(0 to
C_OPB_DWIDTH-1);
    OPB_RNW                        : in  std_logic;
    OPB_select                     : in  std_logic;
    OPB_seqAddr                    : in  std_logic;
    M_ABus                         : out std_logic_vector(0 to
C_OPB_AWIDTH-1);
    M_BE                           : out std_logic_vector(0 to
C_OPB_DWIDTH/8-1);
    M_busLock                      : out std_logic;
    M_request                      : out std_logic;
    M_RNW                          : out std_logic;
    M_select                       : out std_logic;
    M_seqAddr                      : out std_logic;
    OPB_errAck                     : in  std_logic;
    OPB_MGrant                     : in  std_logic;
    OPB_retry                      : in  std_logic;
    OPB_timeout                    : in  std_logic;
    OPB_xferAck                    : in  std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

What could be the problem.Is there some other signal that thas to be
tken care of?
Is there some other way other than IPIF that I can add my module as a
master on the OPB bus.
Thanks,
Nitesh


Article: 89607
Subject: Re: Core import into ISE
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Tue, 20 Sep 2005 17:35:06 GMT
Links: << >>  << T >>  << A >>

"Duane Clark" <dclark@junkmail.com> wrote in message 
news:jsXXe.983$OC2.441@newssvr21.news.prodigy.com...
> Roger wrote:
>> I'm trying to implement a project in ISE which comprises some logic and 
>> an Aurora core. I generate the Aurora core OK using the Core Generator 
>> but I cannot figure out how to bring the core into ISE so that I can add 
>> my extra logic and then implement the whole thing. I've read as much 
>> information as I can find but still can't get it to work. The Aurora core 
>> User Guide just goes on about using Perl scripts to implement the core on 
>> it's own but that's not what I want to do.
>>
>
> The core is generated in source code form, so you simply include the 
> source code into your project. I generally include it as a library, but it 
> really doesn't matter; you can just include the source code.

Duane,

Thanks for your reply. I'm trying to use the example supplied from the core 
generator. I've copied the xco file, the frame_gen.vhd, frame_check.vhd and 
the standard_cc_module.vhd into the project and all seems OK but then I get 
the following message:
ERROR:HDLParsers:3014 - "C:/Roger/Xilinx_designs/rio_test/frame_check.vhd" 
Line 54. Library unit AURORA is not available in library work.

There's another step that I seem to be missing. The hassle is due to the 
line in the source: use WORK.AURORA.all;

Any ideas? Thanks. (As you can guess I'm new to this so apologies if I'm 
making a really stupid mistake!)

Rog.







Article: 89608
Subject: Re: Modelsim XE, what's the latest version?
From: sharp@cadence.com
Date: 20 Sep 2005 10:58:24 -0700
Links: << >>  << T >>  << A >>

gallen wrote:.
>
> As far as I know vcs and ncverilog don't have nice guis.  With those
> tools you do everything on the command line.

NC-Verilog has a GUI.  You can invoke it with the +gui option to
ncverilog, or the -gui option to ncsim.


Article: 89609
Subject: Re: problem with Thold violation under quartus
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 20 Sep 2005 11:13:20 -0700
Links: << >>  << T >>  << A >>
pinkotronic wrote:

> But I don't really understand what "Thold" mean.. and i'm not sure my
> solution is to increase it..

Consider a synchronous design.

         --Mike Treseler

Article: 89610
Subject: Re: Core import into ISE
From: Duane Clark <dclark@junkmail.com>
Date: Tue, 20 Sep 2005 18:36:10 GMT
Links: << >>  << T >>  << A >>
Roger wrote:
> 
> Thanks for your reply. I'm trying to use the example supplied from the core 
> generator. I've copied the xco file, the frame_gen.vhd, frame_check.vhd and 
> the standard_cc_module.vhd into the project and all seems OK...

An xco file? Have you registered for and obtained an Aurora license? It 
is free:
http://www.xilinx.com/aurora/register_aurora.htm

Then you should have Aurora source rather than an xco file. I have not 
used an xco file, so I am not sure how to use it.

> but then I get 
> the following message:
> ERROR:HDLParsers:3014 - "C:/Roger/Xilinx_designs/rio_test/frame_check.vhd" 
> Line 54. Library unit AURORA is not available in library work.
> 
> There's another step that I seem to be missing. The hassle is due to the 
> line in the source: use WORK.AURORA.all;
> 

The example is expecting the Aurora core to be in a libarary named 
Aurora. I don't know what to do with an xco file, but with the Aurora 
core in source form in ISE7.1, in the "Sources in Project" window, right 
click on one of the files in your project and select "New Source". In 
the dialog, click "VHDL Library" and enter "AURORA in the File Name box, 
and then click through the dialog.

At the bottom of the "Sources in Project" window, click the "Library 
View" tab. Your new library should be there. Right click on the library, 
and select "Add Source", and add the source.

With an xco file, it looks like you can add that directly to your 
project. Then right click on it and see if it will let you select "Move 
to Library...". I don't know whether that will actually work.

Article: 89611
Subject: XST equivelent for Synplify "synthesis syn_preserve = 1"
From: "Austin Franklin" <austin@darkr00m.com>
Date: Tue, 20 Sep 2005 15:48:53 -0400
Links: << >>  << T >>  << A >>
Hi,

What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for
Verilog)?  I've tried using "
synthesis attribute register_duplication xx "yes" " (closest thing I found
so far that may be what I'm looking for) with xx equal to the module name,
the module instance, the signal...nothing seems to work.  I have register
dulpication selected in the properties for "implement design"...

Any help appreciated.

Austin



Article: 89612
Subject: Re: Generating Modelsim Verilog resource libraries - pointers/questions
From: Garrick <gk@garrickk.net>
Date: Tue, 20 Sep 2005 20:11:17 GMT
Links: << >>  << T >>  << A >>
> OK, I'm using the SE version and it's manuals :)

I've been struggling to figure out the compatibilities between the SE 
and XE worlds.  I've discovered a lot, and have several questions ready 
to drop on Xilinx and Mentor Graphics.  Below is a rant of the things 
I've discovered so far:

1.) We are using ModelSim Xilinx Edition III Starter edition (6.0a). 
It's free and most of our current customers are using it to simulate 
designs for our hardware.  Up to 10,000 lines of HDL code, it's 
suppossed to simulate at 30% the performance of ModelSim PE.  Here are 
the links at Xilinx's webpage the show differences between the XE 
version of Modelsim and the PE version:

http://www.xilinx.com/xlnx/xil_tt_faq.jsp?iLanguageID=1&sProduct=MXE+III
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=17834

In no place at either company's site do they discuss the -nodebug or 
+protect utilization in any formal way.  There is an that says to use 
-nodebug compiled libraries, you must upgrade to Modesim PE or SE.



> 
>> project size, but I am unable to compile a resource library with a 
>> -nodebug flag, and would be unable to use a -nodebug compiled library 
>> if one was supplied to me by a 3rd party.
> 
> 
> I would be suprised if you couldn't use -nodebug library in XE version.
> That is the old way of protecting IP with Modelsim. The problem was that
> it protected the whole modules and tied them to some simulator version.
> -nodebug just removes all visibility from the design module when compiled.
> But I guess you should be asking from Mentor what they suppport in XE.
> There are limitations how -nodebug modules can be used in the hierarchy.
> If I remeber correctly they must be leafs in the design hierarchy, 
> otherwise
> Modelsim can complain quite loudly.
> 
>> It appears as if the `protect compiler directive is supported (at 
>> least initially) in Modelsim XE.  I've placed `protect/`endprotect in 
>> my verilog modules and compiled them using the +protect flag.  They 
>> compile fine with no warnings.
>>
>> However, it doesn't appear as if anything is being protected.  I've 
>> tried putting the `protect/`endprotect both within the module and around 
> 
> 
> I just tried and in SE it works just fine. I used the small example 
> below and
> then commands
> 
> vlib work
> vlog +protect foo.v
> more work/foo.vp (contains file that has the module definition but 
> everything
> else is encrypted).
> 
> foo.v:
> 
> module D_Flop (q, d, clock, reset);
> 
> output q;
> input  d;
> input  clock;
> input  reset;
> reg    q;
> 
> `protect
> 
> always @(posedge clock or posedge reset)
>     if (reset) q <= #1 0;
>     else       q <= #1 d;
> 
> 
> endmodule // D_Flop
> `endprotect
> 
> --Kim

Article: 89613
Subject: EDK libgen cc choice
From: praetorian <Hua.Zheng@jpl.nasa.gov>
Date: Tue, 20 Sep 2005 13:18:33 -0700
Links: << >>  << T >>  << A >>
I'm trying to use an alternative compiler for EDK's libgen (one that 
supports my special FPU). So far all the options that I've explored 
don't work. I've spent hours on the phone with Xilinx's support hot line 
but to no avail. Anybody had any experience with this?

Article: 89614
Subject: Re: Generating Modelsim Verilog resource libraries - pointers/questions
From: Garrick <gk@garrickk.net>
Date: Tue, 20 Sep 2005 20:27:40 GMT
Links: << >>  << T >>  << A >>
Sorry, the previous post was prematurely sent, I'll continue:

There is an Answer Record that says to use -nodebug compiled libraries, 
you must upgrade to Modesim PE or SE.
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=16166&BV_SessionID=@@@@1177595150.1127247013@@@@&BV_EngineID=ccchaddfkfflfmfcefeceihdffhdfjf.0

 > I would be suprised if you couldn't use -nodebug library in XE version.
 > That is the old way of protecting IP with Modelsim. The problem was that
 > it protected the whole modules and tied them to some simulator version.
 > -nodebug just removes all visibility from the design module when 
compiled.
 > But I guess you should be asking from Mentor what they suppport in XE.
 > There are limitations how -nodebug modules can be used in the hierarchy.
 > If I remeber correctly they must be leafs in the design hierarchy,
 > otherwise
 > Modelsim can complain quite loudly.

2. I had an old evaluation version of Modelsim SE 6.0d that I installed 
to test out support between the SE and the XE version.  Resource 
libraries created by the SE compiler were not usable by the XE version - 
regardless of what options I tried!  Even a -refresh from within XE 
wouldn't work (only errors).

Within our Modelsim XE Starter Edition III program, any attempt to 
compile or refresh a library generated by SE 6.0d gave an error message 
that "this library is incompatible with this version of vlog."  Even if 
I created the resource library within SE 6.0d without any compiler 
directives at all.  Clearly, Modelsim XE is only designed to work with 
open libraries.

All libraries generated within Modelsim XE 6.0a work perfectly with 
Modelsim SE 6.0d, even without a refresh on them.  Nothing works in the 
opposite direction.

This is a problem for us that I don't know how we'll resolve.  Too many 
of our customers will be using the Starter Edition for us to offer them 
nothing.

Another small note - the XE compiler generates library directories with 
_primary.dat, _primary.vhd, and verilog.asm files.  It doesn't generate 
a file.vp file.  Aren't these three files effectively encrypted enough 
to protect our code?  We're not concerned with users seeing the signals 
coming out of the ports.

Thanks for your patience.  I guess I need to contact Mentor and find out 
precisely what they recommend for generating libraries used by XE 
Starter Edition users.

Garrick

Article: 89615
Subject: Re: Core import into ISE
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Tue, 20 Sep 2005 20:30:53 GMT
Links: << >>  << T >>  << A >>

"Duane Clark" <dclark@junkmail.com> wrote in message 
news:uEYXe.643$Ur.36@newssvr29.news.prodigy.net...
> Roger wrote:
>>
>> Thanks for your reply. I'm trying to use the example supplied from the 
>> core generator. I've copied the xco file, the frame_gen.vhd, 
>> frame_check.vhd and the standard_cc_module.vhd into the project and all 
>> seems OK...
>
> An xco file? Have you registered for and obtained an Aurora license? It is 
> free:
> http://www.xilinx.com/aurora/register_aurora.htm
>
> Then you should have Aurora source rather than an xco file. I have not 
> used an xco file, so I am not sure how to use it.
>
>> but then I get the following message:
>> ERROR:HDLParsers:3014 - 
>> "C:/Roger/Xilinx_designs/rio_test/frame_check.vhd" Line 54. Library unit 
>> AURORA is not available in library work.
>>
>> There's another step that I seem to be missing. The hassle is due to the 
>> line in the source: use WORK.AURORA.all;
>>
>
> The example is expecting the Aurora core to be in a libarary named Aurora. 
> I don't know what to do with an xco file, but with the Aurora core in 
> source form in ISE7.1, in the "Sources in Project" window, right click on 
> one of the files in your project and select "New Source". In the dialog, 
> click "VHDL Library" and enter "AURORA in the File Name box, and then 
> click through the dialog.
>
> At the bottom of the "Sources in Project" window, click the "Library View" 
> tab. Your new library should be there. Right click on the library, and 
> select "Add Source", and add the source.
>
> With an xco file, it looks like you can add that directly to your project. 
> Then right click on it and see if it will let you select "Move to 
> Library...". I don't know whether that will actually work.

Duane,

Yes, I've got a license. I thought the xco file was some clever way of 
bringing the whole core into the project in 1 easy move - obviously not.

I've done what you suggested and managed to get it working now. Thanks very 
much for your help.

The xco can be added to the project but it can't be moved to the library.

Regards,

Rog. 



Article: 89616
Subject: Re: problem with Thold violation under quartus
From: "Peter Alfke" <peter@xilinx.com>
Date: 20 Sep 2005 14:17:49 -0700
Links: << >>  << T >>  << A >>
Tutorial explanation:
In order to capture data reliably, the D input of each flip-flop must
be valid at least a SET-UP TIME before the active clock edge, and must
be stable until a HOLD-TIME after the active clock edge.
Modern flip-flops never have a positive hold time, and a synchronous
design will have no hold-time issues. But long clock delay differences
can cause the input to change well before the clock edge. Then you can
have a race condition. Unreliable at any clock rate!
Design synchronously, and always use low-skew global clock
distribution!
Peter Alfke, Xilinx
===============
Mike Treseler wrote:
> pinkotronic wrote:
>
> > But I don't really understand what "Thold" mean.. and i'm not sure my
> > solution is to increase it..
> 
> Consider a synchronous design.
> 
>          --Mike Treseler


Article: 89617
Subject: Re: XST equivelent for Synplify "synthesis syn_preserve = 1"
From: "Austin Franklin" <austin@darkr00m.com>
Date: Tue, 20 Sep 2005 17:19:51 -0400
Links: << >>  << T >>  << A >>
I found "equivalent_register_removal", but so far, that hasn't worked
either...but that seems to be the right attribute, now I just have to get it
to work...as register_duplication is apparently not the right attribute.

"Austin Franklin" <austin@darkr00m.com> wrote in message
news:EIZXe.347$X6.321@fe05.lga...
> Hi,
>
> What is the XST equivelent of Synplify's "synthesis syn_preserve = 1" (for
> Verilog)?  I've tried using "
> synthesis attribute register_duplication xx "yes" " (closest thing I found
> so far that may be what I'm looking for) with xx equal to the module name,
> the module instance, the signal...nothing seems to work.  I have register
> dulpication selected in the properties for "implement design"...
>
> Any help appreciated.
>
> Austin
>
>



Article: 89618
Subject: JTAG USB Circuit
From: fecs@usa-dot-com.no-spam.invalid (fecs2)
Date: Tue, 20 Sep 2005 19:16:18 -0500
Links: << >>  << T >>  << A >>
anyboydy knows how to find the circuit or schematic fo make an JTAG
USB  cable?


Article: 89619
Subject: Re: how to set OPB EMC for flash use?
From: Athena <lnzhao@emails.bjut.edu.cn>
Date: Tue, 20 Sep 2005 17:43:42 -0700
Links: << >>  << T >>  << A >>
Hello,

Thank you for your help. I got much from your answer. I will read the related materials much more carefully and try to solve the problem.

Thank you!

Athena

Article: 89620
Subject: Xilinx ISE Passing IO pad attributes using UCF file.
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 20 Sep 2005 18:36:13 -0700
Links: << >>  << T >>  << A >>
Hi,
I am using a ucf file to pass pin location, iostandard, slew rate and
drive strength constraints to the xilinx PAR tools. ISE 7.1 SP4, the
part I am targetting is XC3S50-4TQ144C.

I use the following statement in my UCF file.
INST "potsSdo" LOC = P79 | IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=8;

At the Translate stage of the tools a warning(as below) is issued
telling me that my attribute/contraint is being ignored. (I have 96
other statements in the UCF very similar to the one above, so I am
puzzled that the tools should only complain about this one).

WARNING:NgdBuild:486 - Attribute "IOSTANDARD" is not allowed on symbol
"potsSdo"
of type "FD". This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SLEW" is not allowed on symbol
"potsSdo" of
type "FD". This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DRIVE" is not allowed on symbol
"potsSdo" of
type "FD". This attribute will be ignored.

It would seem from the warning that the tools are trying to apply the
constraint to an "FD" element which I suspect is a D flip flop. Of
course I want the tools to be applying the constraint to the IO PAD
rather than any logic elements inside the design. There were no
warnings issued for the other 96 similar constraints I have in the ucf
file. Any ideas on where to look to figure out why the tools not
applying this constraint to the IO Pad?

I guess I could instantiate the IO pad directly, but why do I need to.
I'm worried there is something more sinister going on here that will
bite when I come to test...

(I have read the Xilinx constraints guide.)

Any ideas, hints etc much appreciated.

Regards
Andrew


Article: 89621
Subject: Re: Xilinx ISE Passing IO pad attributes using UCF file.
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Wed, 21 Sep 2005 02:27:37 GMT
Links: << >>  << T >>  << A >>
Andrew - 

On 20 Sep 2005 18:36:13 -0700, "Andrew FPGA"
<andrew.newsgroup@gmail.com> wrote:

>Hi,
>I am using a ucf file to pass pin location, iostandard, slew rate and
>drive strength constraints to the xilinx PAR tools. ISE 7.1 SP4, the
>part I am targetting is XC3S50-4TQ144C.
>
>I use the following statement in my UCF file.
>INST "potsSdo" LOC = P79 | IOSTANDARD=LVCMOS33 | SLEW=SLOW | DRIVE=8;

I use something like:

NET "net_name" LOC = "AB26" | IOSTANDARD = LVCMOS25 | PULLDOWN ;

where net_name is the name of the I/O signal.

Although I don't use it to create my UCF files, I sometimes employ the
Xilinx constraints editor to determine correct syntax.  (Maybe things
have changed, but the last time I tried to use it for design, the
constraints editor generated UCF files that were far too messy and
verbose for my tastes.) 

Bob Perlman
Cambrian Design Works

>
>At the Translate stage of the tools a warning(as below) is issued
>telling me that my attribute/contraint is being ignored. (I have 96
>other statements in the UCF very similar to the one above, so I am
>puzzled that the tools should only complain about this one).
>
>WARNING:NgdBuild:486 - Attribute "IOSTANDARD" is not allowed on symbol
>"potsSdo"
>of type "FD". This attribute will be ignored.
>WARNING:NgdBuild:486 - Attribute "SLEW" is not allowed on symbol
>"potsSdo" of
>type "FD". This attribute will be ignored.
>WARNING:NgdBuild:486 - Attribute "DRIVE" is not allowed on symbol
>"potsSdo" of
>type "FD". This attribute will be ignored.
>
>It would seem from the warning that the tools are trying to apply the
>constraint to an "FD" element which I suspect is a D flip flop. Of
>course I want the tools to be applying the constraint to the IO PAD
>rather than any logic elements inside the design. There were no
>warnings issued for the other 96 similar constraints I have in the ucf
>file. Any ideas on where to look to figure out why the tools not
>applying this constraint to the IO Pad?
>
>I guess I could instantiate the IO pad directly, but why do I need to.
>I'm worried there is something more sinister going on here that will
>bite when I come to test...
>
>(I have read the Xilinx constraints guide.)
>
>Any ideas, hints etc much appreciated.
>
>Regards
>Andrew


Article: 89622
Subject: Re: JTAG USB Circuit
From: Al Clark <dsp@danvillesignal.com>
Date: Wed, 21 Sep 2005 03:18:40 GMT
Links: << >>  << T >>  << A >>
fecs@usa-dot-com.no-spam.invalid (fecs2) wrote in news:V-
GdndRkpJTPO63eRVn_vA@giganews.com:

> anyboydy knows how to find the circuit or schematic fo make an JTAG
> USB  cable?
> 
> 

I think ftdichip.com has an application

-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Article: 89623
Subject: Re: Modelsim XE, what's the latest version?
From: "do_not_reply" <do_not_reply@nowhere.net>
Date: Wed, 21 Sep 2005 03:27:54 GMT
Links: << >>  << T >>  << A >>
>> As far as I know vcs and ncverilog don't have nice guis.  With those
>> tools you do everything on the command line.
>
> NC-Verilog has a GUI.  You can invoke it with the +gui option to
> ncverilog, or the -gui option to ncsim.

I've also launched ncsim in post-process mode (ncsim +ppe ...)
But I must say, it's hard for me to remember all the necessary
command-line specifiers to select the right 'cds.lib', 'hdl.var', etc.
(I'm really dumb when it comes to design library management!)



Article: 89624
Subject: Re: JTAG USB Circuit
From: "GPE" <See_my_website_for_email@cox.net>
Date: Tue, 20 Sep 2005 22:41:13 -0500
Links: << >>  << T >>  << A >>
Wouldn't it be slick if Xilinx would offer USB as one of the available 
configuration modes for their FPGA config memories!

FTDI does have the hardware, app notes and drivers to write your own JTAG 
programmer.  For us lazy people, I wish somebody had some canned software to 
do this.  Maybe someday I'll get off me buns and do this...

-- Ed


"Al Clark" <dsp@danvillesignal.com> wrote in message 
news:Xns96D7E2F569B9Eaclarkdanvillesignal@66.133.129.71...
> fecs@usa-dot-com.no-spam.invalid (fecs2) wrote in news:V-
> GdndRkpJTPO63eRVn_vA@giganews.com:
>
>> anyboydy knows how to find the circuit or schematic fo make an JTAG
>> USB  cable?
>>
>>
>
> I think ftdichip.com has an application
>
> -- 
> Al Clark
> Danville Signal Processing, Inc.
> --------------------------------------------------------------------
> Purveyors of Fine DSP Hardware and other Cool Stuff
> Available at http://www.danvillesignal.com 





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