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Hi, Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte masking. Did you put the cache into "write back" mode? Hopefully someone with more experience will help us out when they get back from their labor day holiday! Also, I should ask my FAE I suppose! Cheers, Syms. "I. Ulises Hernandez" <delete@e-vhdl.com> wrote in message news:dfhs7e$i4c$1@nwrdmz02.dmz.ncs.ea.ibs-infra.bt.com... > Thanks Symon, > > I had actually enabled the caches and still seems to be performing byte > accesses every now and then... if variables have been defined as 'bytes' > then the compiler seems to be generating Load Byte assembler instructions, > also for strings (I can see in simulation - PPC swift model than 'printf' > for instance is generating PLB byte accesses)... >Article: 89101
Probably the easiest thing to do is uninstall and reinstall both ISE and EDK. Nothing is likely to work if the underlying install is suspect. Paul "zoinks@mytrashmail.com" wrote: > > ok I think I know what is wrong: > > Something went wrong during the installation of the ISE or the SDK. In > my list of available devices, only some spartans and the Virtex2 and > Virtex4 are listed. When I select one of the virtex, the program gives > an error message that it cannot find the specified device size. > > Is there a way to add those devices to the system?Article: 89102
Symon wrote: > Hi, > Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte > masking. Did you put the cache into "write back" mode? > Hopefully someone with more experience will help us out when they get back > from their labor day holiday! Also, I should ask my FAE I suppose! > Cheers, Syms. If it happens rarely you can create a bus error and trap it to a service routine that berforms a 32-bit wide read-modify-write transaction to do the byte write. Of course you can as well add hardware that does this to the memory controller. Also, make sure that the compiler knows that the memory region is cachable. In an embedded world it could be that all addresses default to address space with side effects. In that case the compiler has no choice but to perform access to data of type byte as individual byte accesses. Kolja SulimmaArticle: 89103
If you are using modelsim search their documentation for signal_spy. ALuPin@web.de wrote: > One possibility could be to route the internal signal > to an output pin.=20 >=20 > Rgds > Andr=E9Article: 89104
Signals defined in a VHDL package can be global in scope. -JeffArticle: 89105
Sylvain Munaut wrote: > Not really on topic but why are the caps number in the 300 range on > your DSP card ? like 339 ... > > > Sylvain All parts on page 1 of the schematic are in the 100 range, all parts on page 2 are in the 200 range, ... This makes finding parts on the schematic easy. The only problem I have found with the scheme is when I move parts from page to page it takes some time to renumber. I probably should put up an explanation of my schematic standards. Darrell HarmonArticle: 89106
Hi Austin , Is Xilinx doing more work on this ? Hi All ! I did a simulation use HyperLynx. Below is the circuit: PCI-Driver -------- 15 nH Inductor -------7.6cm,88.5ohms,447ps transmission line ---- ---PCI Receiver ------- 7.6cm,88.5ohms,447ps transmission line ---PCI Receiver. PCI receiver use xc2s200-pq208 PCI33M 5V I think voltage across the Inductor is crossed by ground bounce . Result: When PCI-Driver use xc3s200-pq208 PCI33-3, the max voltage is 490mV. When PCI-Driver use xc2s200-pq208 PCI33M5V, the max voltage is 370mV. Question: This result accords with spartan3-SSO guidelines ( SSO number is 1 for PQ208 ), but not accords with spartan2(SSO number is 4 for PQ208). And my xc2s200-pq208 board works well . Why ?Article: 89107
Your problem may be that the flipflops aren't initialized. If you're building something that depends on the previous state, such as a counter, it will generate XXX unless you have a way to force some known initial state. This could be done using a reset in your code, or by using an initial statement to set up the initial state. Regarding <= vs =, the simple rule is to use <= in an always block. Use = in an assign statement. By the way, a good Verilog reference is http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html. However, it is dated as it's based on Verilog 1995 and doesn't include any of the many improvements. On Thu, 01 Sep 2005 19:37:16 +0100, Philip Pemberton <philpem@despammed.com> wrote: >Hi, > I'm currently designing a disc drive controller to interface with a >6502-based system. To ease the design a little, I've split it up into a few >different modules which are all used by a module called "fdd_top". Now, if I >simulate any of the child modules that fdd_top uses, I can simulate the module >perfectly with Modelsim XE. That, of course, is what is supposed to happen. > The problems start when I try and simulate fdd_top: nothing works! All the >outputs are shown as "X". > Is there some setting in Modelsim or ISE7.1 that I need to tweak to get MXE >to simulate the children as well as the fdd_top module? > > Sorry if this question sounds a bit silly, but I only started learning howw >to use CPLDs last week (using XC9500XL CPLDs, but I want some Coolrunner >XPLA3s to play with - shame no-one seems to want to sell me any - same goes >for the >72 macrocell XC9500XLs). > I've worked out most of the basics of Verilog from studying other people's >code (and reading some of the guides on fpga4fun) but still need to work out >how the "<=" and "=" assignment operators differ, plus other stuff like that. >Not too bad for a week's work I guess :) > >Thanks,Article: 89108
Hello: Quartus 2 Web edition has a build in Modelsim simulator, which seems to work, but: But I can only (so far) simulate using the mouse withing the timing diagram. This is fine and dandy for a clock, but not always enough. Now, the question is: Can you simulate from a testbench file using Quartus 2 Web edition, or do you need to use an external simulator? If yes a pointer would be appreciated. Andre G.Article: 89109
Hi John!
Since you have workable 3s pq208 board , I have a method to test the
ground bounce
rather than simulation.Below is how :
1. Assert pci REQ signal ,request bus.
2. Wait until GNT asserted .
3. Generate an reserved PCI command, assert FRAME.Sine all pci device
will
ignore reserved pci command,we are safe to driver the bus
arbitrarily.
4. While keep FRAME asserted, continuous change pci all signals (all
1->0,0->1
at same time ) except one .
5. Route the "unchanged" signal to a counter's clk pin or enable pin
in fpga,
watch the counter . Or
6. Use oscilloscope whatch and measure the unchanged signal.
7. When all done , deassert PCI FRAME.
I think doing this can get more than simulation.
If you alse think this a good idea , since this can be done without
change
hardware ,can you do it and post the result ?
BTW, did you get more information from XILINX ?
Article: 89110
John,
Sorry for I forgot this :
1.The changed signal must have some loads (no loads, no current ,no
current change)
to watch the effect of ground bounce use any pci signas well but
must be pluged
into computer's slot.
The unchanged signal must be polled down or polled up ,ie,use pci
irdy,stop.
2. Can observ ground bounce by :
a) Use one board to watch effect of ground bounce on input .
b) Use two or more board to watch effect of ground bounce on output.
c) Route the ground bounce effected signal to counter's clk pin to
watch any voltage
change ,to counter's enable pin to watch effect in a clock
system.
Article: 89111VSP wrote: > Hello All, > > I am facing a very bugging problem while using XILINX ISE 7.1i with SP4 > installed. > > Some of my top level ports has been removed by the MAP utility of > ISE.The synthesis is successfully completing without any errors or > warnings. The post synthesis simulation model shows all the ports and > its related logic. > > However after the MAP process has been completed, its throws up a > warning saying that some top level ports has been > removed.(WARNING:MapLib:701 - Signal P_GPIO_3 connected to top level > port P_GPIO_3 has been removed.") > > Please respond if any one has encountered such problems before. > > > Regards, > VSP > Without more details, it is difficult to see what is really happening, but I would check: a) This signal is routed to a PAD. If it is not, and it is an unconnected output, it will be removed b) It is connected to on output pin, but no PAD is automatically created, set option Synthesis/Xilinx Specific Options/Add I/O Buffers to true If it is not so, please send more spsecific info.Article: 89112
You can not use a testbench file which is simulated by Quartus. Use Modelsim stand-alone. Rgds Andr=E9Article: 89113
>I verified that no logic of my design is responsible for that, by >creating a memory from the MegaWizard Plugin Manager and >setting the >memory as the top level module, thus no other logic is there >besides >the memory. So where does your write enable for the memory come from ? Directly from pin or is it an internal logic ? Rgds Andr=E9Article: 89114
Thanks for your replies... See below for my comments. "Kolja Sulimma" <news@sulimma.de> wrote in message news:431c93f2$0$24158$9b4e6d93@newsread4.arcor-online.net... > > Symon wrote: >> Hi, >> Hmm, that's a shame, It'd be nice to save the I/Os I'd need for byte >> masking. Exactly what we thought ;O) >> Did you put the cache into "write back" mode? I am not sure if that is the case, I'll double check! I am not a software expert... just trying to speed up things in this project giving a hand to the softies. I am actually the guy who wrote the HDL for the PPC system on this card and part of it is the PLB_DDR2 controller. >> Hopefully someone with more experience will help us out when they get >> back >> from their labor day holiday! Also, I should ask my FAE I suppose! >> Cheers, Syms. > > If it happens rarely you can create a bus error and trap it to a service > routine that berforms a 32-bit wide read-modify-write transaction to do > the byte write. Ok, I see what you mean... the plan is to use Montavista Linux on the card and I am not sure how easy would be to add such service. I'll check with the software guys. > > Of course you can as well add hardware that does this to the memory > controller. 32-bit wide read-modify-write transaction to do byte writes... that is going to be the solution for the meantime, messy PLB_DDR2 controller but, it will get us further. > > Also, make sure that the compiler knows that the memory region is > cachable. In an embedded world it could be that all addresses default to > address space with side effects. In that case the compiler has no choice > but to perform access to data of type byte as individual byte accesses. I have checked that and it is cacheable... Regards, U. Hernandez > > Kolja SulimmaArticle: 89115
Does anyone know the use of block "*2" (multiplication by 2) in a carry saver adder?Article: 89116
When we worked with one of our leading networking clients last year, they identified Xilinx WASSO (weighted avg SSO) calcs as being "necessary but not sufficient" for project success, and asked us to do something about making it easier to calculate. After our client runs WASSO, they still do a *detailed* SI analysis - but will not invest the time doing so until the WASSO numbers are OK. They even "derate" the passing WASSO levels further. While this may be extra-conservative, their revenues and margins indicate they are doing a lot right :-) We have since integrated WASSO calculations into the latest release of DesignF/X Pin Assignment (DPA), with lots of inputs from users and Xilinx FAEs, on a number of other features as well. (Disclosure: DPA is available only for Xilinx FPGAs at this time, and our company is a Xilinx EDA Alliance Partner.) Of interest to this group and this thread in particular is that DPA is free to use for under 600 pins, WASSO setup is easy, and calculations are updated as pin assignment progresses, along with IO standard assignment, etc. You can download DPA from our website at http://www.prodacc.com Good luck in all your projects! Manu PillaiArticle: 89117
I mean VHDL testbench file.Article: 89118
Hello all, What is the method to isolate a FPGA (XCV600E) from a bus. I am asking this because i observed starnge behaviour while trying it. I am working with a development board from ARM. In two buses are shared by a bus switch and an FPGA (XCV600E). Input to the bus switch (PI3C34X245B) is from the ARM chip which is under software control. And the output is connected to 'A' and 'B' buses. These 'A' and 'B' bus are connected to FPGA which outputs peripheral signals to these buses. In the initial configuration the bus switch was disabled so the 'A' and 'B' was used only for the peripheral control signals. To suit our rquirement we enabled the bus switch and connected the signals from the ARM to these buses and removed all occurance of these buses from the FPGA ( to free the bus fronm the peripheral siganls). Both buses were declared "inout" in the RTL. Assigned high impedance state to both buses. Thus both the buses are now used by the bus switches. But when output all '1' to these buses bit 12 and '0' of the bus A was permanently connected to zero and 'B' was working perfect. But when i changed the direction of 'A' bus in the FPGA to 'in' the problem with a vanished but bit 6 and 16 of 'B' bus was permannently connected to low. What could be the reason behind this starnge behaviour. When i repeated the test several times by varying the status of both buses to 'in' 'inout' 'out' etc each time different bits were found faulty. I am not able to give any logical reason to this strange behaviour. What is the best procedure to completly disconnect FPGA I/O pads from the external bus. If i delete the signal itself from the RTL of the FPGA will that help??? SumeshArticle: 89119
Is it possiable to arrive clock signal to spartan 2e, if I have already used all global clocks (device compromises 4 global clocks). If I arrived input clock signal on I/O pin (not global) ISE 6.3.03 shows me following error: ERROR:Pack:1107 - Unable to combine the following symbols into a single GCLKIOB component: PAD symbol "CLK_1M" (Pad Signal = CLK_1M) GCLKIBUF symbol "clkDAC_bufg" (Output Signal = CLK_1M_BUF) Each of the following constraints specifies an illegal physical site for a component of type GCLKIOB: Symbol "CLK_1M" (LOC=P3) Please correct the constraints accordingly. PLEASE HELP ME!Article: 89120
Hello, I'm trying to use Linux 2.6 on the ML310 Xilinx board with PCI support. After adding the PCI bridge, I generate the BSP headers to compile the Linux kernel. I do __make menuconfig__ and add PCI support but when I __make__ I get the following errors: arch/ppc/syslib/ppc4xx_setup.c: In function `ppc4xx_map_io': arch/ppc/syslib/ppc4xx_setup.c:123: error: `PPC4xx_PCI_IO_VADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:123: error: (Each undeclared identifier is reported only once arch/ppc/syslib/ppc4xx_setup.c:123: error: for each function it appears in.) arch/ppc/syslib/ppc4xx_setup.c:124: error: `PPC4xx_PCI_IO_PADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:124: error: `PPC4xx_PCI_IO_SIZE' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:125: error: `PPC4xx_PCI_CFG_VADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:126: error: `PPC4xx_PCI_CFG_PADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:126: error: `PPC4xx_PCI_CFG_SIZE' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:127: error: `PPC4xx_PCI_LCFG_VADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:128: error: `PPC4xx_PCI_LCFG_PADDR' undeclared (first use in this function) arch/ppc/syslib/ppc4xx_setup.c:128: error: `PPC4xx_PCI_LCFG_SIZE' undeclared (first use in this function) make[1]: *** [arch/ppc/syslib/ppc4xx_setup.o] Error 1 What do I have to do to get rid of these errors? Is there a patch available? Thanks a lot, SvenArticle: 89121
Hello I'm wondering what alternatives I have to GTL on an Spartan 3E. I would like to use an output pin as an open collector output with an external pull-up to 5 Volt. This is to interface 5 Volt logic. On the Spartan 3 we used GTL outputs.Article: 89122
Hello, I think the problem is that your synthesizer is infering a GCLKIBUF for 'clkDAC', exactly what you have told it to do (although you are probably not aware of that) and then when ISE loads the UCF and sees LOC=P3 it can't find a GCLKIBUF allocated to it, just a normal IBUF... you need to tell your synthesizer not to allocate GCLKIBUF for clkDAC... or you could also modify your RTL and connect an IBUF to clkDAC before it starts driving any FF. Regards, Ulises Hernandez "amko" <sinebrate@yahoo.com> wrote in message news:1125999514.520189.221060@g47g2000cwa.googlegroups.com... > Is it possiable to arrive clock signal to spartan 2e, if I have > already used all global clocks (device compromises 4 global clocks). > > If I arrived input clock signal on I/O pin (not global) > ISE 6.3.03 shows me following error: > ERROR:Pack:1107 - Unable to combine the following symbols into a single > GCLKIOB > component: > PAD symbol "CLK_1M" (Pad Signal = CLK_1M) > GCLKIBUF symbol "clkDAC_bufg" (Output Signal = CLK_1M_BUF) > Each of the following constraints specifies an illegal physical site > for a > component of type GCLKIOB: > Symbol "CLK_1M" (LOC=P3) > Please correct the constraints accordingly. > > PLEASE HELP ME! >Article: 89123
Mak wrote: > Hello all, > > I am interested in designing a custom board with serial interface and I > am searching for RS232 port driver ICs which can support baud rates > higher than 230kbps. > > There are many PCI or USB to serial interface options available which > support bauds of upto 920kbps. I have designed a UART interface in FPGA > but need higher baud rate driver ics to actaully get the performance I > require. > > Any recommendations? Yes, use the FT232 RS232 to USB converter for a desktop application. The cable then is USB and the baudrates reach 1Mbit. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 89124
The wren port is set to 0, so that no writes occur out of the logic. Sebastian. Am Tue, 06 Sep 2005 08:45:28 +0200 schrieb <ALuPin@web.de>: >> I verified that no logic of my design is responsible for that, by >> creating a memory from the MegaWizard Plugin Manager and >setting the >> memory as the top level module, thus no other logic is there >besides >> the memory. > > So where does your write enable for the memory come > from ? Directly from pin or is it an internal logic ? > > Rgds > André >
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