Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
(my response is all the way @ the bottom) On 16 Sep 2005 09:42:25 +0200, David Brown <david@westcontrol.removethisbit.com> wrote: >Jim Granville wrote: >> they call me frenchy wrote: >> >>> On 15 Sep 2005 10:35:32 +0200, David Brown >>> <david@westcontrol.removethisbit.com> wrote: >>> >>>> Unless you have complex timing requirements, a small micro would be >>>> the best for making 3 PWMs. Get a small msp430 processor - they are >>>> cheap, easy to work with, and have good free tools (the gcc port is >>>> excellent, and there are free versions of ImageCraft and IAR tools >>>> for limited program sizes). >>> >>> >>> >>> >>> David, >>> Thank you very much for your response. I am new to programmable logic >>> and I really appreciate the suggestion. Just to make sure that I >>> paint the entire picture, here are my full requirements... >>> >>> 1) 3independent PWM generators running at the same frequency. I am >>> starting with 8-bit, but I could justify going down to 7bit and >>> maaaaaaybe 6 or even 5 bit if it will save me much grief. >>> >>> 2) The FSM will probably have 8 states (cylcled through with a simple >>> pushbutton, no reset). State 1 will tell PWM1 to run at 90% and PWM2 >>> and 3 to be off. The rest of the states will turn the PWMs off and on >>> in a variety of ways. The most complex of the states will tell all 3 >>> PWMs to cylce from 10% to 90% out of phase from each other at about >>> 0.5Hz. I do not have complex timing requirements. >>> >>> 3) I would like to detect the battery voltage and when it is running >>> semi low, I would like to scale down the values of ALL PWM signals to >>> extend battery life. For example, full battery = all PWMs @ 100%, >>> battery 1/2 dead = all PWMs @ 50%, battery pretty much dead = sleep >>> mode until the batteries start to receive a recharge, which could be >>> several hours away. >>> >>> I got a Coolrunner II development kit just to get going with a >>> 256macrocell chip onboard. I will plan on testing my functionality on >>> that even if I fill the whole damn thing and then perhaps migrate to >>> your recommended MSP430 after some research to prove why that would >>> indeed be better than a CPLD. >>> >>> My application is geared towards a very high quantity consumer part, >>> so I would like to see the chip cost under US$1 at quantity. I know >>> that I have an uphill climb in front of me and my boots are on. >> >> >> This does not sound like a CPLD problem. A fundamental determinant in >> cost is pin count, and there are no 8 or 14 pin CPLDs. >> CPLDs also have narrow Vcc tolerance, and in some cases, need Two supplies. >> You will also find the 10-20uA the CPLD vendors boast of, is MUCH higher >> than the Static Icc of Microcontrollers. There are no CPLDs with low >> power on-chip oscillators... >> >> You have not mentioned the PWM frequency, but the usage and action >> sounds like a lighting effects one, so you do not need the 300Mhz clock >> rates of a CPLD. >> >> Do a pin-count budget, and then choose a 8 pin or 14 pin >> Microcontroller. [I'd start with 14, and then see if it will fit in 8, >> when you are all done] >> >> For 8 & 14 pin Microcontrollers, look at >> Atmel, Freescale, Microchip, Philips, ST, TI, Zilog (etc) >> >> This application will move across uC quite easily, so choose the >> one that looks easiest for you to learn, and get it working on that, >> then start the bidding process, when it hits real volume :) >> >> >>> If I indeed switch over to a MSP430, will my VHDL code that I am >>> writing now be able to come with me? >> >> >> NO, but the ideas will. >> > >Additionally, if you want to measure battery voltage, you'll need some >sort of ADC. There are lots of small micros with an ADC, whereas with a >CPLD you'd need an external ADC. > >I think Atmel have some new AVR chips aimed specifically at lighting >applications, with very flexible PWM outputs. I don't know the details, >but they'd be worth a look. > >Your software is going to be vastly easier to write and test in C on a >microcontroller, rather than VHDL on a CPLD. The responses from both David Brown and Jim Granville have been infinitely helpful. What an idiot I am. You both hit the nail on the head...the application is indeed a lighting effects one. Independently controlling 3 LxExDs (or6)(or9)(or12)(or15) only requires a PWM frequency of 100Hz to a couple kHz. I suppose that it is just stupid to be looking @ a CPLD, especially when power consumption and price are very important driving factors. I guess in my mind I knew that the PWM frequency could be low, but that all of the logic required was complex and needed a much faster clock. As I mentioned previously, I am just getting back into electronic design for the 1st time pretty much since college. I have never used a uC before and I gravitated to Xilinx because I took a introductory FPGA course in college and I knew that it would functionally accomplish most of my requirements (I used one to simulate the insides of a pop machine). The fact that I have never used a uC before really bit me in the a$$. Thank you for your patience! I am about done with my 1st run of VHDL code and about ready to program my CoolRunnerII 256 for the 1st time (everything is simulating great). I will finish that in order to test my optics & LxExD driving circuits and meanwhile I will indeed look into the uC solutions that both of you presented above. I appreciate your input. You will probably hear from me again in the coming weeks. BTW, what is the most appropriate newsgroup for my new uC path? infinite gratitude, frenchyArticle: 89501
vssumesh wrote: > Ok ... But what about the dynamic property of the routing. Is the PAR > tool wil cnsider all the possibilites that may arise only at working > time. > Kolja are you suggesting a manual duplication or the method suggested > by the Muravin. > There aren't any issues with implementing what you want (a register with a fanout of 172 loads in a Virtex FPGA). Virtex FPGAs use a fully buffered interconnect which means that every time a routing resource connects to another routing resource it goes through a buffer that is appropriately sized for the wire that it drives. In Virtex any single buffer/wire should see only 1-3 loads with the exception of a "long wire" that covers the length or width of the device that might see up to 20 loads depending on the device size. The timing analyzer will correctly report the timing of the net depending on the resources that are used. EdArticle: 89502
On Thu, 15 Sep 2005 21:51:19 +0100, "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote: >Hi, > >Ha!!! What they do is PDM pulse density modulation not PWM, >may work the same for you... don't know, depends on how you use it. >The PWM-pulse width modulation with a constant single >output frequency with variable duty cycle, must be with a count and compare >;) > >> Although I will not be using a LPF >> in my application, I remember his statement about logic. > >So, that is the problem... after a low pass filter both are equal, and PDM >is more >tolerant on filtering, but for direct use they are different ! >think well if PDM does the same for you or not :) > >...me, controlling step motors didn't had much luck with it ;) > >lc. > Aha, I see. I will be driving normal L..E..D..s and now that I understand the difference between PWM and PDM, I ask the following question... Since I want to keep system cost to a minimum, I should avoid adding an extra LPF....will PDM work, or should I just stay with PWM? I will research this tomorrow, but feel free to comment if you like. thanks for your input, Luis! frenchyArticle: 89503
"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> schrieb im Newsbeitrag > Aha, I see. I will be driving normal L..E..D..s and now that I > understand the difference between PWM and PDM, I ask the following > question... > > Since I want to keep system cost to a minimum, I should avoid adding > an extra LPF....will PDM work, or should I just stay with PWM? I will > research this tomorrow, but feel free to comment if you like. For driving LEDs you dont need (and dont should use!) a LPF (low pass filter). The filtering is done by the eyes/brain ot the observer. Just keep the PWM frequency high enough to avoid flickering (100 Hz ++). The only thing you need is the current limiting resistor. Regards FalkArticle: 89504
Yannis Koryfidis wrote: > We have a ParallelCable IV but it seems that the "STATUS" led is not lighted > at all. Could it be the problem? Yes, this indicates that the cable is not powered. It will not work without a power supply. Why do you think there is a power-connector on the cable? > Moreover, there is no PS2 port since the board is connected to a laptop. > Any ideas why ?? You need to connect an external 5V power-supply to the power connector. cu, SeanArticle: 89505
Brad Smallridge wrote: > Hello group, > > Can anyone tell me about the ML403 kit that Xilinx now advertises > on there home page? You can buy the ML403 in two ways. First as a stand alone unit that is does not include any design software or cables for $495 that has everything shown here: http://www.xilinx.com/ml403 Second in a kit form that includes everything in the ML403 stand alone version, plus EDK, ISE (BASE-X Version), and a JTAG download cable (PC-4 or USB)for $895 ($400 more). More information can be found here: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-ML403-EDK-ISE > Specifically, is there any source code for it? Do you pay the $895 > and get all the software you need, or are there hidden cost for > IP modules and the compiler software for the hard PC? We do provide the EDK projects for each of the reference designs that ship with board and all of them can be downloaded from the links found on the above links. The $895 kit includes everything that you need to be able to rebuild any of the reference designs and to create new designs or software for the PowerPC and MicroBlaze designs. Some of the IP modules included in EDK do require additional licensing cost, but you have access to evaluation versions of the cores. You can find a complete breakdown of the peripheral cores and if they are require additional licensing here: http://www.xilinx.com/ise/embedded/edk_ip.htm > Generally, I notice that the speed grades for the Virtex4 seem about > twice that of the Spartan3s, although the fabric looks the same for > the casual reader. Is the speed grade more a function of the Virtex4 > IO SERDES functions, and not the fabric? At one point in time the speed grades were directly correlated with a timing parameter in our FPGAs. This became unworkable a few generations ago and now the numbers are intended as an relative indication of speed with in the Fabric within the same Family. > And on the IOs, can the SERDES be used to accept a Camera Link > specified 60MHz times 7 = 420MHz input rate on the specified 16 > LVDS pairs? Or do I need RocketIO or MGT for this? I am not familiar with the Camera Link protocol, electrical or AC timing specs, but at 420 Mbps this would be below the low end data rate for the RocketIO MGTs. It may be possible to over sample the data to drop down this low, but it would have to be carefully looked at. Please keep in mind that the IO SERDES blocks are just serializers and deserializers logic and do not include a CDR (Clock Data Recovery) block. This means that you have to have the necessary clock sources and alignment logic also present in your design. EdArticle: 89506
Dear everybody, I have two dubious about using the DEV_CLRn and CRC_ERROR pins on ALTERA Cyclone. If the DEV_CLRn pin is LOW during FPGA configuration, does the active configuration (AS) take place since the device's internal registers are cleared by DEV_CLRn ? I would like to enable the CRC_ERROR feature but I don't know what to do when this pin goes active. Do I have to restart the configuration making a transition on CONFIGn ? Do you suggest something else ? Best Regards /AlessandroArticle: 89507
>I have a question that is more theoretical than practical: > But why is this loop nessecary to create this behaviour? > I know it's a bit vague, but I didn't find to much detailed > info on it ... > Can someone please explain me the working of this system, or give me a > link to a place on the net where I can find it? For a well written explanation of one of the uses of DCM, I would go to Xilinx Application note 462 XAPP462 and begin reading around page 25, Eliminating Clock Skew.Article: 89508
Neill A wrote: > I've just started looking into getting our VHDL code into some sort of > version control tool, and would like to get some information about > which ones work best with VHDL & FPGA tools. If you set up your directory structures with some thought, and you use Makefiles and shell scripts to do the builds, your files will all be text and basically any version-control system will be fine. Don't expect any of the FPGA vendors to add SCC hooks into their software. > All our designs are done using Actel Libero, and AFAIK it doesn't > provide any helpful features for version control. I have previously > used SourceSafe for a little while, but since we are just a small > company I think the cost is a bit much. I use Subversion (http://subversion.tigris.org/). It's free, it's well-supported, and unlike VSS, it doesn't suck (or eat your repository). There's an excellent Windows Explorer shell tool called TortoiseSVN (http://tortoisesvn.tigris.org/) that puts useful icon overlays on all files that are under version control, as well as adding context-menu commands. Recommended. -aArticle: 89509
Thanks Ed, > Second in a kit form that includes everything in the ML403 stand alone > version, plus EDK, ISE (BASE-X Version), and a JTAG download cable (PC-4 > or USB)for $895 ($400 more). More information can be found here: Last time I priced the PC4 USB cable was around $500. So I suspect that I'm getting a pretty good package? > Please keep in mind that the IO SERDES blocks are just serializers > and deserializers logic and do not include a CDR (Clock Data Recovery) > block. This means that you have to have the necessary clock sources > and alignment logic also present in your design. As far as I understand the Camera Link interface, the clock is sent along with the data on a separate LVDS pair. The specification wants a National chipset to render the LVDS pairs to TTL/CMOS levels, but I'm thinking that the Xilinx part should be able to handle it. > We do provide the EDK projects for each of the reference designs that > ship with board and all of them can be downloaded from the links found > on the above links. I found these descriptions listed below in one of the user guides. I see some USB software but more related to hardware peripherals. Is there a way to write data from a host computer GUI down to the Xilinx fabric so that I type a number into my computer, and some register in the fabric changes to match that value? Best Regards, Brad Smallridge aivsion.com bootload Displays menu on VGA/LCD/Serial Port and loads appropriate ACE file based on user input. sw/standalone/bootload/ button_led_test Turns on LEDs when buttons are pressed. sw/standalone/button_led_test/ flash_hello Program designed to be loaded from linear flash describing the process by which it was loaded. sw/standalone/flash_hello/ flash_load Program that loads data from System ACE CompactFlash cards and programs them into FLASH memory. sw/standalone/flash_load/ flash_test Program that writes and reads FLASH to test it. sw/standalone/flash_test/ hello Using C's studio library, prints Hello world! and echoes characters entered via standard input to standard output. sw/standalone/hello/ hello_uart Using the EDK UART driver, prints Hello world! on the UART and outputs characters entered via standard input to standard output. sw/standalone/hello_uart/ iic_eeprom Writes test pattern to IIC and reads back data (Note: This test will overwrite the contents of IIC only if enabled to do so.) sw/standalone/iic_eeprom/ my_ace Program asking user to create their own ACE file. sw/standalone/my_ace/ my_plat_flash Program asking user to load their own design into Platform Flash. sw/standalone/my_plat_flash/ plat_flash_menu (ML401 only) A Program listing the demos available on the Platform Flash. sw/standalone/plat_flash_menu/ ps2_scancodes_polled Polled, reads keystrokes on a keyboard attached to PS/2 port 1 and displays corresponding PS/2 scancodes on standard output. sw/standalone/ps2_scancodes_polled/ simon Simon game using LCD, LEDs, and buttons on the ML40x. sw/standalone/simon/ slideshow Reads audio and video files from CompactFlash via System ACE and displays a slideshow accompanied by music. sw/standalone/slideshow/ sysace_rebooter Program that asks user with which System ACE configuration to reconfigure. sw/standalone/sysace_rebooter/ test_ac97 Program that records sound from the Line- In/Microphone inputs, stores the audio data into DDR memory, then plays the sound to the Line-Out and Headphone outputs. sw/standalone/test_ac97/ testfatfs Simple test program that reads files from CompactFlash via System ACE interface. sw/standalone/testfatfs/ usb_hpi_test Echoes characters typed on a USB keyboard to the LCD and serial port on the ML40x. sw/standalone/usb_hpi_test/ usb_printer Prints Hello World! to a USB printer. sw/standalone/usb_printer webserver Implements a webserver that displays ML40x DIP switch settings and controls LEDs. sw/standalone/web_server/ xrom ML40x board test and diagnostic program. sw/standalone/ml40x/sw/standalone/xrom/Article: 89510
On Fri, 16 Sep 2005 18:39:59 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: > >"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> >schrieb im Newsbeitrag > >> Aha, I see. I will be driving normal L..E..D..s and now that I >> understand the difference between PWM and PDM, I ask the following >> question... >> >> Since I want to keep system cost to a minimum, I should avoid adding >> an extra LPF....will PDM work, or should I just stay with PWM? I will >> research this tomorrow, but feel free to comment if you like. > >For driving LEDs you dont need (and dont should use!) a LPF (low pass >filter). The filtering is done by the eyes/brain ot the observer. Just keep >the PWM frequency high enough to avoid flickering (100 Hz ++). The only >thing you need is the current limiting resistor. > >Regards >Falk > > Right, but my question (as elementary as it may be) was whether PDM would work for such an application or whether PWM is preferred for any particular reason. Both of them seem to acheive the same thing in different ways assuming the frequency is adequately high. grusse, frenchyArticle: 89511
I posted this in another thread, but didn't hear from anyone. Maybe here it will get more exposure? I'm beginning to question the organization of the fuse map in a HAL. It doesn't seem to be related to the datasheets. I've collected a lot of data so far and have outlined it below. Here is an x-ray of the actual package to show where the bond wires go: http://media.diywelder.com/images3/091405-HAL16R8chip2_Image412.jpg Here is the whole chip: http://media.diywelder.com/images3/091205-wholechip_IMGP2074.jpg Here is the map which is connected to "Pin 2", but the connections to the fusemap seem to indicate pin 3: http://media.diywelder.com/images3/091205-FusemapMap-IMGP2067.jpg Here is the fuse map schematic for pin 2. Note the locations of the input and feedback fuses. http://media.diywelder.com/images3/091105-PALdatasheetimage.jpg Can anyone give me any insight? Will I have to translate the location of the vertical fuse columns to what they "should be" in a GAL? Thanks, GrantArticle: 89512
Thanks Sean. I will try to connect the cable PS2 to a power source. Forgive me that I neglected the power ;) "Sean Durkin" <smd@despammed.com> wrote in message news:3p0bffF7nt9sU1@individual.net... > Yannis Koryfidis wrote: >> We have a ParallelCable IV but it seems that the "STATUS" led is not >> lighted >> at all. Could it be the problem? > Yes, this indicates that the cable is not powered. It will not work > without a power supply. Why do you think there is a power-connector on > the cable? > >> Moreover, there is no PS2 port since the board is connected to a laptop. >> Any ideas why ?? > You need to connect an external 5V power-supply to the power connector. > > cu, > SeanArticle: 89513
"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> schrieb im Newsbeitrag > Right, but my question (as elementary as it may be) was whether PDM > would work for such an application or whether PWM is preferred for any > particular reason. Both of them seem to acheive the same thing in > different ways assuming the frequency is adequately high. For LEDs, PWM is just as good as PDM. PDM has the advantage that you can use lower clock frequencies, but this is not a real advantage. Regards FalkArticle: 89514
I'm not sure if anyone on this group has toyed with the CVS/Ritz one-time-use cameras by PureDigital or not, but they have a control ASIC made by SMaL technologies, which uses the Arclite MicroRISC 8-bit core. I have had no luck getting information from Arc about the core, though a thorough web search turned up a cached support page from VAutomation. >From this support page, a disassembler and assembler were written (not by me, mind you - the disassembler was done by a guy named John Maushammer, and the assembler is based on a MAME assembler that was converted by a guy named Bill Wiley) So, I have the instruction set, including flags, and a (very) basic knowledge of the interrupts (I know where the vectors are). What I would like to do is round out my info on the processor, though. Does anyone have any datasheets, or other documentation on this core? For example, I would really like to know if the core has an interrupt architecture built in, or if you have to add that yourself. I realize the core itself is commercial IP - I'm not looking for that - just any help in understanding how it works. What exactly did you get with the V8/Arclite MicroRISC core, and what did you have to write yourself? BTW - I do not have regular access to this newsgroup. Please cc jshamlet@gmail.com with replies. Thanks! -Seth HenryArticle: 89515
Thanks for your help. I have another observation I would like to confirm. It seems that the MSR[29] carry bit, used to determine if the fifo has data, is set by control reads and is not set by data reads. Tbis bit is used by a lot of instructions and as such is not "sticky" like the FSL_Error bit. Has that been your experience?Article: 89516
Brad Smallridge wrote: > Last time I priced the PC4 USB cable was around $500. > So I suspect that I'm getting a pretty good package? The PC-4 cable sells for $95, and the Platform USB cable sells for $149. You must be thinking of the now obsolete MultiLinx USB cable. It's still a really good value priced package if you don't have a current copy of EDK. If you already have our SW tools (EDK and ISE) then you would be better off buying the non-bundled version. Oh, and there is also an optional accessory set that has all of the cables that you might want to use with the board for an extra $50. > As far as I understand the Camera Link interface, the > clock is sent along with the data on a separate LVDS > pair. The specification wants a National chipset to render > the LVDS pairs to TTL/CMOS levels, but I'm thinking > that the Xilinx part should be able to handle it. If this is true, then you should be able to create a quick and dirty card to plug onto the Xiling Generic Interface (XGI, aka BERG. Also since I didn't explicitly mention this before, the RocketIO MGTs are not in the FX12 part that is on this board. We are creating a similiar version with a FX20 part, but this won't be out until next year. > I found these descriptions listed below in one of the user guides. > I see some USB software but more related to hardware peripherals. > Is there a way to write data from a host computer GUI down to > the Xilinx fabric so that I type a number into my computer, and > some register in the fabric changes to match that value? > And this is where we get off the pre-canned design examples and it becomes an "excerise left to the user".... > > usb_hpi_test > Echoes characters typed on a USB keyboard > to the LCD and serial port on the ML40x. > sw/standalone/usb_hpi_test/ I think that this would meet your request more or less. This is done with a USB keyboard instead of computer and the register is the LCD panel, but it should provide the basis for the design that you want to implement. Usually when we are creating user controlled input designs we opt to implement them through the UART instead of USB as it's a much easier, but you can certainly do this with a ML40x. EdArticle: 89517
Hi All, I want to use the flash on the P160 Module, but I don't know how to set the opb EMC(external memory controller) for flash. Does anyone knows? Please help me. thank you very much! LinaArticle: 89518
The DEV_CLRn to the best of my knowlege has nothing at all to do with the cofiguration mode Cyclone will be set to. The mode is set via the mode select pins. I don't know of any CRC_ERROR pins on the Cyclone either. CRC is, to the best of knowledge, something that happens under the hood during configuration, see below. Cyclic redundancy code (CRC) circuitry validates each data frame (i.e., sequence of data bits) as it is loaded into the target device. If the CRC generated by the device does not match the data stored in the data stream, the configuration process is halted, and the nSTATUS pin is pulled and held low to indicate an error condition. CRC circuitry ensures that noisy systems will not cause errors that yield an incorrect or incomplete configuration. Take care, Rob <alessandro.strazzero@virgilio.it> wrote in message news:1126890874.993877.227310@g44g2000cwa.googlegroups.com... > Dear everybody, > > I have two dubious about using the DEV_CLRn and CRC_ERROR pins on > ALTERA Cyclone. > > If the DEV_CLRn pin is LOW during FPGA configuration, does the > active configuration (AS) take place since the device's internal > registers are cleared by DEV_CLRn ? > > I would like to enable the CRC_ERROR feature but I don't know what > to do when this pin goes active. Do I have to restart the > configuration making a transition on CONFIGn ? Do you suggest > something else ? > > Best Regards > > /Alessandro >Article: 89519
On 16 Sep 2005 13:52:05 -0700, "logjam" <grant@cmosxray.com> wrote: >I posted this in another thread, but didn't hear from anyone. Maybe >here it will get more exposure? Probably not. We all read the same news group and articles. >I'm beginning to question the organization of the fuse map in a HAL. >It doesn't seem to be related to the datasheets. I've collected a lot >of data so far and have outlined it below. You do seem to be having too much fun. Considering the performance of todays PCs, it would seem you could get to a solution by doing an exhaustive search with a PC controlling the device via some simple circuitry hanging of a printer port. It seems you have hung much of your analysis on the assumption that the chip layout should follow the diagrams in the data book. There is no such requirement, and it would surprise me if you did find a perfect match. The diagram in the data book is laid out for easy of viewing and presenting a logical view of the functionality of the device. The chip layout is laid out to minimize area, to leverage repeated structures, to meet power/noise/other requirements. For example, in the data sheet you see the FF feedback coming across the fuse array as two adjacent lines. But if the Q and Q-bar outputs were not adjacent as they come out of the FF structure, then on the chip the lines may not be adjacent. It is also very common to see structures that share something are laid out as alternating normal lay out and then mirrored layout, so that the shared resource (a signal line, a power/ground, a control line) is only needed once per pair of things. >Can anyone give me any insight? Will I have to translate the location >of the vertical fuse columns to what they "should be" in a GAL? Hope the above helps expand what you are looking for. I still think that a PC based sw/hw exploration would get you to a complete picture with a few days of programming (changes as you learn stuff), and probably less than an hour of CPU time. FYI: The HAL products were promoted as Hard Array Logic, with the intent of mask programming the devices for high volume cost reduction. In fact many HAL devices were just normal PALs that were programmed at the factory. Have you plugged the device into a PAL programmer and seen if it can be read back? I hope so. >Thanks, >Grant Philip Freidin MMI FAE 1980-1983Article: 89520
hi, i bought both spartan3 starter kit and USB2 module from digilent. i tried working with USB2 module plugged in to A1 expansion connector, and it worked well. However when using A1,the IO pins are shared with RAM, and i want to use both USB2 moodule and RAM simultaniously. Therefore i switched the board to B1 expansion and made necessary changes in the pin assignment user constraints. With the USB 2 module in B1 expantion slot, i tried both Slave/Master Serial/Parallel mode of programing through ExPort programe. I changed all jumpers as requred ( including TDO/TDI bypass). However ExPort is unable to find the scan chain in all modes. im sure the USB module connection is OK, because it is shown in the list when i try to add modules. It complaints about identifing invalid devices. if some one knows the reason, please let me know, because im stuck with that. Thank you CMOSArticle: 89521
On 2005-09-16, Mike Harrison <mike@whitewing.co.uk> wrote: > >>FOR SOLUTION-2 that >> Websites to Get economical chips of SDRAM nad VRAM > Easiest way to get chips would be to strip them off a module > >>FOR SOLUTION-3 that >> Links Where to get SSDRAM Socket.... >> Suggestion to do it on Single sided PCB... > > Digikey stock a range of sockets. For a standard Unbuffered SDRAM, the part number is WM1712-ND > > Digikey stocks Micron now. No need to strip chips off a module. Darrell Harmon http://dlharmon.com/dspcardArticle: 89522
Yes, Its read as nothing. I've read a bunch on reverse engineering and PALs, but have not found any information on brute force methods. In fact all I found were testimonials about Apple using PALs to slow down people copying their computers. Also heard a few people talking about IBM slowing down the first clone with a state machine PAL in the FPU? I try not to do TOO much book learning without actually getting dirty, but from what I heard its pretty hard to guess a PALs function by logic tests. Would the program you suggest I write already have a hint of what the PAL does and test for input sequences that make sense for THAT PAL? I know what this "ASG" PAL does, and I'm trying to ignore it. You're right, I am having too much fun. :) A lot of things I do once, and afterwards pledge to never do again. This may be one of them, but at least its looking possible. ;) I've printed out photos of the fuse maps and by Saturday night Alaska time should have a working replacement. :)Article: 89523
Hi! I was wondering if anyone has any recommendations for software that is designed for drawing architectural level diagrams or block diagrams for hardware design. (lets say a microprogrammed pipelined processor). Currently I am using Microsoft Visio 2003, and its okay, but it never hurts to try and find something better (if you know what I mean) :) Also does anyone know what software tools are used to draw the timing diagrams in various datasheets? Any help will be highly appreciated! Thank you!Article: 89524
Telenochek wrote: > Hi! > I was wondering if anyone has any recommendations for software that is > designed for drawing architectural level diagrams or block diagrams for > hardware design. > (lets say a microprogrammed pipelined processor). > Currently I am using Microsoft Visio 2003, and its okay, but it never > hurts to try and find something better (if you know what I mean) :) > > Also does anyone know what software tools are used to draw the timing > diagrams in various datasheets? > > Any help will be highly appreciated! > Thank you! Yes I spent several months preparing a paper (on a pipelined processor) and docs trying to use relatively free software Windows like Open Office but the graphics really just were awefull. I remembered how much fun I had on the old Mac 20yrs ago with MacDraw so I dug up Canvas by deneba who also did a Windows version starting around early 90s. Basically its a CAD program as easy to use as the old MacDraw but much more powerful, it doesn't do the links thing like Visio or OO but after using OO version of that I got sick of that feature in a hurry. In canvas when you need to make up arrays it figures how to auto step & repeat, many Win programs copy right on top of same, what good is that. It allows hierarchy grouping ungrouping etc. Its stipple pattern choices are very dated though right out of MacPaint 1 1984. You can control your grid and resolutions. Its follows good interface design and installs by just dragging (old version). It starts in <<1s while OO,Acrobat_reader starts in 10-20secs. Overall I found I could do all my schematic and other drawings in a half hour instead of hitting the wall. Downside of course these schematics are for artwork only, not machine readable. Works well with OO etc and the final PDFs looks good. They are still around but seem to have moved on to high end drawing. >From the web its looks familiar but the price is much higher (about same as Visio). It started out life as a $50 desk accessory. You can probably find quite a few Windows native CAD programs (some even free) but I always find they get the whole user experience wrong in some terrible way, I have tried way too many and forget them. regards johnjakson at usa dot_com... PS if you want to see what my graphics look like, drop a note, may take a week though.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z