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Hi After some have reported success with the ise 7.1.04i i tried to get the impact running. The installation was running setup_pcusb editing usb_usermap and replacing the 7 with the 9 so that fxload was started for the xup board. I tried Centos 3 (which didn't work at all since impact segfaulted every time when issuing "setMode -bs") Debian Sarge with 2.4.6. and WinDriver v6.03 (orig xilinx) or v7.01 gives: // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port ttyS1 -baud -1 Reusing A1022C81 key. Connecting to cable (Usb Port - USB22). Checking cable driver. File version of /iss/share/linux/xilinx/ise71/bin/lin/xusbdfwu.hex = 101 (dec), 03FA. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 03FA. Cable connection failed. // *** BATCH CMD : setCable -port ttyS1 -baud -1 Reusing A1022C81 key. Connecting to cable (Usb Port - USB22). Checking cable driver. File version of /iss/share/linux/xilinx/ise71/bin/lin/xusbdfwu.hex = 101 (dec), 03FA. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 03FA. Max current requested during enumeration is 150 mA. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1018. CPLD file version = 0006h. CPLD version = 4311h. // *** BATCH CMD : Identify PROGRESS_START - Starting Operation. Identifying chain contents ....read count != nBytes, rc = FFFFFFFF. read failed FFFFFFFF. '1': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. Any ideas to resolve this issue are apreciated STArticle: 89726
Stephen Craven wrote: > I stumbled across a presentation at MAPLD regarding various C-to-gates > tools. The authors at U of F compared several tools to a pure VHDL > implementation and discovered that for each application (FIR filtering, > N-queens, and radix sorting) a particular C-to-gates tool, usually > Handle-C, beat a hardware designer using VHDL. > > The presentation can be viewed at: > http://klabs.org/mapld05/presento/215_holland_p.ppt > > This goes against my common beliefs regarding hardware designers being > many times more efficient. > > Does anyone have experiences with C-to-gates tools that would bolster > or contradict the authors' claims? > > Stephen At cpa2005 I saw something like MAPD - C-Gates discussion using simulink as a bridge. I think most EEs using Verilog or VHDL would think differently. What HandleC does well is in figuring out possible mappings from C to hardware but the performance I usually see isn't anything to write home about. In FPGAs the fully automatic approach usually peaks at 80MHz while many EEs routinely work at 150-300MHz. That means about 4x less hardware for the same job or 4x more performance. If you only want to prototype an idea in hardware, then HC is probably okay assuming you can eat the rather stiff license. Most of the applications you mentioned (except perhaps N Queens) are relatively simple and can be done by EEs in hours (not secs) and can also be done with free software. EEs also have available a vast breadth of specialized techniques available that can be used to further reduce HW or increase speed, I don't believe much of that knowledge can be encoded into HandelC. I think the HandelC results will get better by simply absorbing many more predefined parameterized solutions that have been pre built in HDL and glued together within the DK framework, atleast thats what I see at Celoxica shows these days. They have a nice board with lots of standard I/O ports with ready made IP cores you can glue together within the tool and use HandelC for whatever else they didn't give you. regards at usa dotcomArticle: 89727
S.T. <st@iss.tu-darmstadt.de> wrote: > Debian Sarge with 2.4.6. and WinDriver v6.03 (orig xilinx) or v7.01 gives: Kernel 2.4.6? This is pretty old, albeit the real problem I suggest you first update your kernel. > // *** BATCH CMD : setCable -port ttyS1 -baud -1 ttyS1 is a serial (probably rs232) port. I don't own a usb cable, but even if it emulates a serial port I guess it won't be called ttyS1 (ttyS1 is usually the second serial port, in DOS-speak COM2). It should also be noted that it is always a good idea to use up-to-date cable drivers, at least my parallel cable needs the new windriver (>7.0.0) if I don't want to patch it for using it with kernels newer than 2.6.11. -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Wenn die Kuh am Himmel schwirrt, hat sich die Natur geirrtArticle: 89728
Simon, Firstly, congratulations on having parents who can spell. Secondly, you may be interested in this link:- http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm Lots of good stuff, complete with a link to this:- http://www.fpga-faq.org/archives/59375.html#59399 a simple and reliable circuit posted by Rick Collins to transfer a flag from one domain to another. Cheers, Symon. p.s. Isn't Google ads great? At the bottom of the above linked page, I saw an advertising link for beach footwear! Guess which type.... "Simon Heinzle" <sheinzle@student.ethz.ch> wrote in message news:4333e8e2$1@news1.ethz.ch... > To exchange flags (1 bit signals) between two unrelated clocks, a single > synchronizer flip flop to clock that signal is used normally. However, under > violations of setup/hold times of the flip flop, metastability can occur. > > On a Virtex2 Pro, does metastability occur often? Does adding a second (or > even third) flip flop after the synchronizer flip flop help or is that > overcautious? > > Best Regards, > Simon Heinzle > > >Article: 89729
Simon, metastability is a problem that cannot be "solved", we can only reduce the probability of errors due to metastability. The extra delay at the Q output of a flip-flop (or latch) with undefined timing relationship between D and Clk is theoretically unbounded. This can be a surprise to digital designers who are accustomed to deterministic behavior. Metastability is not deterministic, it is a statistical phenomenon. The good news is that modern CMOS flip-flops and latches recover very fast, within a few ns, as shown in the Xilinx app note XAPP094, which is based on actual measurements, not on theory. In many cases you will find that the mean-time-betwen-failure is millions or billions of years. Just make sure that the data path from the metastable-going flip-flop to the (single!) next synchronizing flip-flop is as fast as possible. No extra logic, absolutely minimal routing delays. Peter Alfke, Xilinx ApplicationsArticle: 89730
Brad Smallridge wrote:
> Well, maybe you can show me an example, because I simply
> don't get it. You say you instantiate the CPU, memory, etc,
> but how does the simulator know what is connected to what?
>
> Perhaps you can snip out one of your test-benches designs with
> bidirectional signals for me and the group?
Here's a rough skeleton. Assume your FPGA's top-level entity is called
mychip, and the SRAM entity is called sram.
library ieee;
use ieee.std_logic_1164;
entity mychip_tb is
generic (
CLKPER : time := 10 ns;
RESETTIME : time = 123 ns);
end entity mychip_tb;
architecture testbench of mychip_tb is
-- globals:
signal SysClk : std_logic;
signal Reset_l : std_logic;
-- SRAM interface:
signal RamAddr : std_logic_vector(18 downto 0);
signal RamData : std_logic_vector(15 downto 0);
signal RamCs_l : std_logic;
signal RamWe_l : std_logic;
signal RamOe_l : std_logic;
begin -- architecture testbench
u_dut : entity work.mychip
port map (
SysClk => SysClk, -- global clock
Reset_l => Reset_l, -- global reset
RamAddr => RamAddr, -- SRAM address bus
RamData => RamData, -- SRAM data bus
RamCs_l => RamCs_l, -- SRAM chip select
RamWe_l => RamWe_l, -- SRAM write enable
RamOe_l => RamOe_l); -- SRAM read enable
u_sram : entity work.sram
port map (
addr => RamAddr, -- SRAM address bus
dq => RamData, -- SRAM data bus
cs_l => RamCs_l, -- SRAM chip select
we_l => RamWe_l, -- SRAM write enable
oe_l => RamOe_l); -- SRAM output enable
ClkGen : process is
SysClk <= '1';
wait for CLKPER;
SysClk <= '0';
wait for CLKPER;
end process ClkGen;
ResetGen : process is
Reset_l <= '0';
wait for RESETTIME;
Reset_l <= '1';
wait;
end process ResetGen;
end architecture testbench;
Article: 89731I'm trying to play with the OPB MCH DDR controller (multichannel ddr controller) on Microblaze platform, on S3. Unfortunately, I have no example to start with. Even on Xilinx site I found not so much help. I saw on the ML403 user guide that with that board comes an example: reference_systems/EDK_projects/ml403_dcm_phase_shift that seems to fit. Even if the ML403 is Virtex 4-FX based, this design uses a Microblaze. I don't really know if asking for a copy of this to some kind people is a copyright violation; I own a full license of EDK, ISE, and a Memec demo board, but no really useful examples to start. I'm just asking for a little help to make me purchase more chips, sooner :-) I would prefer not to have to purchase the V4-FX board, because my design will be S3 based, and my board already has DDR. Can anyone help ? Meanwhile, I'll ask my FAE, but with the Memec / Avnet fusion still to settle, now it's not a good period to ask for help...Article: 89732
Does anyone know of another forum or website where I can get an answer to my question? Thanks. Peace, MohArticle: 89733
I strongly recommend Veritak: www.sugawara-systems.com it works for me for 100K+ designs and the GUI is friendly and very stable. Veritak is $50 and right now it is 1/2 the speed of ModelSim PE (their entry-level paid version). You can try Veritak for free for two weeks and after that you need to buy the license.Article: 89734
Nitesh wrote: > Hello Moh, > I have only one master So there is no problem of arbitration I guess. > > The problem is that the M_request remains constant at '0'. with no > change even when I try to request a master write operation in my > user_logic.vhd > > I enable my IP2bus_wrreq high place a valid address and data on the > IP2bus_addr,IP2bus_data, > IP2Bus_Retry <='0'; > IP2Bus_Error <='0'; > IP2Bus_ToutSup <='0'; > IP2Bus_RdAck <='0'; > IP2Bus_WrAck <='0'; > > My only doubt is what address should we assign to IP2IP_addr. > I think thta is the one which gives the problem. IP2IP_addr must be the address inside your ip address range where you want the data to be 'written' (or read). So if you ask for a master read from 0x10000000 (IP2Bus_addr) to 0x20000000 (IP2IP_addr) (with 0x2000000 being in the address range assigned to your IP), your slave interface will see signals as if someone was trying to write to 0x2000000 from the exterior. Not sure i'm very clear ... SylvainArticle: 89735
You are right, you have to pay all of $50 for a very good GUI: Veritak 1.75a www.sugawara-systems.com RAULArticle: 89736
Thanks. Your comment forced me to closely examine my XCF file. It turned out to be pilot error - I was missing a semicolon at the end of line. Doh! Now it's working. -BrianArticle: 89737
shorty wrote: > Was just told about this site at National Semiconductor. Great idea. > Means I no longer need to worry too much about my power management > for all my Altera FPGA designs - they support Xilinx too ! Check it > out at > > http://www.national.com/appinfo/power/xilinxfpga.html The best device for power management IMHO is the power manager from Lattice. What I like best about these devices is that they are programmable and don't need any discretes to monitor from 1v to 5.75v. Since I'm using fpgas, why shouldn't power sequencing be programmable too! The software is simple GUI based and the reprogrammability has saved my bacon on more than one occasion. http://www.latticesemi.com/products/ispPAC/POWRMGR/index.cfmArticle: 89738
can u get these drivers online or do u have to create one?Article: 89739
Hi all! I need to make wireless device using 802.11g or something else. I check some chips but here is PCI or USB interface. Both are too complex for my purposes, and PCI have big problem - amount of wires. That can you recommend for this case? Is here solution with easy host interface usable for microcontroller or FPGA?Article: 89740
Although I know that modern development has long since bypassed the Excalibur for processor+FPGA design, it happens to be the perfect vehicle for my prototype. If someone has one they'd like to part with, I'd like to talk. Thanks.Article: 89741
I got that part.I have a user space of 256 bytes with 4 bytes per block.So the ip2ip_addr address which I am assigning is also correct but still I cannot get any change on M_request signal. I have gone through the opb manual and also the opb ipif signals manual but I still cannot figure out the solution.Article: 89742
Hi, Recently I noticed that Xilinx FPGA has RocketPHY 10Gbps serial interfaces using 64B66B encoding. However, it seems to have no FEC built in the hardware. Is this a problem? At 10Gbps, the channel won't be clean. There has to be some FEC one way or the other. Can we really let go FEC at 10Gbps (e.g. relying on DFE) ? Or perhaps user needs to build their own FEC in the FPGA to use it along? Anyone had experience on this? In addition, any other FPGA vendor having 10Gbps serial port FPGA chips? thanks, -- FrancisArticle: 89743
francisontheweb@yahoo.com wrote: > Hi, > > Recently I noticed that Xilinx FPGA has RocketPHY 10Gbps > serial interfaces using 64B66B encoding. However, it seems > to have no FEC built in the hardware. Is this a problem? > At 10Gbps, the channel won't be clean. > There has to be some FEC one way or the other. Howdy Francis, Why won't it be clean, and why do you feel there must be FEC? While OC-192 has the option for FEC, it isn't required. Same for 10 Gbps Ethernet. > Can we really let go FEC at 10Gbps (e.g. relying on DFE) ? Yes - many applications do so. I assume DFE stands for decision feedback equalizer? If so, I think it's a safe bet that many (most? or possibly all?) 10 Gbps receivers have some sort of equalization. > Or perhaps user needs to build their own FEC in the FPGA to > use it along? Anyone had experience on this? I'm certain it could be done, if your application needed the extra coding gain. > In addition, any other FPGA vendor having 10Gbps serial port > FPGA chips? No, not yet. Several others provide bonding of four 3.125 Gbps channels to get you the effective rate in excess of 10 Gbps. Have fun, MarcArticle: 89744
On 23 Sep 2005 06:51:59 -0700, "Anuja" <thakkar.anuja@gmail.com> wrote: >i dont want to use Impact.. the project requires me to write APIs in C >code such that i can download the bit file w/out using any special >software Well, even the code you write is "special" :-) You may find the following helpful: http://www.fpga-faq.org/FAQ_Pages/0038_Config_FPGA_from_a_processor.htm Basically, you need some type of interface from your software to the FPGA hardware for configuration, JTAG is an example, and the Xilinx Serial Slave mode is another. The serial slave mode is the simplest. you need a clocl line, a data line, a program line, and a way to read back done and init. With software you shift the data out 1 bit at a time to the data pin, and you make the clock signal go high and low with software too. This is how the old Xilinx parallel download cable works (for both serial slave and JTAG modes). You should be totally confused by now. Let me try and help: The parallel download cable is called parallel because it uses the parallel port of the PC. BUT it is used to send data serially (one bit at a time) by directly controlling turning various bits of the parallel data on and off. One of these bit is used as the serial slave clock, and another is used for serial slave data. Have a look here at what Xilinx has inside their cable: http://toolbox.xilinx.com/docsan/data/alliance/jtg/fig26.htm Once you understand this, everything else is easy :-) Philip Philip Freidin FliptronicsArticle: 89745
Using a VirtexE part. I have two banks of registers. One is actually a 32-bit counter running real slow at 1KHz (1mS time tag). The other is a set of data registers that run anywhere from 100Hz to 100MHz. I need to register the time tag set of registers into the variable frequency registers at predetermined... but variable intervals. I can't do a majority vote with either clock because I don't know which will be running faster and I only have a couple clock periods to live with as far as delay. I draw a blank on this one, does anybody have any ideas to this predicament? I tried doing this with simple registering from one set to the other... And, as expected, I run into metastability problems several times per second. TIA, EdArticle: 89746
If I understand you right, you need to copy the 32-bit counter ontent (which changes very slowly) into a fast-changing (fast-clocked) register at asynchronous times. I am sure that your problem is not metastability, but rather timing uncertainty between the 32 register bits. My suggestion is to run the 32-bit counter as a Gray counter. Since only one bit changes at any time, a not-totally-synchronous transfer never results in a serious error. Afterwards, you can convertthe gray code back to binary. Binary-to-Gray conversion uses one XOR per bit, and is very fast. Gray-to-binary involves a ripple chain, and may be more challenging at 100 MHz, but I suppose you can do it off-line. Or you pipeline the operation. As is often the case,,mtastabilty gets blamed here for a completely different (and more solvable) problem. Peter Alfke, Xilinx ApplicationsArticle: 89747
Hi! Can somebody give me some advices about jbits. I want to use it in reconfigurable computing. What are its limits. Is it useful? Some one already told me "Jbits is dead" but didn't explain why ! MehdiArticle: 89748
Hey Andy, Thanks for the help. I wrote the testbench below based on what you are saying. However, I can't figure out how to get the memory model library to load. Once I have that figured out, I'll let you know. Brad library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity toptb is end toptb; architecture Behavioral of toptb is component top3 port( x2clk : in std_logic ; reset_pin_in : in std_logic ; vga_hsync_out : out std_logic; vga_vsync_out : out std_logic; vga_rgb_red_out : out std_logic_vector(9 downto 0); vga_rgb_green_out : out std_logic_vector(9 downto 0); vga_rgb_blue_out : out std_logic_vector(9 downto 0); vga_clk_out : out std_logic; vga_synct_out : out std_logic; vga_sync_out : out std_logic; vga_blank_out : out std_logic; -- to SRAM sramclk : out std_logic; -- clock srama : out std_logic_vector(20 downto 0); -- address sramdqa : inout std_logic_vector(9 downto 1); -- data a sramdqb : inout std_logic_vector(9 downto 1); -- data b srame1 : out std_logic; -- chip enable 1 sramba : out std_logic; -- a data write enable srambb : out std_logic; -- b data write enable sramw : out std_logic; -- write enable -- from Xilinx U2 u2clk : in std_logic ; cam_line_in : in std_logic; -- via board VGADAT9 cam_data_in : in std_logic_vector(8 downto 0); -- TPA Switch tup_in : in std_logic; -- P198 tdown_in : in std_logic; -- P197 tleft_in : in std_logic; -- P194 tright_in : in std_logic; -- P196 tcenter_in : in std_logic; -- P199 -- Test led_out : out std_logic; test_out : out std_logic ); end component; component G8320Z18T GENERIC ( CONSTANT ramtype : integer := 1; -- NBT=1 Burst=0 CONSTANT ramversion : integer := 1; -- 4->+1 RAM CONSTANT density : integer := 32; CONSTANT byteparl : integer := 4; CONSTANT A_size : integer := 21; CONSTANT DQ_size : integer := 9; CONSTANT bank_size : integer := 1024 * 2048;-- *32M /4 bytes in parallel CONSTANT tKQpipe : real := 3.4e+00 ;--166MHZ CONSTANT tKQflow : real := 8.0e+00) ;--166MHZ PORT ( SIGNAL A832 : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte A data SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte B data SIGNAL nBa : IN std_logic;-- bank A write enable SIGNAL nBb : IN std_logic;-- bank B write enable SIGNAL CK : IN std_logic;-- clock SIGNAL nCKE : IN std_logic;-- clock SIGNAL nW : IN std_logic;-- byte write enable SIGNAL nE1 : IN std_logic;-- chip enable 1 SIGNAL E2 : IN std_logic;-- chip enable 1 SIGNAL nE3 : IN std_logic;-- chip enable 1 SIGNAL nG : IN std_logic;-- output enable SIGNAL pADV : IN std_logic;-- Advance not / load SIGNAL ZZ : IN std_logic;-- power down SIGNAL nFT : IN std_logic;-- Pipeline / Flow through SIGNAL nLBO : IN std_logic);-- Linear Burst Order not end component; signal sramclk : std_logic; -- clock signal srama : std_logic_vector(20 downto 0); -- address signal sramdqa : std_logic_vector(9 downto 1); -- data a signal sramdqb : std_logic_vector(9 downto 1); -- data b signal srame1 : std_logic; -- chip enable 1 signal sramba : std_logic; -- a data write enable signal srambb : std_logic; -- b data write enable signal sramw : std_logic; -- write enable begin u3_spartan3 : top3 port map( x2clk => x2clk, reset_pin_in => reset_pin_in, vga_hsync_out => vga_hsync_out, vga_vsync_out => vga_vsync_out, vga_rgb_red_out => vga_rgb_red_out, vga_rgb_green_out => vga_rgb_green_out, vga_rgb_blue_out => vga_rgb_blue_out, vga_clk_out => vga_clk_out, vga_synct_out => vga_synct_out, vga_sync_out => vga_sync_out, vga_blank_out => vga_blank_out, sramclk => sramclk, srama => srama, sramdqa => sramdqa, sramdqb => sramdqb, srame1 => srame1, sramba => sramba, srambb => srambb, sramw => sramw, u2clk => u2clk, cam_line_in => cam_line_in, cam_data_in => cam_data_in, tup_in => tup_in, tdown_in => tdown_in, tleft_in => tleft_in, tright_in => tright_in, tcenter_in => tcenter_in, led_out => led_out, test_out => test_out ); u21sram : G8320Z18T port map( A832 => srama, -- address DQa => sramdqa, -- byte A data DQb => sramdqb, -- byte B data nBa => sramba, -- bank A write enable nBb => srambb, -- bank B write enable CK => sramclk, -- clock nCKE => '0', -- clock enable nW => sramw, -- byte write enable nE1 => srame1, -- chip enable 1 E2 => '1', -- chip enable 1 nE3 => '0', -- chip enable 1 nG => '0', -- output enable pADV => '0', -- Advance not / load ZZ => '0', -- power down nFT => '1', -- Pipeline / Flow through nLBO => '0'); -- Linear Burst Order not u2clk_proc : process is u2clk <= '1'; wait for 8 ns; u2clk <= '0'; wait for 8 ns; end process; x2clk_proc : process is x2clk <= '1'; wait for 20 ns; x2clk <= '0'; wait for 20 ns; end process; reset_pin_in_proc : process is reset_pin_in <= '0'; wait for 100 ns; reset_pin_in <= '1'; wait; end process; cam_proc : process is cam_line_in <= '0'; cam_data_in <= (others=>'0'); wait for 64 ns; cam_line_in <= '1'; cam_data_in <= "001100000"; wait for 32768 ns; -- 2048x16ns end process; tpa_proc : process is t_up <= '0'; t_down <= '0'; t_left <= '0'; t_right <= '0'; t_center <= '0'; end process; end Behavioral;Article: 89749
Hallo, I have used one core downloded from "opecores.org" into a project which will be a commercial microcotroller. Which are the commercial conditions about selling it into the complete system? Many Thanks Marco
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