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Well, This is where I would start. If you are familiar with hardware architecture in terms of what performance you need and how fast or parallel processing required (no VHDL needed!), you may choose one mathematically familiar implementation, among several FFT implementations, you can image the architecture in terms of multipliers && accumulators && registers (let's call it microarchitecture of your design). One you have done that, the rest is piece of cake, really. Study VHDL, do some minor projects for a few days and then you would be able to estimate your performance better than anybody in this newsgroup. There is a way to have FFT as a core / reference, but i would not recommend this, if the goal is to study FPGAs. Hope this helps. Vladislav "biot" <biot.spm@gmail.com> wrote in message news:1126681614.779175.35990@g14g2000cwa.googlegroups.com... > > Hi members, > I am a student and completely new to FPGA. I am learning VHDL. My > objective is to implement FFT in spartan-3 starter kit. I would like to > know how many months it will take me to fully design it. As a novice i > would like to know few suggestions and references for my project. I > need help. I don't know from where to start. >Article: 89401
S V S, There should be no problem with what you describe here. The place and route tool will use LUTs for routing, if there is not enough interconnect. The place and route tool may multiply the FF, depending if there is another one, so that there are two "sampling" stages. Vladislav "vssumesh" <vssumesh_asic@yahoo.com> wrote in message news:1126671718.653020.252000@f14g2000cwb.googlegroups.com... > Hello all, > In my design there is a possibility (its dynamic) that a register > may get connect to inputs of 172 gates. Is this possible on Virtex E or > any other xilinx FPGA. And is it possible in the real silicon i am > asking about industry standards. Or is there any other way i can achive > this. By changing my design etc. > Sumesh V S >Article: 89402
Why not designing a FIFO on your own? V "Remco" <whybcuz@yahoo.com> wrote in message news:1126643665.621179.25160@g44g2000cwa.googlegroups.com... > Hi all > We've set up a simple FIFO on a Spartan3 FPGA using the free code from > Xilinx XApp258 (FifoCTLR_IC_V2.vhd) > Initially this mechanism was tied to a DMA and we were having a hard > time figuring out what was going on. > By process of elimination, we tied the FIFO to an address and used the > read/write strobed to read and write to the fifo. > > We can scribble data and read it back. > The weird thing we're seeing is that the "empty" does not become true > until data is read for the first time. It also becomes untrue with data > left in the FIFO (usually 2 longs remaining). > > Has anyone seen this before? Or do we need to pay for the libary to get > it fixed :) > > TIA > Remco >Article: 89403
Paul, You are not the first to be amazed by this result. I can only add that I was not able to persuade my management to give me Dual AMD 64 due to some unfixable bug (in the management), so I have only P4 :( I am sure that Xilinx software is always being developed && improved to match any future stuff Vladislav "Paul Gentieu" <pg8192@yahoo.com> wrote in message news:ee900d0.-1@webx.sUN8CHnE... > Here's a benchmark for PAR (high effort level) running on two different > CPUs. The design utilized about 40% of an XC2V4000-5 and had some > difficult-to-meet timing constraints. PAR's peak memory usage was ~500 MB. > > Intel Pentium D 830 (3.0 GHz), 2 GB RAM: Total CPU time to PAR completion: > 2 hours 32 mins > > AMD Athlon 64 4000+ (2.4 GHz), 2 GB RAM: Total CPU time to PAR completion: > 1 hour 2 mins > > I was blown away by the result. I was expecting a modest speed increase > with the AMD- maybe 1.3x, if you go by the model number- but certainly not > 2.5x. Based on this benchmark, the AMD CPU should actually be called a > 7500+. :) > > The Pentium is a dual core and the AMD is a single, but the Xilinx > software utilizes only one core so this is a fair comparison of raw > processor speed. > > The Pentium probably gets killed by its deep pipelines. I'd guess that > PAR, like most real-world apps, consists mainly of spaghetti code rather > than regular loops processing masses of similar data. So the Pentium > spends a lot of its time flushing pipelines because of mispredicted > branches and such. It probably suffers from its higher memory access > latency as well. > > It sure would be nice if Xilinx could made their software multithreaded... > then an Athlon X2 4800+ would really scream. As it is, I'd guess that an > Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently > possible. > > -PaulArticle: 89404
> It sure would be nice if Xilinx could made their software multithreaded... then an Athlon X2 4800+ would really scream. As it is, I'd guess that an Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently possible. > > -Paul PAR is multithreaded, use the -m switch.Article: 89405
Hello, I'm a soft designer. I want to access Spartan board with JTAG interface. I do not have kwoledge about electronic. I try to send/read informations according to TAP controller sequence. I can read IDCODE and set the board in BYPASS mode. When I try to send instruction with Impact (to instruction register), the instrcution is not understood. Must I do something like initialisation before sending instruction code? How can I debug this situation without eletronic equipment ? -- Digonnet Daniel COPALP 10, Rue de Chamechaude 38360 SASSENAGE - FRANCE Tel : ++33 (0)4 38 26 00 75 Fax : ++33(0)4 76 26 34 17 Mail : dd@copalp.com www.copalp.comArticle: 89406
Vladislav Muravin wrote: > Why not designing a FIFO on your own? > > V > Yeah, that's what we're doing now. It is just that when they give you the freebie library of components why re-invent the wheel, right? Of course, their %#$%$%$^@# component doesn't work for crap, so they basically steer you down a dark alley for a day or so. We had it integrated in a DMA mechanism and when stuff doesn't work, you don't immediately assume it is the commercially availbable component -- one would hope they test their junk before it is thrown over the wall (I guess they didn't). So the first thing you assume is bad is your own code.. I guess you get what you pay for. Remco > > "Remco" <whybcuz@yahoo.com> wrote in message > news:1126643665.621179.25160@g44g2000cwa.googlegroups.com... > > Hi all > > We've set up a simple FIFO on a Spartan3 FPGA using the free code from > > Xilinx XApp258 (FifoCTLR_IC_V2.vhd) > > Initially this mechanism was tied to a DMA and we were having a hard > > time figuring out what was going on. > > By process of elimination, we tied the FIFO to an address and used the > > read/write strobed to read and write to the fifo. > > > > We can scribble data and read it back. > > The weird thing we're seeing is that the "empty" does not become true > > until data is read for the first time. It also becomes untrue with data > > left in the FIFO (usually 2 longs remaining). > > > > Has anyone seen this before? Or do we need to pay for the libary to get > > it fixed :) > > > > TIA > > Remco > >Article: 89407
Re-phrase the question, because you cannot remove I/O port which exists in the design. Because it's like asking "can i use 16K RAM block without actually consuming it?" V "geoffrey wall" <wallge@eng.fsu.edu> wrote in message news:dg4n2j$dqk$1@news.fsu.edu... > how can you reduce the number if IOBs a design uses > during synthesis? > > thanks > > -- > Geoffrey Wall > Masters Student in Electrical/Computer Engineering > Florida State University, FAMU/FSU College of Engineering > wallge@eng.fsu.edu > Cell Phone: > 850.339.4157 > > ECE Machine Intelligence Lab > http://www.eng.fsu.edu/mil > MIL Office Phone: > 850.410.6145 > > Center for Applied Vision and Imaging Science > http://cavis.fsu.edu/ > CAVIS Office Phone: > 850.645.2257 >Article: 89408
> PAR is multithreaded, use the -m switch. The -m does not work on Windows, according to the documentation. This is silly because they should be using cross-platform code anyway. A decent Windows pthread library utilizing termination drivers is not that expensive. I fully agree that they should be using SSE, SSE2, SSE3, 3dNow, etc., along with utilizing Intel and AMD's math/DSP libraries. Even if they have to ship different EXEs for each processor it would totally be worth it.Article: 89409
Finn, For this kind of accuracy in delivery, I would suggest you work directly with the distributor, your FAE, or the factory (depending on how large the order is). Distributors are averse (they resist) having shelf stock, as shelf stock is money they spend, and do not have money to show for it. It is a bit of a problem for us, as we would like to have shelf stock for customers, so the wait times get reduced. Unfortunately, distributors do have a business to run, and they decide how much to stock. We have some say in this. I suspect that we have stock here at the factory (actually Ireland, not San Jose), and so we can respond very quickly to a large order. Smaller orders go through distribution, and it is up to them to decide how much stays on their shelves in anticipation of orders. Austin Finn S. Nielsen wrote: > Does anyone know what the current delivery situation is for > XC3S1000-5FT256C. > On Xilinx's website they say 3-4 weeks, but from Memec they say more than 8 > weeks. > Does anyone know the truth here.. Austin ? > > Finn > > >Article: 89410
"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.09.14.14.28.25.727255@PleaseDontSpamMEpolybus.com... > > > It sure would be nice if Xilinx could made their software multithreaded... then an Athlon X2 4800+ would really scream. As it is, I'd guess that an Athlon FX-57 (2.8 GHz) will give the fastest PAR performance currently possible. > > > > -Paul > > PAR is multithreaded, use the -m switch. When I used the -m switch a while back on our unix system, I was able to specify a node list for different hosts to run the multipass place & route one more than one machine but I couldn't utilize multiple cores in one host. I also can't use more than one host (or core) for one long place & route job; the -m is specifically for multipass place & route (which, by the way, doesn't have the option to use multiple mapper seeds!).Article: 89411
Thank you Vladislav !!! My objective is to study both FPGA and computer architecture. I have prelimnary knowledge about architecture and I am trying to design simple 4-bit ALU /CPU using VHDL. I think i have virually completed it. As a student I am in process of learing. I want to know more on FPGA, Please suggest me where to start learning and also let me know your recommendation.Article: 89412
On Wed, 14 Sep 2005 11:54:14 +1200, Jim Granville <no.spam@designtools.co.nz> wrote: >they call me frenchy wrote: >> I am thinking of using a lowcost CPLD as a brain to do various logic >> functions in addition to driving 3 separate PWM generators. The PWM >> generators will receive their intputs from a state diagram that is >> cycled through via a pushbutton. Sounds simple. Does anyone object >> to using a very low cost CPLD for this? >> >> Obviously there are many more details involved, like the battery >> powered, low power requirement (Coolrunner II, maybe)...but I just >> wanted to have a general discussion at this point. > > The choice will depend on how many macrocells you actually need, >and the cost relative to alternatives. eg there are many small >uC that can handle 3 PWMs, but a CPLD might give speed or resolution or >protection advantages. > Lowest power 5V parts are Atmel ATF150xASL, and lowest power >1.8V parts are Xilinx Coolrunner and Lattice Mach4000Z series. >-jg Mr. Granville, Thank you very much for your response. Since this is my 1st programmable logic project since college, I really dont know how many macrocells I will need yet. I am in the process of learning VHDL right now and coding the most efficient triple 8-bit PWM imeplementation that I can. It is going well, but it will still be 1-2 days before I can compile it and see how many macrocells are required. (I am using Xilinx's free ISE 7.1 software). When you say there are many small uC that can handle 3 PWMs, can you give me a couple of specific examples so that I can compare their cost/functionality? I admit to you that although I graduated with an EE degree, I have been a musician and running a recording studio for the last several years. I am just now getting back into the EE loop, but I love it and am moving forward quickly. Unfortunately, the fool in me has no idea what you are referring to when you say uC. It probably means microcontroller, but I have never used one and I dont know if they are re-programmable like CPLDs are. The reason that I was looking into the Xilinx Coolrunner II is because I need ultralow power consumption and I found the price on their smallest one (32macrocells) to be $0.85 at quantities of >100k. I hope I can fit it into the smallest one! thx again, frenchyArticle: 89413
Based on your experience, do you think that three 8-bit PWMs could fit inside of a small CPLD (32 or 64 mcarocells)? The other funcionality that I plan to have in there is a state machine that drives the PWM inputs and perhaps some logic that detects the battery voltage level and chooses states accordingly. The more room that I have left over, the more involved I will make the state machine. The Max II that you used seems very similar to the Coolrunner II that I have been looking into. Was your project hi or low quantity? What was the cost of your MaxII at your quantity? thx again! frenchy On Wed, 14 Sep 2005 04:11:55 +0100, "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote: >I've done that 2 times already ! >First was a dual stepper-motor controller (on a EPM7064), >Second it was a GPS frequency control, dac output was a PWM filtered (on a >EPM3064 >and later on a MAXII) > >These are the kind of things that usually don't take a lot of LE's >and fit well inside small CPLD's >But of course I know little about what else you need besides the >PWM... > >lc. > > >"they call me frenchy" <solarfrenchyNO@SPAMhouseofharmonystudios.com> wrote >in message news:takei1lj59t5dd42nmhh85ajjlh4ka05ed@4ax.com... >>I am thinking of using a lowcost CPLD as a brain to do various logic >> functions in addition to driving 3 separate PWM generators. The PWM >> generators will receive their intputs from a state diagram that is >> cycled through via a pushbutton. Sounds simple. Does anyone object >> to using a very low cost CPLD for this? >> >> Obviously there are many more details involved, like the battery >> powered, low power requirement (Coolrunner II, maybe)...but I just >> wanted to have a general discussion at this point. >> >> thx, >> frenchy >Article: 89414
Remco wrote:
> It is just that when they give you the freebie library of components
> why re-invent the wheel, right?
Yes, the components are presented like
jelly beans in a candy store.
I didn't notice the handcuffs, the black box,
and the lawyer until the sugar wore off.
> Of course, their %#$%$%$^@# component doesn't work for crap, so they
> basically steer you down a dark alley for a day or so.
Even if they worked perfectly,
I don't need the complications of their
sim models and libraries. Running
synthesis and simulation using the
same code that I wrote and
understand is a huge advantage.
Many of the components are one-liners anyway.
Even a fifo is just two counters
and a block ram template.
> We had it integrated in a DMA mechanism and when stuff doesn't work,
> you don't immediately assume it is the commercially availbable
> component -- one would hope they test their junk before it is thrown
> over the wall (I guess they didn't).
I don't doubt that some vendor testing is
done, but I don't have the source and I have
to redo it anyway in my own testbench.
> So the first thing you assume is bad is your own code..
If I write my own code, I don't have to assume.
The problem is always in my own code,
but I am free to sim/edit/trace it as
much as I like.
> I guess you get what you pay for.
The only payment required is time and thought.
-- Mike Treseler
Article: 89415I have a bonus question for anyone interested in this topic. Since I am trying to pack 3 8-bit PWMs into as small a space as I can...also since I am new to VHDL coding, I have a question. Which would be best? 1) Implement a single file called "triple_PWM.vhd" that handles all 3 of the separate PWMs with 3 different sets of variables (ie pwm_in1, pwm_in2, pwm_in3, etc) or 2) Implement one generic 8-bit PWM file called "single_PWM.vhd" that is called upon 3 different times for the 3 independent PWM applications? Remember that all 3 PWMs must be functional simultaneously. I will go with #1, but I just wanted to throw this question out there because I thought that it may affect the amount of end logic required. Sorry for the kindergarten question, I am learning. thx, frenchyArticle: 89416
Mike Treseler wrote: > Remco wrote: > > > It is just that when they give you the freebie library of components > > why re-invent the wheel, right? > > Yes, the components are presented like > jelly beans in a candy store. > I didn't notice the handcuffs, the black box, > and the lawyer until the sugar wore off. > > > Of course, their %#$%$%$^@# component doesn't work for crap, so they > > basically steer you down a dark alley for a day or so. > > Even if they worked perfectly, > I don't need the complications of their > sim models and libraries. Running > synthesis and simulation using the > same code that I wrote and > understand is a huge advantage. > > Many of the components are one-liners anyway. > Even a fifo is just two counters > and a block ram template. > > > We had it integrated in a DMA mechanism and when stuff doesn't work, > > you don't immediately assume it is the commercially availbable > > component -- one would hope they test their junk before it is thrown > > over the wall (I guess they didn't). > > I don't doubt that some vendor testing is > done, but I don't have the source and I have > to redo it anyway in my own testbench. > > > So the first thing you assume is bad is your own code.. > > If I write my own code, I don't have to assume. > The problem is always in my own code, > but I am free to sim/edit/trace it as > much as I like. > > > I guess you get what you pay for. > > The only payment required is time and thought. > > -- Mike Treseler All good points - thanks for the reality check. RemcoArticle: 89417
I'm trying to put together a small board design that I can use to verify the functionality of a microcontroller that has a USB controller/tranceiver built into it. On the board I would like to have only the controller and a single FPGA (say Xilinx Virtex-4), with the FPGA hooked to every I/O of the controller I'm trying to test, including the USB signals. From what I can tell the FPGA supports LVDS with specs that seem to be in line with the USB differential signalling requirements. My question is, has anyone connected an FPGA like this directly to a USB client/host chip, without using a tranciever on the board? Thanks EricArticle: 89418
Has anyone had success in using the FSL Control bit? I have intermixed data read/write and control read/write with the FSL and it seems that once the FSL_Error bit is set in the MSR, it remains set even when the following accesses are matched.Article: 89419
What can I say? When I just joined the industry, there was a nice time where the university did not really teach FPGAs, so I had to learn about them in the industry. That is why I really cannot recommend you any book or something like this... Learn as much as you can and use the newsgroup, this is very educative... :) no kidding. Vladislav "biot" <biot.spm@gmail.com> wrote in message news:1126712758.771274.22530@g44g2000cwa.googlegroups.com... > Thank you Vladislav !!! > My objective is to study both FPGA and computer architecture. I have > prelimnary knowledge about architecture and I am trying to design > simple 4-bit ALU /CPU using VHDL. I think i have virually completed it. > As a student I am in process of learing. I want to know more on FPGA, > Please suggest me where to start learning and also let me know your > recommendation. >Article: 89420
Attached is my first cut at an address decoder. While it works I am not sure it's the best method. Also I am not sure why there are four 4:1 muxes in the design. Any help or ideas? Thanks, JTW entity Decoder is Generic ( ASIZE : integer := 32; BSIZE : integer := 12); Port ( clk : in std_logic; rst : in std_logic; address : in std_logic_vector(ASIZE-1 downto 0); reset_stb : out std_logic; reg1_stb : out std_logic; reg2_stb : out std_logic; reg3_stb : out std_logic; valid : out std_logic); end Decoder; architecture Behavioral of Decoder is constant PMC_ADDR : std_logic_vector := X"00008"; constant RESET_ADDR : std_logic_vector := X"000"; constant REG1_ADDR : std_logic_vector := X"004"; constant REG2_ADDR : std_logic_vector := X"008"; constant REG3_ADDR : std_logic_vector := X"00C"; begin process (clk, rst) begin if rst = '1' then valid <= '0'; reset_stb <= '0'; reg1_stb <= '0'; reg2_stb <= '0'; reg3_stb <= '0'; elsif rising_edge(clk) then valid <= '0'; reset_stb <= '0'; reg1_stb <= '0'; reg2_stb <= '0'; reg3_stb <= '0'; if (address(ASIZE-1 downto BSIZE) = PMC_ADDR) then valid <= '1'; if (address(BSIZE-1 downto 0) = RESET_ADDR) then reset_stb <= '1'; end if; if (address(BSIZE-1 downto 0) = REG1_ADDR) then reg1_stb <= '1'; end if; if (address(BSIZE-1 downto 0) = REG2_ADDR) then reg2_stb <= '1'; end if; if (address(BSIZE-1 downto 0) = REG3_ADDR) then reg3_stb <= '1'; end if; end if; end if; end process; end Behavioral;Article: 89421
they call me frenchy wrote: > I have a bonus question for anyone interested in this topic. Since I > am trying to pack 3 8-bit PWMs into as small a space as I can...also > since I am new to VHDL coding, I have a question. Which would be > best? > > 1) Implement a single file called "triple_PWM.vhd" that handles all 3 > of the separate PWMs with 3 different sets of variables (ie pwm_in1, > pwm_in2, pwm_in3, etc) > > or > > 2) Implement one generic 8-bit PWM file called "single_PWM.vhd" that > is called upon 3 different times for the 3 independent PWM > applications? Remember that all 3 PWMs must be functional > simultaneously. > > I will go with #1, but I just wanted to throw this question out there > because I thought that it may affect the amount of end logic required. > Sorry for the kindergarten question, I am learning. > thx, > frenchy Are all three PWM's running at the same frequency? If so you may save a lot of macrocells by combining them. Otherwise, do what's easiest to debug. Just my 2 cents, GaborArticle: 89422
JTW wrote:
> Attached is my first cut at an address decoder. While it works I am not sure it's the best method. Also I am not sure why there are four 4:1 muxes in the design.
>
> Any help or ideas?
Yes. Get a better text editor.
Need to eliminate the tabs and
add a few line feeds.
-- Mike Treseler
Article: 89423they call me frenchy wrote: <snip> > Mr. Granville, > > Thank you very much for your response. Since this is my 1st > programmable logic project since college, I really dont know how many > macrocells I will need yet. I am in the process of learning VHDL > right now and coding the most efficient triple 8-bit PWM > imeplementation that I can. It is going well, but it will still be > 1-2 days before I can compile it and see how many macrocells are > required. (I am using Xilinx's free ISE 7.1 software). > > When you say there are many small uC that can handle 3 PWMs, can you > give me a couple of specific examples so that I can compare their > cost/functionality? I admit to you that although I graduated with an > EE degree, I have been a musician and running a recording studio for > the last several years. I am just now getting back into the EE loop, > but I love it and am moving forward quickly. Unfortunately, the fool > in me has no idea what you are referring to when you say uC. It > probably means microcontroller, but I have never used one and I dont > know if they are re-programmable like CPLDs are. The reason that I > was looking into the Xilinx Coolrunner II is because I need ultralow > power consumption and I found the price on their smallest one > (32macrocells) to be $0.85 at quantities of >100k. I hope I can fit > it into the smallest one! You will struggle to do this in a Coolrunner, as you need to store 3 x 8 bit Values, plus have a 8 bit counter, plus prescaler?, and then 3 PWM pins, so that's bumped you into 64 MC coolrunner. I have packed 3 x PWM into ATF1502ASL, using their logic doubling. See http://www.atmel.com/dyn/resources/prod_documents/DOC2310.PDF For small uC, do a google on Motor Control and Microcontroller. There are many, the most recent press release was this http://www.st.com/stonline/press/news/year2005/p1672d.htm and there are numerous 80C51 variants with PCA, and also the Atmel AT90PWMxx family.... Really depends what ELSE you need in the system... -jgArticle: 89424
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:3ore1nF7di2fU1@individual.net... > JTW wrote: > > Attached is my first cut at an address decoder. While it works I am not sure it's the best method. Also I am not sure why there are four 4:1 muxes in the design. > > > > Any help or ideas? > > Yes. Get a better text editor. > Need to eliminate the tabs and > add a few line feeds. > I agree. If you're gonna code like that, you might as well use Verilog. Cheers, Syms.
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