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Threads Starting May 2009
140184: 09/05/01: MikeWhy: Re: ISE/EDK/SDK 11.1 licensing
140185: 09/05/02: MM: Re: ISE/EDK/SDK 11.1 licensing
140234: 09/05/05: MikeWhy: Re: ISE/EDK/SDK 11.1 licensing
140189: 09/05/02: lsmsc: SysACE and append File
140191: 09/05/02: mstanisz: Spartan3E Starter Kit MISO and Flash pin shared
140192: 09/05/02: glen herrmannsfeldt: Re: Spartan3E Starter Kit MISO and Flash pin shared
140193: 09/05/02: mstanisz: Re: Spartan3E Starter Kit MISO and Flash pin shared
140194: 09/05/02: glen herrmannsfeldt: Re: Spartan3E Starter Kit MISO and Flash pin shared
140200: 09/05/03: mstanisz: Re: Spartan3E Starter Kit MISO and Flash pin shared
140201: 09/05/03: MikeWhy: Re: Spartan3E Starter Kit MISO and Flash pin shared
140231: 09/05/05: mstanisz: Re: Spartan3E Starter Kit MISO and Flash pin shared
140233: 09/05/05: MikeWhy: Re: Spartan3E Starter Kit MISO and Flash pin shared
140247: 09/05/05: mstanisz: Re: Spartan3E Starter Kit MISO and Flash pin shared
140250: 09/05/05: mstanisz: Re: Spartan3E Starter Kit MISO and Flash pin shared
140253: 09/05/06: MikeWhy: Re: Spartan3E Starter Kit MISO and Flash pin shared
140252: 09/05/05: Antti.Lukats@googlemail.com: Re: Spartan3E Starter Kit MISO and Flash pin shared
140202: 09/05/03: ee_ether: High-speed signals crossing a split-ground
140203: 09/05/03: -jg: Re: High-speed signals crossing a split-ground
140207: 09/05/04: Chris Abele: Re: High-speed signals crossing a split-ground
140204: 09/05/03: MM: Re: High-speed signals crossing a split-ground
140206: 09/05/04: glen herrmannsfeldt: Re: High-speed signals crossing a split-ground
140214: 09/05/04: MM: Re: High-speed signals crossing a split-ground
140218: 09/05/04: glen herrmannsfeldt: Re: High-speed signals crossing a split-ground
140219: 09/05/04: MM: Re: High-speed signals crossing a split-ground
140221: 09/05/04: glen herrmannsfeldt: Re: High-speed signals crossing a split-ground
140229: 09/05/04: glen herrmannsfeldt: Re: High-speed signals crossing a split-ground
140241: 09/05/05: MM: Re: High-speed signals crossing a split-ground
140205: 09/05/04: David Brown: Re: High-speed signals crossing a split-ground
140213: 09/05/04: Barry: Re: High-speed signals crossing a split-ground
140227: 09/05/04: CBFalconer: Re: High-speed signals crossing a split-ground
140226: 09/05/04: rickman: Re: High-speed signals crossing a split-ground
140237: 09/05/05: Symon: Re: High-speed signals crossing a split-ground
140239: 09/05/05: gabor: Re: High-speed signals crossing a split-ground
140209: 09/05/04: Selensky: Picoblaze C Compiler
151647: 11/04/30: gfd: Re: Picoblaze C Compiler
140211: 09/05/04: <hassen.karray@gmail.com>: Dynamic partial reconfiguration on Spartan 3 chips
157711: 15/02/10: nick291: Re: Dynamic partial reconfiguration on Spartan 3 chips
157716: 15/02/13: rickman: Re: Dynamic partial reconfiguration on Spartan 3 chips
140212: 09/05/04: de4: FIFO that latches data asynchronic manner
140215: 09/05/04: Andy Peters: Re: FIFO that latches data asynchronic manner
140216: 09/05/04: <peter@xilinx.com>: Re: FIFO that latches data asynchronic manner
140217: 09/05/04: rickman: Re: FIFO that latches data asynchronic manner
140223: 09/05/04: de4: Re: FIFO that latches data asynchronic manner
140224: 09/05/04: MM: Re: FIFO that latches data asynchronic manner
140228: 09/05/04: Muzaffer Kal: Re: FIFO that latches data asynchronic manner
140230: 09/05/04: rickman: Re: FIFO that latches data asynchronic manner
140238: 09/05/05: chewy: Re: FIFO that latches data asynchronic manner
140225: 09/05/04: =?ISO-8859-1?Q?Nicolas_Herv=E9?=: ML402 kernel config : option missing "CFI Flash device PetaLinux
140232: 09/05/05: MikeWhy: Darnit! Broke MXE...
140259: 09/05/06: LittleAlex: Re: Darnit! Broke MXE...
140236: 09/05/05: Nicolas Matringe: ISE & VHDL : how to include time/date
140256: 09/05/06: Jonathan Bromley: Re: ISE & VHDL : how to include time/date
140350: 09/05/10: Nicolas Matringe: Re: ISE & VHDL : how to include time/date
140240: 09/05/05: rickman: Setting top level VHDL generics in XST
140246: 09/05/05: Nicolas Matringe: Re: Setting top level VHDL generics in XST
140257: 09/05/06: rickman: Re: Setting top level VHDL generics in XST
140258: 09/05/06: rickman: Re: Setting top level VHDL generics in XST
140261: 09/05/06: M.Z.: Re: Setting top level VHDL generics in XST
140281: 09/05/07: Mike Treseler: Re: Setting top level VHDL generics in XST
140567: 09/05/18: MikeWhy: Re: Setting top level VHDL generics in XST
140262: 09/05/06: Svenn Are Bjerkem: Re: Setting top level VHDL generics in XST
140278: 09/05/07: rickman: Re: Setting top level VHDL generics in XST
140591: 09/05/19: Svenn Are Bjerkem: Re: Setting top level VHDL generics in XST
140592: 09/05/19: Svenn Are Bjerkem: Re: Setting top level VHDL generics in XST
140716: 09/05/22: rickman: Re: Setting top level VHDL generics in XST
140812: 09/05/26: Andy Peters: Re: Setting top level VHDL generics in XST
140243: 09/05/05: Jan Pech: Re: Setting top level VHDL generics in XST
140245: 09/05/05: gabor: Re: Setting top level VHDL generics in XST
140244: 09/05/05: leevv: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140248: 09/05/05: MM: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140266: 09/05/07: <ales.gorkic@gmail.com>: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140283: 09/05/07: MM: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140249: 09/05/05: mstanisz: Code blocks to realize this in VHDL
140254: 09/05/06: Jonathan Bromley: Re: Code blocks to realize this in VHDL
140251: 09/05/05: MM: MPPR weirdness in ISE8.2.03
141073: 09/06/04: MM: Re: MPPR weirdness in ISE8.2.03 (Solution)
140263: 09/05/06: Svenn Are Bjerkem: Copying data from one BRAM to a Dual-port RAM, problem with
140264: 09/05/06: water: raid controller
140265: 09/05/07: Andreas Ehliar: Re: board with 2 gigabit ethernet connectors?
140267: 09/05/07: recoder: board with 2 gigabit ethernet connectors?
140271: 09/05/07: glen herrmannsfeldt: Re: board with 2 gigabit ethernet connectors?
140272: 09/05/07: Bert_Paris: Re: board with 2 gigabit ethernet connectors?
140273: 09/05/07: Bert_Paris: Re: board with 2 gigabit ethernet connectors?
140277: 09/05/07: Rob Gaddi: Re: board with 2 gigabit ethernet connectors?
140303: 09/05/08: Sebastien @ Sundance: Re: board with 2 gigabit ethernet connectors?
140268: 09/05/07: Nial Stewart: Environmental variables to point at libraries with Modelsim?
140270: 09/05/07: Sean Durkin: Re: Environmental variables to point at libraries with Modelsim?
140275: 09/05/07: Nial Stewart: Re: Environmental variables to point at libraries with Modelsim?
140292: 09/05/07: <pontus.stenstrom@gmail.com>: Re: Environmental variables to point at libraries with Modelsim?
140274: 09/05/07: Bert_Paris: Re: Environmental variables to point at libraries with Modelsim?
140276: 09/05/07: <hepmehepme@comcast.net>: Seeding random number generator
140279: 09/05/07: Tricky: Re: Seeding random number generator
140280: 09/05/07: Tricky: Re: Seeding random number generator
140295: 09/05/07: JimLewis: Re: Seeding random number generator
140282: 09/05/07: rickman: Dual Port RAM Inference
140284: 09/05/07: Peter Alfke: Re: Dual Port RAM Inference
140286: 09/05/07: Jonathan Bromley: Re: Dual Port RAM Inference
140291: 09/05/07: Jonathan Bromley: Re: Dual Port RAM Inference
140306: 09/05/08: Jonathan Bromley: Re: Dual Port RAM Inference
140313: 09/05/08: Mike Treseler: Re: Dual Port RAM Inference
140323: 09/05/08: Mike Treseler: Re: Dual Port RAM Inference
140329: 09/05/09: Jonathan Bromley: Re: Dual Port RAM Inference
140332: 09/05/09: Mike Treseler: Re: Dual Port RAM Inference
140333: 09/05/09: Frank Buss: Re: Dual Port RAM Inference
140353: 09/05/10: Jonathan Bromley: Re: Dual Port RAM Inference
140346: 09/05/10: Sandro: Re: Dual Port RAM Inference
140330: 09/05/09: Peter Alfke: Re: Dual Port RAM Inference
140338: 09/05/09: rickman: Re: Dual Port RAM Inference
140341: 09/05/09: Sandro: Re: Dual Port RAM Inference
140342: 09/05/09: Jacko: Re: Dual Port RAM Inference
140343: 09/05/09: Peter Alfke: Re: Dual Port RAM Inference
140344: 09/05/09: Sandro: Re: Dual Port RAM Inference
140345: 09/05/09: Brian: Re: Dual Port RAM Inference
140371: 09/05/11: rickman: Re: Dual Port RAM Inference
140374: 09/05/11: Sandro: Re: Dual Port RAM Inference
140287: 09/05/07: rickman: Re: Dual Port RAM Inference
140289: 09/05/07: rickman: Re: Dual Port RAM Inference
140296: 09/05/07: Peter Alfke: Re: Dual Port RAM Inference
140299: 09/05/07: rickman: Re: Dual Port RAM Inference
140321: 09/05/08: <peter@xilinx.com>: Re: Dual Port RAM Inference
140324: 09/05/08: rickman: Re: Dual Port RAM Inference
140372: 09/05/11: Mark: Re: Dual Port RAM Inference
140373: 09/05/11: <peter@xilinx.com>: Re: Dual Port RAM Inference
140377: 09/05/11: Mark: Re: Dual Port RAM Inference
140378: 09/05/11: <peter@xilinx.com>: Re: Dual Port RAM Inference
140392: 09/05/12: <peter@xilinx.com>: Re: Dual Port RAM Inference
140404: 09/05/12: rickman: Re: Dual Port RAM Inference
140285: 09/05/07: Jukka Marin: OpenCores CAN/Ethernet cores
140293: 09/05/07: Mike Treseler: Re: OpenCores CAN/Ethernet cores
140294: 09/05/07: Joachim =?ISO-8859-1?Q?F=F6rster?=: Re: OpenCores CAN/Ethernet cores
140387: 09/05/12: Tom: Re: OpenCores CAN/Ethernet cores
140302: 09/05/08: Haris: Re: OpenCores CAN/Ethernet cores
140328: 09/05/09: Richard Pennington: Re: OpenCores CAN/Ethernet cores
140421: 09/05/13: Jukka Marin: Re: OpenCores CAN/Ethernet cores
140288: 09/05/07: Xin Xiao: FPGAs and Cryptography
140290: 09/05/07: glen herrmannsfeldt: Re: FPGAs and Cryptography
140300: 09/05/07: <goouse@twinmail.de>: Re: FPGAs and Cryptography
140305: 09/05/08: Sebastien @ Sundance: Re: FPGAs and Cryptography
140310: 09/05/08: Allan Herriman: Re: FPGAs and Cryptography
140319: 09/05/08: glen herrmannsfeldt: Re: FPGAs and Cryptography
140322: 09/05/08: Allan Herriman: Re: FPGAs and Cryptography
140297: 09/05/07: <prashant.gyawali@gmail.com>: problem during port mapping
140298: 09/05/07: KJ: Re: problem during port mapping
140301: 09/05/08: renupriya: Help required on Ethernet with FPGA
140304: 09/05/08: Symon: Re: Help required on Ethernet with FPGA
140307: 09/05/08: Chico: Quartus II negative bus dimensions in Schematic file
140308: 09/05/08: KJ: Re: Quartus II negative bus dimensions in Schematic file
140315: 09/05/08: Wade Hassler: Re: Quartus II negative bus dimensions in Schematic file
140309: 09/05/08: Chico: Re: Quartus II negative bus dimensions in Schematic file
140317: 09/05/08: LittleAlex: Re: Quartus II negative bus dimensions in Schematic file
140312: 09/05/08: lioncat: Question on using ODDR
140314: 09/05/08: Symon: Re: Question on using ODDR
140316: 09/05/08: lioncat: Re: Question on using ODDR
140320: 09/05/08: Symon: Re: Question on using ODDR
140365: 09/05/11: lioncat: Re: Question on using ODDR
140368: 09/05/11: lioncat: Re: Question on using ODDR
140331: 09/05/09: <prashant.gyawali@gmail.com>: difficulty during processing
140334: 09/05/09: KJ: Re: difficulty during processing
140335: 09/05/09: KJ: Re: difficulty during processing
140363: 09/05/11: hamze60: Re: difficulty during processing
140367: 09/05/11: Allan Herriman: Re: difficulty during processing
140337: 09/05/09: andip1982: Which alternative prog to use for hdl handling ?
140340: 09/05/09: Jonathan Bromley: Re: Which alternative prog to use for hdl handling ?
140354: 09/05/10: MikeWhy: Re: Which alternative prog to use for hdl handling ?
140380: 09/05/12: <'use_real_email'>: Re: Which alternative prog to use for hdl handling ?
140347: 09/05/10: anand: implementing arbitrary combinational functions using block rams
140348: 09/05/10: Jacko: Re: implementing arbitrary combinational functions using block rams
140349: 09/05/10: whygee: Re: implementing arbitrary combinational functions using block rams
140351: 09/05/10: Jeff Cunningham: Re: implementing arbitrary combinational functions using block rams
140352: 09/05/10: Peter Alfke: Re: implementing arbitrary combinational functions using block rams
140355: 09/05/10: anand: Re: implementing arbitrary combinational functions using block rams
140356: 09/05/10: anand: Re: implementing arbitrary combinational functions using block rams
140358: 09/05/10: Samuel Thomas Kerr: Getting started with FPGA
140359: 09/05/10: Haris: Re: Getting started with FPGA
140364: 09/05/11: Sebastien @ Sundance: Re: Getting started with FPGA
140369: 09/05/11: jack.gassett: Re: Getting started with FPGA
140370: 09/05/11: Rich Webb: Re: Getting started with FPGA
140375: 09/05/11: John Adair: Re: Getting started with FPGA
140558: 09/05/17: Tony Burch: Re: Getting started with FPGA
140360: 09/05/11: hamze60: which low cost fpga for space?
140361: 09/05/11: Antti.Lukats@googlemail.com: Re: which low cost fpga for space?
140366: 09/05/11: HT-Lab: Re: which low cost fpga for space?
140401: 09/05/13: Marty Ryba: Re: which low cost fpga for space?
140381: 09/05/12: Sebastien @ Sundance: Re: which low cost fpga for space?
140382: 09/05/12: Antti.Lukats@googlemail.com: Re: which low cost fpga for space?
140384: 09/05/12: HAAH: Re: which low cost fpga for space?
140449: 09/05/13: halong: Re: which low cost fpga for space?
140527: 09/05/15: hamze60: Re: which low cost fpga for space?
140362: 09/05/11: Antti: verilog in TV show (soon)
140510: 09/05/15: Tommy Thorn: Re: verilog in TV show (soon)
140889: 09/05/28: Antti.Lukats@googlemail.com: Re: verilog in TV show (soon)
141004: 09/06/02: Antti.Lukats@googlemail.com: Re: verilog in TV show (soon)
140376: 09/05/11: <bigcaboy@gmail.com>: DSP + FPGA reference design?
140383: 09/05/12: Sebastien @ Sundance: Re: DSP + FPGA reference design?
140396: 09/05/12: <bigcaboy@gmail.com>: Re: DSP + FPGA reference design?
140397: 09/05/12: kenm: Re: DSP + FPGA reference design?
140379: 09/05/11: Mark: Re: Dual Port RAM Inference
140385: 09/05/12: Marteno Rodia: [newbie asking] I don't like Xilinx
140386: 09/05/12: <goouse@twinmail.de>: Re: I don't like Xilinx
140391: 09/05/12: Muzaffer Kal: Re: [newbie asking] I don't like Xilinx
140438: 09/05/13: Muzaffer Kal: Re: I don't like Xilinx
140411: 09/05/13: Marteno Rodia: Re: I don't like Xilinx
140414: 09/05/13: <'use_real_email'>: Re: [newbie asking] I don't like Xilinx
140441: 09/05/13: halong: Re: I don't like Xilinx
140444: 09/05/13: Finn S. Nielsen: Re: [newbie asking] I don't like Xilinx
140815: 09/05/26: Muzaffer Kal: Re: I don't like Xilinx
140506: 09/05/15: Marteno Rodia: Re: I don't like Xilinx
140389: 09/05/12: vcar: Data buffering scheme problem for PCI-E interface
140393: 09/05/12: Rob Gaddi: Re: Data buffering scheme problem for PCI-E interface
140428: 09/05/13: vcar: Re: Data buffering scheme problem for PCI-E interface
140503: 09/05/15: vcar: Re: Data buffering scheme problem for PCI-E interface
140509: 09/05/15: Mives: Re: Data buffering scheme problem for PCI-E interface
140553: 09/05/16: vcar: Re: Data buffering scheme problem for PCI-E interface
140390: 09/05/12: <lolita.tangier@gmail.com>: how i can use the external SRAM of FPGA
140398: 09/05/12: MikeWhy: Re: how i can use the external SRAM of FPGA
140399: 09/05/12: SUMAN: Re: how i can use the external SRAM of FPGA
140405: 09/05/12: Homuncilus: Re: how i can use the external SRAM of FPGA
140407: 09/05/12: <goouse@twinmail.de>: Re: how i can use the external SRAM of FPGA
140415: 09/05/13: Martin Thompson: Re: how i can use the external SRAM of FPGA
140551: 09/05/16: james: Re: how i can use the external SRAM of FPGA
140565: 09/05/18: <lolita.tangier@gmail.com>: Re: how i can use the external SRAM of FPGA
140394: 09/05/12: Dave: XCF32P programming via JTAG
140395: 09/05/12: Antti.Lukats@googlemail.com: Re: XCF32P programming via JTAG
140402: 09/05/12: mng: Re: XCF32P programming via JTAG
140460: 09/05/14: Petter Gustad: Re: XCF32P programming via JTAG
140403: 09/05/12: mng: Re: XCF32P programming via JTAG
140427: 09/05/13: Dave: Re: XCF32P programming via JTAG
140434: 09/05/13: Antti.Lukats@googlemail.com: Re: XCF32P programming via JTAG
140437: 09/05/13: Dave: Re: XCF32P programming via JTAG
140446: 09/05/13: mng: Re: XCF32P programming via JTAG
140461: 09/05/14: Antti.Lukats@googlemail.com: Re: XCF32P programming via JTAG
140400: 09/05/12: Manny: Lockable shared memory co-simulation
140522: 09/05/15: Manny: Re: Lockable shared memory co-simulation
140406: 09/05/12: <aitezaz.abd@gmail.com>: 100 Mbps on 1000/100/10 Mbps PHY
140408: 09/05/12: Sandro: Re: 100 Mbps on 1000/100/10 Mbps PHY
140412: 09/05/13: <aitezaz.abd@gmail.com>: Re: 100 Mbps on 1000/100/10 Mbps PHY
140432: 09/05/13: Rob Gaddi: Re: 100 Mbps on 1000/100/10 Mbps PHY
140456: 09/05/13: <aitezaz.abd@gmail.com>: Re: 100 Mbps on 1000/100/10 Mbps PHY
140409: 09/05/13: Matthias Alles: Achronix' asynchronous FPGAs
140410: 09/05/13: Matthias Alles: Re: Achronix' asynchronous FPGAs
140442: 09/05/13: Jonathan Bromley: Re: Achronix' asynchronous FPGAs
140413: 09/05/13: <aitezaz.abd@gmail.com>: 100 Mbps on NETFPGA http://netfpga.org
140416: 09/05/13: Antti: xilinx 1000-base-X drivers XPS_LL_TEMAC
140417: 09/05/13: Mike Harrison: cheapest FPGA?
140418: 09/05/13: Antti.Lukats@googlemail.com: Re: cheapest FPGA?
140436: 09/05/13: Mike Harrison: Re: cheapest FPGA?
140450: 09/05/13: Mike Harrison: Re: cheapest FPGA?
140499: 09/05/15: Mike Harrison: Re: cheapest FPGA?
140443: 09/05/13: rickman: Re: cheapest FPGA?
140479: 09/05/14: rickman: Re: cheapest FPGA?
140419: 09/05/13: Petter Gustad: Re: cheapest FPGA?
140422: 09/05/13: <smith410@gmail.com>: Re: cheapest FPGA?
140435: 09/05/13: Antti.Lukats@googlemail.com: Re: cheapest FPGA?
140429: 09/05/13: Bert_Paris: Re: cheapest FPGA?
140459: 09/05/14: Petter Gustad: Re: cheapest FPGA?
140467: 09/05/14: Petter Gustad: Re: cheapest FPGA?
140466: 09/05/14: Jacko: Re: cheapest FPGA?
140433: 09/05/13: Rob Gaddi: Re: cheapest FPGA?
140451: 09/05/13: -jg: Re: cheapest FPGA?
140463: 09/05/14: Mike Harrison: Re: cheapest FPGA?
140500: 09/05/15: Mike Harrison: Re: cheapest FPGA?
140490: 09/05/14: -jg: Re: cheapest FPGA?
140487: 09/05/14: Jon Elson: Re: cheapest FPGA?
140420: 09/05/13: Marteno Rodia: Re: I don't like Xilinx
140423: 09/05/13: tpsooraj: How to improve maximum operating frequency of a design using DSP 48E?
140430: 09/05/13: glen herrmannsfeldt: Re: How to improve maximum operating frequency of a design using DSP 48E?
140439: 09/05/13: Muzaffer Kal: Re: How to improve maximum operating frequency of a design using DSP 48E?
140424: 09/05/13: raghu: Connect two bidirectional pins in FPGA
140426: 09/05/13: Dave Pollum: Re: Connect two bidirectional pins in FPGA
140425: 09/05/13: jayantbala: connecting FPGA with PC using ethernet MAC layer only
140431: 09/05/13: glen herrmannsfeldt: Re: connecting FPGA with PC using ethernet MAC layer only
140455: 09/05/14: jayantbala: Re: connecting FPGA with PC using ethernet MAC layer only
140485: 09/05/14: MikeWhy: Re: connecting FPGA with PC using ethernet MAC layer only
140440: 09/05/13: Nico Coesel: Re: connecting FPGA with PC using ethernet MAC layer only
140445: 09/05/13: <liguosu@gmail.com>: how to choose the FPGA/DSP coprocessor system architecture
140447: 09/05/13: <liguosu@gmail.com>: Re: how to choose the FPGA/DSP coprocessor system architecture
140448: 09/05/13: <bigcaboy@gmail.com>: FPGA/DSP system design problem
140482: 09/05/14: rickman: Re: FPGA/DSP system design problem
140498: 09/05/15: bish: Re: FPGA/DSP system design problem
140501: 09/05/15: Sebastien @ Sundance: Re: FPGA/DSP system design problem
140452: 09/05/13: DH: Open source processors
140453: 09/05/13: Antti.Lukats@googlemail.com: Re: Open source processors
140468: 09/05/14: <jon@beniston.com>: Re: Open source processors
140474: 09/05/14: Chris Felton: Re: Open source processors
140516: 09/05/15: <'use_real_email'>: Re: Open source processors
140526: 09/05/15: MikeWhy: Re: Open source processors
141334: 09/06/19: ??: Re: Open source processors
141337: 09/06/19: ÂÀ½¨: Re: Open source processors
141335: 09/06/19: Wu Peng: Re: Open source processors
140581: 09/05/18: DH: Re: Open source processors
140624: 09/05/20: Tommy Thorn: Re: Open source processors
140633: 09/05/20: Jecel: Re: Open source processors
140634: 09/05/20: -jg: Re: Open source processors
140639: 09/05/20: Tommy Thorn: Re: Open source processors
140645: 09/05/20: Antti.Lukats@googlemail.com: Re: Open source processors
140690: 09/05/21: Jecel: Re: Open source processors
140693: 09/05/21: Antti.Lukats@googlemail.com: Re: Open source processors
141053: 09/06/03: David: Re: Open source processors
141076: 09/06/04: OutputLogic: Re: Open source processors
141079: 09/06/04: rickman: Re: Open source processors
141092: 09/06/04: Tommy Thorn: Re: Open source processors
141108: 09/06/05: rickman: Re: Open source processors
141130: 09/06/08: Tommy Thorn: Re: Open source processors
141132: 09/06/08: rickman: Re: Open source processors
141146: 09/06/08: Tommy Thorn: Re: Open source processors
140454: 09/05/14: Andreas Ehliar: Re: XML for LUT+FF netlist representation in (academic) tools
140457: 09/05/13: acd: XML for LUT+FF netlist representation in (academic) tools
140462: 09/05/14: Brian Drummond: Re: XML for LUT+FF netlist representation in (academic) tools
140458: 09/05/14: jayantbala: EDK Enviorment setting problem
140464: 09/05/14: <andrew.newsgroup@gmail.com>: EMACS VHDL mode: how to rescan project so that makefile generates
140475: 09/05/14: Andy Botterill: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140489: 09/05/14: Florian Stock: Re: EMACS VHDL mode: how to rescan project so that makefile generates correctly?
140476: 09/05/14: phil hays: Re: EMACS VHDL mode: how to rescan project so that makefile
140478: 09/05/14: Andy Botterill: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140483: 09/05/14: Mike Treseler: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140820: 09/05/26: Mike Treseler: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140745: 09/05/24: <andrew.newsgroup@gmail.com>: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140790: 09/05/26: <pontus.stenstrom@gmail.com>: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140465: 09/05/14: Sharan: sync vs async reset
140480: 09/05/14: rickman: Re: sync vs async reset
140481: 09/05/14: Mives: Re: sync vs async reset
140491: 09/05/14: Andy: Re: sync vs async reset
140502: 09/05/15: Brian Drummond: Re: sync vs async reset
140580: 09/05/19: Brian Drummond: Re: sync vs async reset
140507: 09/05/15: Sharanbr: Re: sync vs async reset
140574: 09/05/18: Andy Peters: Re: sync vs async reset
140469: 09/05/14: Antti: ISE multiple UCF files from commandline
140470: 09/05/14: Benjamin Krill: Re: ISE multiple UCF files from commandline
140471: 09/05/14: Antti.Lukats@googlemail.com: Re: ISE multiple UCF files from commandline
140472: 09/05/14: renuka: arrays in VHDL
140473: 09/05/14: alfred: Re: arrays in VHDL
140484: 09/05/14: Brad Smallridge: Re: arrays in VHDL
140477: 09/05/14: Poojan Wagh: Survey: What's a good FPGA-related conference?
140508: 09/05/15: Andreas Ehliar: Re: Survey: What's a good FPGA-related conference?
140518: 09/05/15: Mike Treseler: Re: Survey: What's a good FPGA-related conference?
140571: 09/05/18: Jonathan Bromley: Re: Survey: What's a good FPGA-related conference?
140570: 09/05/18: Bryan: Re: Survey: What's a good FPGA-related conference?
140988: 09/06/01: Bryan: Re: Survey: What's a good FPGA-related conference?
140486: 09/05/14: Jon Elson: Xilinx 5V FPGA available from distributors again???
140492: 09/05/14: -jg: Re: Xilinx 5V FPGA available from distributors again???
140517: 09/05/15: Jon Elson: Re: Xilinx 5V FPGA available from distributors again???
140488: 09/05/14: =?UTF-8?B?SGVpbnotSsO8cmdlbg==?= Oertel: SGMII to MII
141062: 09/06/04: veera: Re: SGMII to MII
140493: 09/05/14: <r.fridolin@gmx.de>: XILINX license model restricts longtime availability
140495: 09/05/14: Antti.Lukats@googlemail.com: Re: XILINX license model restricts longtime availability
140496: 09/05/15: Kim Enkovaara: Re: XILINX license model restricts longtime availability
140523: 09/05/15: John McCaskill: Re: XILINX license model restricts longtime availability
140579: 09/05/18: glen herrmannsfeldt: Re: XILINX license model restricts longtime availability
140583: 09/05/19: Kim Enkovaara: Re: XILINX license model restricts longtime availability
140603: 09/05/20: Kim Enkovaara: Re: XILINX license model restricts longtime availability
140604: 09/05/20: Martin Thompson: Re: XILINX license model restricts longtime availability
144755: 09/12/30: salman: Re: XILINX license model restricts longtime availability
140573: 09/05/18: Andy Peters: Re: XILINX license model restricts longtime availability
140575: 09/05/18: Antti.Lukats@googlemail.com: Re: XILINX license model restricts longtime availability
140578: 09/05/18: -jg: Re: XILINX license model restricts longtime availability
140587: 09/05/19: LittleAlex: Re: XILINX license model restricts longtime availability
140588: 09/05/19: colin_toogood@yahoo.com: Re: XILINX license model restricts longtime availability
140494: 09/05/14: Antti: actel block RAM initial value
140504: 09/05/15: whygee: Re: actel block RAM initial value
140505: 09/05/15: maxascent: Virtex 5 clocking
140512: 09/05/15: Nathan Bialke: Re: Virtex 5 clocking
140513: 09/05/15: maxascent: Re: Virtex 5 clocking
140524: 09/05/16: Symon: Re: Virtex 5 clocking
140535: 09/05/16: maxascent: Re: Virtex 5 clocking
140548: 09/05/16: Muzaffer Kal: Re: Virtex 5 clocking
140550: 09/05/17: Symon: Re: Virtex 5 clocking
140552: 09/05/16: Muzaffer Kal: Re: Virtex 5 clocking
140515: 09/05/15: Nathan Bialke: Re: Virtex 5 clocking
140514: 09/05/15: gert1999: Coolrunner II: what's wrong up here ?
140520: 09/05/15: MikeWhy: Re: Coolrunner II: what's wrong up here ?
140521: 09/05/15: MikeWhy: Re: Coolrunner II: what's wrong up here ?
140543: 09/05/16: MikeWhy: Re: Coolrunner II: what's wrong up here ?
140547: 09/05/16: MikeWhy: Re: Coolrunner II: what's wrong up here ?
140538: 09/05/16: gert1999: Re: Coolrunner II: what's wrong up here ?
140546: 09/05/16: gert1999: Re: Coolrunner II: what's wrong up here ?
140840: 09/05/27: gert1999: Re: Coolrunner II: what's wrong up here ?
140846: 09/05/27: rickman: Re: Coolrunner II: what's wrong up here ?
140867: 09/05/27: -jg: Re: Coolrunner II: what's wrong up here ?
140909: 09/05/29: gert1999: Re: Coolrunner II: what's wrong up here ?
140931: 09/05/29: -jg: Re: Coolrunner II: what's wrong up here ?
141103: 09/06/05: gert1999: Re: Coolrunner II: what's wrong up here ?
140519: 09/05/15: <'use_real_email'>: Info on the JBC file
140528: 09/05/15: <'use_real_email'>: sdio lab testing help needed
140532: 09/05/15: Antti.Lukats@googlemail.com: Re: sdio lab testing help needed
140544: 09/05/16: Antti.Lukats@googlemail.com: Re: sdio lab testing help needed
140545: 09/05/16: <'use_real_email'>: Re: sdio lab testing help needed
140530: 09/05/15: radarman: Cheap Ethernet PHY boards?
140534: 09/05/16: Sebastien @ Sundance: Re: Cheap Ethernet PHY boards?
140536: 09/05/16: John Adair: Re: Cheap Ethernet PHY boards?
140537: 09/05/16: glen herrmannsfeldt: Re: Cheap Ethernet PHY boards?
140641: 09/05/20: radarman: Re: Cheap Ethernet PHY boards?
140531: 09/05/15: <'use_real_email'>: Net-List Conversion
140539: 09/05/16: wzab: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140540: 09/05/16: Antti.Lukats@googlemail.com: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140542: 09/05/16: Antti.Lukats@googlemail.com: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140541: 09/05/16: wzab: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140559: 09/05/17: wzab: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140560: 09/05/17: wzab: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140554: 09/05/16: <wenweizha@gmail.com>: Bug in Xilinx's hwicap_v1_01_a/src/xhwicap_srp.c
140555: 09/05/16: intermilan: Problem with ML410 board ethernet
140557: 09/05/17: Antti: soft processor report
140568: 09/05/18: rickman: Re: soft processor report
140562: 09/05/17: Jake7: Online tool that generates parallel CRC and Scrambler
140614: 09/05/20: luudee: Re: Online tool that generates parallel CRC and Scrambler
140629: 09/05/20: Mark: Re: Online tool that generates parallel CRC and Scrambler
140635: 09/05/21: glen herrmannsfeldt: Re: Online tool that generates parallel CRC and Scrambler
140907: 09/05/29: glen herrmannsfeldt: Re: Online tool that generates parallel CRC and Scrambler
140683: 09/05/21: Mike Treseler: Re: Online tool that generates parallel CRC and Scrambler
140786: 09/05/26: Andreas Ehliar: Re: Online tool that generates parallel CRC and Scrambler
140814: 09/05/26: Mike Treseler: Re: Online tool that generates parallel CRC and Scrambler
140829: 09/05/27: Petter Gustad: Re: Online tool that generates parallel CRC and Scrambler
140859: 09/05/27: Jan Decaluwe: Re: Online tool that generates parallel CRC and Scrambler
140830: 09/05/27: Jan Decaluwe: Re: Online tool that generates parallel CRC and Scrambler
140828: 09/05/27: Petter Gustad: Re: Online tool that generates parallel CRC and Scrambler
140851: 09/05/27: Mark: Re: Online tool that generates parallel CRC and Scrambler
140905: 09/05/28: Jake7: Re: Online tool that generates parallel CRC and Scrambler
140906: 09/05/28: Jake7: Re: Online tool that generates parallel CRC and Scrambler
140922: 09/05/29: OutputLogic: Re: Online tool that generates parallel CRC and Scrambler
140563: 09/05/17: <naveen.thohare@gmail.com>: Doubts in using memory of verilog
140566: 09/05/18: Jonathan Bromley: Re: Doubts in using memory of verilog
140569: 09/05/18: Fredxx: OT: Google vs Yahoo
140572: 09/05/18: Antti: SD card bootstrap code in 55 instructions
140577: 09/05/18: -jg: Re: SD card bootstrap code in 55 instructions
140584: 09/05/19: Antti.Lukats@googlemail.com: Re: SD card bootstrap code in 55 instructions
140576: 09/05/18: VIPS: i2c Start and stop detection
140582: 09/05/18: <'use_real_email'>: Re: i2c Start and stop detection
140594: 09/05/19: Brad Smallridge: Re: i2c Start and stop detection
141402: 09/06/23: Vikas: Re: i2c Start and stop detection
141403: 09/06/23: Vikas: Re: i2c Start and stop detection
141421: 09/06/24: Vikas: Re: i2c Start and stop detection
140622: 09/05/20: VIPS: Re: i2c Start and stop detection
140628: 09/05/20: gabor: Re: i2c Start and stop detection
141404: 09/06/23: gabor: Re: i2c Start and stop detection
141405: 09/06/23: gabor: Re: i2c Start and stop detection
141406: 09/06/23: Andrew Holme: Re: i2c Start and stop detection
140585: 09/05/19: <philippe.faes@gmail.com>: Sigasi Public Beta: future of VHDL design
140593: 09/05/19: Aiken: Re: Sigasi Public Beta: future of VHDL design
140596: 09/05/19: Mike Treseler: Re: Sigasi Public Beta: future of VHDL design
140597: 09/05/19: Matthew Hicks: Re: Sigasi Public Beta: future of VHDL design
140619: 09/05/20: Mike Treseler: Re: Sigasi Public Beta: future of VHDL design
140595: 09/05/19: <philippe.faes@gmail.com>: Re: Sigasi Public Beta: future of VHDL design
140649: 09/05/21: colin_toogood@yahoo.com: Re: Sigasi Public Beta: future of VHDL design
140655: 09/05/21: Jan Decaluwe: Re: Sigasi Public Beta: future of VHDL design
140658: 09/05/21: Nial Stewart: Re: Sigasi Public Beta: future of VHDL design
140586: 09/05/19: =?windows-1252?Q?GaLaKtIkUs=99?=: JAM scripts and Altera's USB-Blaster cable
140589: 09/05/19: Naveen: Prob with verilog memory
140601: 09/05/19: gabor: Re: Prob with verilog memory
140590: 09/05/19: hvo: How to load xilinx mfs file into spi flash?
140598: 09/05/19: WZab: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
140739: 09/05/23: wzab: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
140757: 09/05/25: <jetmarc@hotmail.com>: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
140599: 09/05/20: Andrew Holme: DCM Jitter
140600: 09/05/19: Rob Gaddi: Re: DCM Jitter
140602: 09/05/19: Peter Alfke: Re: DCM Jitter
140605: 09/05/20: Andrew Holme: Re: DCM Jitter
140615: 09/05/20: gabor: Re: DCM Jitter
140618: 09/05/20: Symon: Re: DCM Jitter
140686: 09/05/21: Andrew Holme: Re: DCM Jitter
140701: 09/05/22: Symon: Re: DCM Jitter
140742: 09/05/23: Symon: Re: DCM Jitter
140672: 09/05/21: austin: Re: DCM Jitter
140700: 09/05/22: gabor: Re: DCM Jitter
140713: 09/05/22: Sandro: Re: DCM Jitter
140606: 09/05/20: <barme2i@gmail.com>: Port assignment question
140608: 09/05/20: Sean Durkin: Re: Port assignment question
140617: 09/05/20: Jonathan Bromley: Re: Port assignment question
140616: 09/05/20: <hassen.karray@gmail.com>: Re: Port assignment question
140631: 09/05/20: Nicolas Matringe: Re: Port assignment question
140738: 09/05/23: KJ: Re: Port assignment question
140664: 09/05/21: <hassen.karray@gmail.com>: Re: Port assignment question
140666: 09/05/21: Andy: Re: Port assignment question
140736: 09/05/23: <hassen.karray@gmail.com>: Re: Port assignment question
140737: 09/05/23: <hassen.karray@gmail.com>: Re: Port assignment question
140741: 09/05/23: <hassen.karray@gmail.com>: Re: Port assignment question
140607: 09/05/20: <sbattazz@yahoo.co.jp>: Actel Low Cost Programming Stick (IGLOO kits)
140609: 09/05/20: Antti.Lukats@googlemail.com: Re: Actel Low Cost Programming Stick (IGLOO kits)
140611: 09/05/20: <sbattazz@yahoo.co.jp>: Re: Actel Low Cost Programming Stick (IGLOO kits)
140612: 09/05/20: Antti.Lukats@googlemail.com: Re: Actel Low Cost Programming Stick (IGLOO kits)
140610: 09/05/20: HT-Lab: ISIM and CONV_INTEGER warnings
140621: 09/05/20: MikeWhy: Re: ISIM and CONV_INTEGER warnings
140626: 09/05/20: HT-Lab: Re: ISIM and CONV_INTEGER warnings
140627: 09/05/20: MikeWhy: Re: ISIM and CONV_INTEGER warnings
140647: 09/05/21: HT-Lab: Re: ISIM and CONV_INTEGER warnings
140659: 09/05/21: MikeWhy: Re: ISIM and CONV_INTEGER warnings
140661: 09/05/21: Brian Drummond: Re: ISIM and CONV_INTEGER warnings
140694: 09/05/22: HT-Lab: Re: ISIM and CONV_INTEGER warnings
140696: 09/05/22: Fredxx: Re: ISIM and CONV_INTEGER warnings
140613: 09/05/20: luudee: Muli-Cycle Path Constrains in RTL
140620: 09/05/20: Mike Treseler: Re: Muli-Cycle Path Constrains in RTL
140685: 09/05/21: Mike Treseler: Re: Muli-Cycle Path Constrains in RTL
140717: 09/05/22: Muzaffer Kal: Re: Muli-Cycle Path Constrains in RTL
140743: 09/05/23: Mike Treseler: Re: Muli-Cycle Path Constrains in RTL
140746: 09/05/25: Kim Enkovaara: Re: Muli-Cycle Path Constrains in RTL
140670: 09/05/21: Andy: Re: Muli-Cycle Path Constrains in RTL
140715: 09/05/22: luudee: Re: Muli-Cycle Path Constrains in RTL
140753: 09/05/25: Andy: Re: Muli-Cycle Path Constrains in RTL
140623: 09/05/20: CMOS: please recommend a soft processor for small image processing tasks
140625: 09/05/20: Tommy Thorn: Re: please recommend a soft processor for small image processing
140697: 09/05/22: Martin Thompson: Re: please recommend a soft processor for small image processing tasks
140642: 09/05/20: CMOS: Re: please recommend a soft processor for small image processing
140643: 09/05/20: Antti.Lukats@googlemail.com: Re: please recommend a soft processor for small image processing
140651: 09/05/21: CMOS: Re: please recommend a soft processor for small image processing
140656: 09/05/21: Antti.Lukats@googlemail.com: Re: please recommend a soft processor for small image processing
140660: 09/05/21: <ales.gorkic@gmail.com>: Re: please recommend a soft processor for small image processing
140676: 09/05/21: CMOS: Re: please recommend a soft processor for small image processing
140677: 09/05/21: Antti.Lukats@googlemail.com: Re: please recommend a soft processor for small image processing
140678: 09/05/21: Rob Gaddi: Re: please recommend a soft processor for small image processing
140679: 09/05/21: CMOS: Re: please recommend a soft processor for small image processing
140680: 09/05/21: Rob Gaddi: Re: please recommend a soft processor for small image processing
140735: 09/05/23: bish: Re: please recommend a soft processor for small image processing
140630: 09/05/20: Erik Anderson: Synthesis of Xilinx's PLB DDR Controller
140636: 09/05/20: Weng Tianxiang: Are all these claims in VHDL correct?
140648: 09/05/21: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140652: 09/05/21: Fredxx: Re: Are all these claims in VHDL correct?
140653: 09/05/21: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140654: 09/05/21: Fredxx: Re: Are all these claims in VHDL correct?
140662: 09/05/21: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140682: 09/05/21: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140698: 09/05/22: Martin Thompson: Re: Are all these claims in VHDL correct?
140707: 09/05/22: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140704: 09/05/22: Jonathan Bromley: Re: Are all these claims in VHDL correct?
140665: 09/05/21: Andy: Re: Are all these claims in VHDL correct?
140675: 09/05/21: Weng Tianxiang: Re: Are all these claims in VHDL correct?
140703: 09/05/22: Weng Tianxiang: Re: Are all these claims in VHDL correct?
140740: 09/05/23: Weng Tianxiang: Re: Are all these claims in VHDL correct?
140744: 09/05/24: Andy: Re: Are all these claims in VHDL correct?
140637: 09/05/20: <andrew.newsgroup@gmail.com>: Can we expect ISE Gui and makefile to produce identical bit files?
140640: 09/05/21: Matthew Hicks: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140801: 09/05/26: MikeWhy: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140817: 09/05/26: MikeWhy: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140646: 09/05/20: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140663: 09/05/21: Brian Drummond: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140668: 09/05/21: phil hays: Re: Can we expect ISE Gui and makefile to produce identical bit
140687: 09/05/21: Mike Treseler: Re: Can we expect ISE Gui and makefile to produce identical bit
140712: 09/05/22: LittleAlex: Re: Can we expect ISE Gui and makefile to produce identical bit
140771: 09/05/25: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140772: 09/05/25: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140773: 09/05/25: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140816: 09/05/26: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140819: 09/05/26: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140864: 09/05/27: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
140897: 09/05/29: phil hays: Re: Can we expect ISE Gui and makefile to produce identical bit
140898: 09/05/28: David Antliff: Re: Can we expect ISE Gui and makefile to produce identical bit
141617: 09/06/30: OutputLogic: Re: Can we expect ISE Gui and makefile to produce identical bit
140650: 09/05/21: <secureasm@gmail.com>: No integer interpolation ...
140669: 09/05/21: MM: Re: No integer interpolation ...
140673: 09/05/21: MM: Re: No integer interpolation ...
140705: 09/05/22: MM: Re: No integer interpolation ...
140722: 09/05/22: Kappasm: Re: No integer interpolation ...
140731: 09/05/22: MM: Re: No integer interpolation ...
140733: 09/05/23: Kappasm: Re: No integer interpolation ...
140671: 09/05/21: <secureasm@gmail.com>: Re: No integer interpolation ...
140699: 09/05/22: <secureasm@gmail.com>: Re: No integer interpolation ...
140657: 09/05/21: <aitezaz.abd@gmail.com>: 90 degree phase shifted clock for RGMII
140667: 09/05/21: jacko: Nibz VHDL Processor (Version G-spot)
140674: 09/05/21: Antti.Lukats@googlemail.com: Re: Nibz VHDL Processor (Version G-spot)
140695: 09/05/22: HT-Lab: Re: Nibz VHDL Processor (Version G-spot)
140684: 09/05/21: Jacko: Re: Nibz VHDL Processor (Version G-spot)
140688: 09/05/21: Jacko: Re: Nibz VHDL Processor (Version G-spot)
140689: 09/05/21: Jacko: Re: Nibz VHDL Processor (Version G-spot)
140692: 09/05/21: Antti.Lukats@googlemail.com: Re: Nibz VHDL Processor (Version G-spot)
140708: 09/05/22: jacko: Re: Nibz VHDL Processor (Version G-spot)
140726: 09/05/22: Jacko: Re: Nibz VHDL Processor (Version G-spot)
140681: 09/05/21: <francescopoderico@googlemail.com>: JTAG problem
140691: 09/05/21: Devlin: FC vore support problem
140702: 09/05/22: Amal: SPAM?
140710: 09/05/22: Rob Gaddi: Re: SPAM?
140718: 09/05/22: Dave Farrance: Re: SPAM?
140719: 09/05/22: BobW: Re: SPAM?
140727: 09/05/22: Dave Farrance: Re: SPAM?
140711: 09/05/22: <MadHatter7@myself.com>: Re: SPAM?
140734: 09/05/23: Robert Miles: Re: SPAM?
140714: 09/05/22: James Harris: Re: SPAM?
140706: 09/05/22: Neil Steiner: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140709: 09/05/22: evilkidder@googlemail.com: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140720: 09/05/22: Neil Steiner: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140732: 09/05/22: Neil Steiner: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140725: 09/05/22: evilkidder@googlemail.com: Re: Unable to run 'xdl -ncd2xdl' on RHEL 5.3 in ISE 10.1
140721: 09/05/22: jleslie48: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140723: 09/05/22: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140728: 09/05/22: Muzaffer Kal: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred .... Warning. Should I care?
140810: 09/05/26: Muzaffer Kal: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred .... Warning. Should I care?
140724: 09/05/22: doug: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140730: 09/05/22: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140799: 09/05/26: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140809: 09/05/26: Andy Peters: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140813: 09/05/26: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140852: 09/05/27: Andy Peters: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140862: 09/05/27: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140868: 09/05/27: rickman: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140884: 09/05/28: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140891: 09/05/28: Andy Peters: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140894: 09/05/28: jleslie48: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred ....
140729: 09/05/22: jacko: 512*256 resolution on VGA (generic code available)
140747: 09/05/24: Antti: VHDL synthesis difference bwetween tools
140936: 09/05/30: Jonathan Bromley: Re: VHDL synthesis difference bwetween tools
140937: 09/05/30: Antti.Lukats@googlemail.com: Re: VHDL synthesis difference bwetween tools
141029: 09/06/02: Pauli =?iso-8859-1?Q?Per=E4l=E4?=: Re: VHDL synthesis difference bwetween tools
141030: 09/06/02: Antti.Lukats@googlemail.com: Re: VHDL synthesis difference bwetween tools
140748: 09/05/25: <yuchiwai@gmail.com>: Architecture of FPGA
140749: 09/05/25: Nobby Anderson: Re: Architecture of FPGA
140755: 09/05/25: MM: Re: Architecture of FPGA
140770: 09/05/25: Symon: Re: Architecture of FPGA
140798: 09/05/26: MM: Re: Architecture of FPGA
140774: 09/05/25: Nobby Anderson: Re: Architecture of FPGA
140802: 09/05/26: Nobby Anderson: Re: Architecture of FPGA
140805: 09/05/26: Weng Tianxiang: Re: Architecture of FPGA
140833: 09/05/27: Symon: Re: Architecture of FPGA
140834: 09/05/27: Florian Stock: Re: Architecture of FPGA
140808: 09/05/26: halong: Re: Architecture of FPGA
140826: 09/05/26: rickman: Re: Architecture of FPGA
140750: 09/05/25: <sbattazz@yahoo.co.jp>: Adders with multiple inputs?
140751: 09/05/25: Andrew Holme: Re: Adders with multiple inputs?
140752: 09/05/25: <sbattazz@yahoo.co.jp>: Re: Adders with multiple inputs?
140754: 09/05/25: Andy: Re: Adders with multiple inputs?
140758: 09/05/25: Peter Alfke: Re: Adders with multiple inputs?
140764: 09/05/25: Weng Tianxiang: Re: Adders with multiple inputs?
140778: 09/05/25: <sbattazz@yahoo.co.jp>: Re: Adders with multiple inputs?
140779: 09/05/25: <sbattazz@yahoo.co.jp>: Re: Adders with multiple inputs?
140780: 09/05/25: Peter Alfke: Re: Adders with multiple inputs?
140781: 09/05/25: <sbattazz@yahoo.co.jp>: Re: Adders with multiple inputs?
140794: 09/05/26: Kolja: Re: Adders with multiple inputs?
140800: 09/05/26: Weng Tianxiang: Re: Adders with multiple inputs?
140822: 09/05/26: <sbattazz@yahoo.co.jp>: Re: Adders with multiple inputs?
140756: 09/05/25: <pantgom@gmail.com>: Doubt about a Microblaze Based Multiprocessor SoC
140759: 09/05/25: <ljung@codetronix.com>: Re: Doubt about a Microblaze Based Multiprocessor SoC
140787: 09/05/26: Andreas Ehliar: Re: Doubt about a Microblaze Based Multiprocessor SoC
141192: 09/06/10: naim32: Re: Doubt about a Microblaze Based Multiprocessor SoC
141206: 09/06/11: naim32: Re: Doubt about a Microblaze Based Multiprocessor SoC
141223: 09/06/11: naim32: Re: Doubt about a Microblaze Based Multiprocessor SoC
141230: 09/06/11: naim32: Re: Doubt about a Microblaze Based Multiprocessor SoC
140767: 09/05/25: Pablo: Re: Doubt about a Microblaze Based Multiprocessor SoC
140782: 09/05/25: <ljung@codetronix.com>: Re: Doubt about a Microblaze Based Multiprocessor SoC
140784: 09/05/26: Pablo: Re: Doubt about a Microblaze Based Multiprocessor SoC
140811: 09/05/26: Pablo: Re: Doubt about a Microblaze Based Multiprocessor SoC
141195: 09/06/10: pbljung: Re: Doubt about a Microblaze Based Multiprocessor SoC
141214: 09/06/11: pbljung: Re: Doubt about a Microblaze Based Multiprocessor SoC
141226: 09/06/11: pbljung: Re: Doubt about a Microblaze Based Multiprocessor SoC
140760: 09/05/25: Antti: V5 GTX clocking
140761: 09/05/25: Antti.Lukats@googlemail.com: Re: V5 GTX clocking
140762: 09/05/25: Frank Buss: passing data from fast to slow time domain
140763: 09/05/25: Nathan Bialke: Re: passing data from fast to slow time domain
140765: 09/05/25: Frank Buss: Re: passing data from fast to slow time domain
140825: 09/05/27: Frank Buss: Re: passing data from fast to slow time domain
140766: 09/05/25: Weng Tianxiang: When is it to generate transparent latch or usual combinational
140768: 09/05/25: Dave: Re: When is it to generate transparent latch or usual combinational
140788: 09/05/26: Brian Drummond: Re: When is it to generate transparent latch or usual combinational logic?
140807: 09/05/26: Mike Treseler: Re: When is it to generate transparent latch or usual combinational
140769: 09/05/25: Andy: Re: When is it to generate transparent latch or usual combinational
140777: 09/05/25: Weng Tianxiang: Re: When is it to generate transparent latch or usual combinational
140793: 09/05/26: Andy: Re: When is it to generate transparent latch or usual combinational
140803: 09/05/26: Weng Tianxiang: Re: When is it to generate transparent latch or usual combinational
140818: 09/05/26: Andy: Re: When is it to generate transparent latch or usual combinational
140821: 09/05/26: Weng Tianxiang: Re: When is it to generate transparent latch or usual combinational
140841: 09/05/27: Andy: Re: When is it to generate transparent latch or usual combinational
140899: 09/05/28: Jacko: Re: When is it to generate transparent latch or usual combinational
140912: 09/05/29: Andy: Re: When is it to generate transparent latch or usual combinational
140775: 09/05/25: MikeWhy: Multple architectures in ISE top level module?
140776: 09/05/25: MikeWhy: Re: Multple architectures in ISE top level module?
140789: 09/05/26: Brian Drummond: Re: Multple architectures in ISE top level module?
140795: 09/05/26: MikeWhy: Re: Multple architectures in ISE top level module?
145477: 10/02/11: tamoruso: Re: Multple architectures in ISE top level module?
145479: 10/02/11: RCIngham: Re: Multple architectures in ISE top level module?
140783: 09/05/26: luudee: 11.1 & USB cable drivers
140785: 09/05/26: Uwe Bonnes: Re: 11.1 & USB cable drivers
140792: 09/05/26: Uwe Bonnes: Re: 11.1 & USB cable drivers
140797: 09/05/26: Uwe Bonnes: Re: 11.1 & USB cable drivers
141105: 09/06/05: Uwe Bonnes: Re: 11.1 & USB cable drivers
141420: 09/06/23: Chet: Re: 11.1 & USB cable drivers
141423: 09/06/24: Uwe Bonnes: Re: 11.1 & USB cable drivers
141485: 09/06/25: Chet: Re: 11.1 & USB cable drivers
140791: 09/05/26: luudee: Re: 11.1 & USB cable drivers
140796: 09/05/26: Sandro: Re: 11.1 & USB cable drivers
140804: 09/05/26: Antti.Lukats@googlemail.com: Re: 11.1 & USB cable drivers
140954: 09/05/31: Charles: Re: 11.1 & USB cable drivers
140955: 09/05/31: Charles: Re: 11.1 & USB cable drivers
140806: 09/05/26: <your.box2@googlemail.com>: URGENT help with a CPLD and LCD display chip SED1278F
140827: 09/05/26: <goouse@twinmail.de>: Re: URGENT help with a CPLD and LCD display chip SED1278F
140845: 09/05/27: MM: Re: URGENT help with a CPLD and LCD display chip SED1278F
140823: 09/05/26: Pete Fraser: Core 2 Duo E8500 vs. Core i7 920?
140824: 09/05/26: Muzaffer Kal: Re: Core 2 Duo E8500 vs. Core i7 920?
140831: 09/05/27: <lolita.tangier@gmail.com>: how i can to send a sequence of bytes to the FPGA ?
140832: 09/05/27: Antti.Lukats@googlemail.com: Re: how i can to send a sequence of bytes to the FPGA ?
140835: 09/05/27: HT-Lab: Re: how i can to send a sequence of bytes to the FPGA ?
140838: 09/05/27: Symon: Re: how i can to send a sequence of bytes to the FPGA ?
140837: 09/05/27: <lolita.tangier@gmail.com>: Re: how i can to send a sequence of bytes to the FPGA ?
140848: 09/05/27: Antti.Lukats@googlemail.com: Re: how i can to send a sequence of bytes to the FPGA ?
140850: 09/05/27: Mike Treseler: Re: how i can to send a sequence of bytes to the FPGA ?
140836: 09/05/27: shantesh: Signal encoding for a user-defined type
140839: 09/05/27: Symon: Re: Signal encoding for a user-defined type
140842: 09/05/27: Andy: Re: Signal encoding for a user-defined type
140843: 09/05/27: Andy: Re: Signal encoding for a user-defined type
140844: 09/05/27: rickman: Re: Signal encoding for a user-defined type
140847: 09/05/27: jleslie48: phase locking a slow (2Mhz) signal.
140855: 09/05/27: MM: Re: phase locking a slow (2Mhz) signal.
140856: 09/05/27: Muzaffer Kal: Re: phase locking a slow (2Mhz) signal.
140888: 09/05/28: MM: Re: phase locking a slow (2Mhz) signal.
140892: 09/05/28: doug: Re: phase locking a slow (2Mhz) signal.
140908: 09/05/29: Fredxx: Re: phase locking a slow (2Mhz) signal.
140913: 09/05/29: doug: Re: phase locking a slow (2Mhz) signal.
140917: 09/05/29: doug: Re: phase locking a slow (2Mhz) signal.
140959: 09/05/31: doug: Re: phase locking a slow (2Mhz) signal.
140914: 09/05/29: doug: Re: phase locking a slow (2Mhz) signal.
141010: 09/06/02: Mike Treseler: Re: phase locking a slow (2Mhz) signal.
140861: 09/05/27: jleslie48: Re: phase locking a slow (2Mhz) signal.
140866: 09/05/27: rickman: Re: phase locking a slow (2Mhz) signal.
140872: 09/05/27: Peter Alfke: Re: phase locking a slow (2Mhz) signal.
140887: 09/05/28: jleslie48: Re: phase locking a slow (2Mhz) signal.
140890: 09/05/28: jleslie48: Re: phase locking a slow (2Mhz) signal.
140895: 09/05/28: gabor: Re: phase locking a slow (2Mhz) signal.
140902: 09/05/28: Antti.Lukats@googlemail.com: Re: phase locking a slow (2Mhz) signal.
140910: 09/05/29: jleslie48: Re: phase locking a slow (2Mhz) signal.
140916: 09/05/29: jleslie48: Re: phase locking a slow (2Mhz) signal.
140920: 09/05/29: jleslie48: Re: phase locking a slow (2Mhz) signal.
140925: 09/05/29: rickman: Re: phase locking a slow (2Mhz) signal.
140956: 09/05/31: jleslie48: Re: phase locking a slow (2Mhz) signal.
140957: 09/05/31: Peter Alfke: Re: phase locking a slow (2Mhz) signal.
140964: 09/06/01: Antti.Lukats@googlemail.com: Re: phase locking a slow (2Mhz) signal.
140965: 09/06/01: rickman: Re: phase locking a slow (2Mhz) signal.
140982: 09/06/01: jleslie48: Re: phase locking a slow (2Mhz) signal.
140985: 09/06/01: <peter@xilinx.com>: Re: phase locking a slow (2Mhz) signal.
140990: 09/06/01: rickman: Re: phase locking a slow (2Mhz) signal.
140992: 09/06/01: -jg: Re: phase locking a slow (2Mhz) signal.
140994: 09/06/01: Peter Alfke: Re: phase locking a slow (2Mhz) signal.
140995: 09/06/01: rickman: Re: phase locking a slow (2Mhz) signal.
140996: 09/06/01: rickman: Re: phase locking a slow (2Mhz) signal.
141016: 09/06/02: rickman: Re: phase locking a slow (2Mhz) signal.
141018: 09/06/02: jleslie48: Re: phase locking a slow (2Mhz) signal.
140849: 09/05/27: jacko: Nibz (Version P)
140863: 09/05/27: Jacko: Re: Nibz (Version P)
140865: 09/05/27: Jacko: Re: Nibz (Version P)
140875: 09/05/27: Antti.Lukats@googlemail.com: Re: Nibz (Version P)
140853: 09/05/27: PrAsHaNtH@IIT: Reading from and writing to a text file in verilog hdl
140881: 09/05/28: gabor: Re: Reading from and writing to a text file in verilog hdl
140854: 09/05/27: Nad: Cyclone3 and AT45DB serial flash
140879: 09/05/28: Bert_Paris: Re: Cyclone3 and AT45DB serial flash
140950: 09/05/30: radarman: Re: Cyclone3 and AT45DB serial flash
140857: 09/05/27: PrAsHaNtH@IIT: Error in Verilog Code
140860: 09/05/27: john: Re: Error in Verilog Code
140858: 09/05/27: <wzab@ise.pw.edu.pl>: Python code accessing the Altera Virtual JTAG instances (via urJTAG)
140869: 09/05/27: Gerry_MAN: Old School Altera MAX 7000
140870: 09/05/28: Fredxx: Re: Old School Altera MAX 7000
140871: 09/05/27: Gerry_MAN: Re: Old School Altera MAX 7000
140873: 09/05/27: Gerry_MAN: Re: Old School Altera MAX 7000
140900: 09/05/28: Gerry_MAN: Re: Old School Altera MAX 7000
144480: 09/12/09: Gerry_MAN: Altera LP6 Logic Programming Card Acquired!
140878: 09/05/27: -jg: Re: Old School Altera MAX 7000
140874: 09/05/27: radarman: Cyclone III == Spartan ?
140876: 09/05/27: Antti.Lukats@googlemail.com: Re: Cyclone III == Spartan ?
140877: 09/05/28: hvo: writing to reset vectors - xilinx spartan 3an
140880: 09/05/28: gabor: Re: writing to reset vectors - xilinx spartan 3an
140883: 09/05/28: hvo: Re: writing to reset vectors - xilinx spartan 3an
140882: 09/05/28: Weng Tianxiang: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to
140921: 09/05/29: rickman: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140923: 09/05/29: gabor: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140924: 09/05/29: Mike Treseler: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140929: 09/05/29: MikeWhy: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell?
140979: 09/06/01: MikeWhy: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell?
140927: 09/05/29: Weng Tianxiang: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140928: 09/05/29: Weng Tianxiang: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140966: 09/06/01: gabor: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140977: 09/06/01: Weng Tianxiang: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140885: 09/05/28: CMOS: simulating a program inside a soft core with systemc
140886: 09/05/28: Muzaffer Kal: Re: simulating a program inside a soft core with systemc
140893: 09/05/28: <iammayank@gmail.com>: Has ST's FPGA project GOSPL transformed to Morpheus ?
140926: 09/05/29: rickman: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140933: 09/05/30: -jg: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140934: 09/05/30: Antti.Lukats@googlemail.com: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140945: 09/05/30: rickman: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140946: 09/05/30: rickman: Re: Has ST's FPGA project GOSPL transformed to Morpheus ?
140896: 09/05/28: Cy Drellinger: ISE USB Slave Parallel programming
140901: 09/05/28: Antti.Lukats@googlemail.com: Re: ISE USB Slave Parallel programming
140903: 09/05/28: Marteno Rodia: I don't like xilinx (again)
140904: 09/05/29: MM: Re: I don't like xilinx (again)
140918: 09/05/29: Mike Treseler: Re: I don't like xilinx (again)
140930: 09/05/29: KJ: Re: I don't like xilinx (again)
140932: 09/05/29: <mtom199@gmail.com>: Re: I don't like xilinx (again)
140999: 09/06/01: Marteno Rodia: Re: I don't like xilinx (again)
140911: 09/05/29: Rebecca: Question about SERR of Xilinx PCIE core.
140915: 09/05/29: Peter: Urgent help with a Simple AND simulation
140919: 09/05/29: Ed McGettigan: Re: Urgent help with a Simple AND simulation
140939: 09/05/30: Peter: Re: Urgent help with a Simple AND simulation
140940: 09/05/30: Peter: Re: Urgent help with a Simple AND simulation
140935: 09/05/30: Antti: patent free ARM cores
140938: 09/05/30: <jon@beniston.com>: Re: patent free ARM cores
140942: 09/05/30: Fredxx: Re: patent free ARM cores
140944: 09/05/30: Rich Webb: Re: patent free ARM cores
140941: 09/05/30: rickman: Re: patent free ARM cores
140943: 09/05/30: <jon@beniston.com>: Re: patent free ARM cores
140949: 09/05/30: Antti.Lukats@googlemail.com: Re: patent free ARM cores
140952: 09/05/30: rickman: Re: patent free ARM cores
140953: 09/05/31: <jon@beniston.com>: Re: patent free ARM cores
140947: 09/05/30: rana: time constraining asynchronous fifo
140948: 09/05/30: Phil Jessop: Re: time constraining asynchronous fifo
140967: 09/06/01: gabor: Re: time constraining asynchronous fifo
140951: 09/05/30: iquadri: Xilinx PDR flow questions - Time function and DDR RAM access
140958: 09/05/31: radarman: GMII pinning issue
140960: 09/05/31: <cpandya@yahoo.com>: Virtex4 LX DCM Minimum Input Frequency
140961: 09/05/31: Peter Alfke: Re: Virtex4 LX DCM Minimum Input Frequency
140962: 09/05/31: vcar: Micron SODIMM Type Variation
141035: 09/06/02: vcar: Re: Micron SODIMM Type Variation
141046: 09/06/03: LittleAlex: Re: Micron SODIMM Type Variation
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