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Jonathan Bromley a écrit : > On Tue, 5 May 2009 02:22:44 -0700 (PDT), Nicolas Matringe wrote: > >> I'm just done with this and since this a quite frequent question I >> thought I might give my solution so that the time I struggled with >> this probllem will benefit to others. > > Thanks for the nice writeup. Useful! Now that I upgraded to ISE 11.1 it doesn't work anymore. The additional space between the last quotes must be removed. NicolasArticle: 140351
anand wrote: > Hi > > I am looking to get some info on implementing arbitrary combinational > functions in large designs using block rams (BRAMs). The target is an > emulation platform using Virtex 4 fpgas > ... > Now the question is - is this a feasible way to reduce LUTs and > thereby area? . see the mapper switch -bp "map slice logic into unused block rams" -JeffArticle: 140352
On May 10, 12:51=A0am, anand <writean...@gmail.com> wrote: > Hi > > I am looking to get some info on implementing arbitrary combinational > functions in large designs using block rams (BRAMs). The target is an > emulation platform using Virtex 4 fpgas > > For example > > assign x =3D ^a > =A0 where a is an 8 bit input for example. > > in normal fpga synthesis will use LUTS. > > However I can declare a memory as > > reg [255:0] lookuptable_for_bitwise_xor_mem; > > always@(a) begin > > x <=3D =A0lookuptable_for_bitwise_xor_mem[a]; > end > > I would have pre loaded =A0lookuptable_for_bitwise_xor_mem with the > truth table for 8 input bitwise XOR. > > Note that this is just one example. > > The advantage is that I use little LUTs and only Block RAMs (which are > unused otherwise), therefore rducing area. > > If there is another assign that takes a bitwise xor of 8 bit vector, I > can use the same ROM and reuse the ROM. > > Example: > > assign x =3D ^a > assign y =3D ^b > =A0where a, b is an 8 bit input for example. > > becomes > > always@(a or b) begin > > x <=3D =A0lookuptable_for_bitwise_xor_mem[a]; > y <=3D =A0lookuptable_for_bitwise_xor_mem[b]; > > end > > =A0I am basically trying to use BRAMs that are unused anyway - there are > more than 300 BRAMs per Virtex 4 FPGA each of 16K. > > Now the question is - is this a feasible way to reduce LUTs and > thereby area? . > > -Andy Remember that the BRAM is not a combinatorial look-up table. It give you the desired output after a clock edge. "Nothing happens without a clock". Peter AlfkeArticle: 140353
On Sat, 9 May 2009 21:00:40 -0700 (PDT), Brian wrote: >Thought I would chime in on some of the comments and observations from >this thread. Many thanks for an authoritative and very helpful post. I'd worked some of that stuff out for myself, but there are a few important things you've taught me. Much appreciated. >Neither XST, Synplify or Precision support RAMs with different port >with different port widths. Thanks for saving me some investigation time. This happens to be a feature that I don't need in my current project, but it's worth being aware of the restriction. > my understanding is that the [VHDL] shared variable is >necessary for proper simulation when accessing the same array at the >array at the same time. Yes, if you want WRITE_FIRST behaviour. It should be possible to avoid it if you want READ_FIRST, but since we need shared variables for the WRITE_FIRST template it seems sensible to use them in all forms. Alternatively, a doubly-clocked template would allow the variable to stay local to the process - but that's stretching things a bit. One downside of the shared variable is that it's not strictly VHDL language-compliant, since it doesn't use protected types. Those simulators that understand protected types (VHDL >= 2000) will usually issue a warning for it. This warning can safely be ignored (although, of course, it is in a sense alerting you to the risk of write-write collision!). >In the Single-Port descriptions you >can see the differences between READ_FIRST, WRITE_FIRST and NO_CHANGE >mode however unfortunately for the dual port not all have been adapted Yes, and sometimes it's far from obvious how to extrapolate from the single-port to dual-write description. >I will see if in 11.2 we can get the >templates updated to include all of the dual port examples for these. Simply having authoritative and complete examples in the docs would be a really good start. >One other note, if you are inferring a BRAM in which you never plan to >read from the same port at the time you are writing, describe >NO_CHANGE mode. It will save power but not many realize this. I certainly didn't. Can you (or Peter???) elaborate a bit more? Is the power saving significant in practice? > A behavioral RTL simulation will not alert >or model a collision An assertion could easily be added. I would be very suspicious of an inference template that did not include such an assertion to generate at least a warning. >some synthesis tools have decided to >arbitrate the access to the same memory locations with additional >logic around the BRAM. Both Synplicity and Precision do this however >XST does not. Yes, I'd noticed that. My preference would by far be for XST's approach, but with a suitable assertion in the template. Best of all would be the synth tool checking for existence of such an assertion, and complaining if it was absent :-) > Most people who are aware of this, disable the addition >of the collision avoidance logic using a synthesis attribute I have not yet had the persistence to track down those attributes in the vendor docs. Thanks for alerting me to their existence. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140354
"andip1982" <andreasp1982@arcor.de> wrote in message news:972a27b9-458b-440f-9a5a-b70ef24c628d@q14g2000vbn.googlegroups.com... >I am searching for a simple tool to handle hdl entities similar to > mentor hdl designer. no hdl synthesis required - just edit entites > graphically and keep overview over the hierarchies. > > any idea ? If you're looking for simple, Programmer's Notepad does a pretty fair job of navigating tags on VHDL source.Article: 140355
Thanks to all of your for your responses
Jacko: You are right - the duplication needs to happen depending on
the #read ports to the RAM.
However, we have a custom flow that allows time-multiplexed access to
N read ports (usually
we keep it around 20, can go higher to 32 or even 50 at the expense
of performance, since
more clock edges to the BRAM are needed to read all 50 ports, which
effectively has the effect
of "stretching" the DUT clock cycle === lesser frequency of DUT clock
=== lesser performance.
In other words, our custom flow maps N ports from RTL to 2 physical
ports in BRAM through
time multiplexing.
whygee: Yes, PAR effort will be more. However, when you consider a
multi-fpga design (I am talking
250 FPGA design at a minimum), the number of BRAM's wasted is
tremendous. The LUTs are usually
the bottleneck, not the BRAMs. THis is why the more logic we infer in
BRAM's the better.
JeffC: Thanks for the -bp "map slice logic into unused block rams"
option.
(a) Is it part of Xilinx ISE 11.x? Can you give me some examples
maybe?
(b) does it work well? I See some posts that have mentioned that it
doesnt work well.
what is your experience/suggestion?
I ask this because we have developed a custom flow (as I mentioned
that does something like this:)
RTL Parser, Synthesis (to Virtex 4 gates), Partitioning (a multi FPGA
design so to get the
optimal communication between FPGAs and avoiding long combinational
paths as much as possible).
The net result is User RTL is transformed to multiple EDF files. On
top of this, we add some
vendor specific`instrumentation logic and C code to allow emulator
access to certain internal signals, and other debug features. THEN, it
goes thro the normal xilinx mapping, place and route flow etc. Then
finally, we do some custom post-processing (after the bit files for
the design have been generated) before stimulating the user RTL model
with test content.
Peter: Yes, you are right about the clock. However, based on our
custom flow that I have given an overview of,
the memory operations are transparent to the end-user - i.e all of
the BRAM Read/Write operations happen
in a time multiplexed fashion, and multiple R/W accesses in a single
cycle is done using a memory clock
that is super-fast compared to the emulator "tick" phase length (or
DUT frequency in other words).
In other words, between DUT Cycle N and N+1, there are K memory
clocks that allow for multiple
BRAM access (where K > N). Secondly, the user does NOT see memory
clock and cannot access it - it is completely transparent. Because of
this artefact, if we increase the num ports haphazardly, the DUT clock
cycle will get stretched automatically, thereby reducing performance.
But this rarely happens since
the combinational delays from fpga-fpga are way more than this
"stretching" effect - effectively, the
bottleneck would still be the long combinational paths that span
several fpgas.
Now given this scenario: My question is - how can I use this as a
combinatorial lookup ROM?
WHat are the pros and cons?
In your paper "Creative Uses of Block RAM" @ (An excellent paper
btw, it piqued my curiosity!)
http://www.xilinx.com/support/documentation/white_papers/wp335.pdf
you mention that one can implement sine/cosine functions as a lookup
table.
Why not use it for arbitrary combinational logic as well using lookup
ROMs and use BRAM's that are lying
waste anyway?
Thanks once again and looking forward to have a good discussion with
all of you.
Article: 140356sorry guys the formatting was off on my previous post :(Article: 140357
Any luck with this Partha?Article: 140358
Hi guys, I'd like to get started with FPGAs and I'm looking for a good development board to get started with. Could you please point me to some good boards?Article: 140359
You can look into Altera's DE2 board. It is a very good development board for a starter http://www.altera.com/education/univ/materials/boards/unv-de2-board.html Thanks, HarisArticle: 140360
I want to design a space system and don't want to use airspace expensive fpga. considering space radiation I want to make this system fault tolerant. ACTEL is flash-based but in program lost condition ( even with low probability ) it should be reprogrammed so a programing circuit is also needed. Xilinx or Altera are RAMbased but they have very small size EPROMs to store both hardware configuration and software, so using multiple of EPROMs is possible for redundancy. can anybody suggest better solution or even a new idea?Article: 140361
On May 11, 10:26=A0am, hamze60 <hamz...@gmail.com> wrote: > I want to design a space system and don't want to use airspace > expensive fpga. considering space radiation I want to make this system > fault tolerant. ACTEL is flash-based but in program lost condition > ( even with low probability ) it should be reprogrammed so a > programing circuit is also needed. Xilinx or Altera are RAMbased but > they have very small size EPROMs to store both hardware configuration > and software, so using multiple of EPROMs is possible for redundancy. > can anybody suggest better solution or even a new idea? sorry to ask this but where do you get low cost rocket to get to the thing into space? my son would be very interested, we had long discussion about rockets this weekend. he is only 6, so I had to spend lots of time explaining the laws of aerodynamics eg, why the rockets normally need tail-stabilizing wings when flying in air we later agreed that specially designer rocket body could also guarantee stable flight in the air (without any wings/stabilizers) if designed properly. (very likely i have to design such a rocket now!!) AnttiArticle: 140362
Hi it will be only short clip in local TV (estonian, kanal-2) in the DIY show, but was still funny to look into the camera with FPGA board in the hands. the highlite is actually on the "Electronic Constructor - CRUVI(tm)" as such, not at all on FPGA's (the audience is too generic), but the TV demo was made with the ACTEL FPGA module on the CRUVI baseboard, not with some MCU board. I got the PCBs (27 different ones!) just a few days before the TV shooting, so only prepared very simple stupid and annoying demo making some REAL annoying sound, and displaying 8 bit counter on LED strips. The all demo was done (actually copy paste from web) withing 2 hours or so what included modification of the source code, intitial test on S3A starterkit then porting to Actel libero, and programming the actual target module. most of the time was setting up the io pad mapping constraints, i managed to get it wrong a few times. I guess it would have been hard to make similar demo faster with MCU and generic C programming. AnttiArticle: 140363
I think nearest possible approximation is 125Mz / ( 61 * 8 ) = 256.14 Kz. you can use a counter to make this frequency easily. but PLL is also another solution.usually FPGAs have a unit inside called PLL, one of its main application is to make a frequency from system clock. PLL is a analog circuit which can generate multiply ( not only divide ) of a frequency so PLL will give you the nearest possible frequency you want. for example ACTEL has a graphical tool for make desirable frequency but is has a down limit of 0.75 Mhz go generate.Article: 140364
On May 11, 3:08=A0am, Samuel Thomas Kerr <stk...@cs.purdue.edu> wrote: > Hi guys, I'd like to get started with FPGAs and I'm looking for a good > development board to get started with. > > Could you please point me to some good boards? Samuel, You can also have a look at the Sundance University Program: http://www.sundance.com/web/files/static.asp?pagename=3Dchoice It allow universities and research labs to purchase a highly discounted prices industrial-standard multiprocessor-based hardware development platforms with all necessary software for Software defiened radio (SDR, telecoms, UWB radio), Wireless (WiMAX, MIMO, LTE), Video-Imaging, Embedded vision, Control and automation, High- performance parallel computing (HPEC, HPC)... Thank you, - SebastienArticle: 140365
> >"lioncat" <dominghang@hotmail.com> wrote in message >news:gI2dnYJKlIWPz5nXnZ2dnUVZ_oGdnZ2d@giganews.com... > >>> >> Thank you for reply. But I have already read the library and the template >> of the ODDR. However my problem is in the map. The unit cannot be mapped. >> I >> want to figure out how to solve this situation. > >So, even if you use the exact template they suggest, maybe with a really >simple experimental design, the map doesn't work? Did you also try looking >at XAPPs with DDR? What about the FDDRRSE part, did you try that? >HTH., Syms. > > > Thank you for reply. I have tried your suggestion to use the ODDR in a simple experimental design. And it turns out success in MAP. So I took a deep look at my older design. Then I think the problem is that in it the ODDR is not directly following by the OBUFDS, but a flip-flop. Therefore I changed the design and it passed the MAP and Place and Route. Maybe it will also work with OSEREDS. Thanks a lot!Article: 140366
><Antti.Lukats@googlemail.com> wrote in message >news:0b8f026a-a206-4d6f-9f9d->97dd719de5e8@r36g2000vbr.googlegroups.com... >On May 11, 10:26 am, hamze60 <hamz...@gmail.com> wrote: >> I want to design a space system and don't want to use airspace >> expensive fpga. considering space radiation I want to make this system >> fault tolerant. ACTEL is flash-based but in program lost condition >> ( even with low probability ) it should be reprogrammed so a >> programing circuit is also needed. Xilinx or Altera are RAMbased but >> they have very small size EPROMs to store both hardware configuration >> and software, so using multiple of EPROMs is possible for redundancy. >> can anybody suggest better solution or even a new idea? > >sorry to ask this but where do you get low cost rocket to get to the >thing into space? There are a number of places, in my previous company we used Ariane4 ASAP and later Russian Cosmos launchers from Plesetsk (interesting place to say the least :-) We used military grade Actel A1010, A1020 and 1280 and they all worked great but then again we launched into a quite a "mild" radiation orbit (LEO,800KM), Hans www.ht-lab.com > >my son would be very interested, we had long discussion about rockets >this weekend. >he is only 6, so I had to spend lots of time explaining the laws of >aerodynamics >eg, why the rockets normally need tail-stabilizing wings when flying >in air >we later agreed that specially designer rocket body could also >guarantee >stable flight in the air (without any wings/stabilizers) if designed >properly. >(very likely i have to design such a rocket now!!) > > >AnttiArticle: 140367
On Mon, 11 May 2009 01:05:13 -0700, hamze60 wrote: > I think nearest possible approximation is 125Mz / ( 61 * 8 ) = 256.14 > Kz. you can use a counter to make this frequency easily. but PLL is > also another solution.usually FPGAs have a unit inside called PLL, one > of its main application is to make a frequency from system clock. PLL is > a analog circuit which can generate multiply ( not only divide ) of a > frequency so PLL will give you the nearest possible frequency you want. > for example ACTEL has a graphical tool for make desirable frequency but > is has a down limit of 0.75 Mhz go generate. You could also use a completely digital fractional-N divider to produce the exact ratio. This works by dividing by 488 or 489, so that the average is 488.28125 (= 125MHz / 256kHz) and there are 32 output clocks for every 15625 input clocks. It will generate just under 8ns p-p jitter though. Any of the standard fractional-N divider topologies is ok here, with the notable exception of the binary phase accumulator, which is incapable of generating this ratio exactly. Regards, AllanArticle: 140368
Still one question After map, place and route, I ran the post route simulation, then I have the error as following, # ** Error: /X_ODDR SETUP High VIOLATION ON D1 WITH RESPECT TO C; # Expected := 0.434 ns; Observed := 0.386 ns; At : 68993.604 ns # Time: 68993604 ps Iteration: 2 Instance: /test_03_04_09/uut/loop_ddr_c_4_oddr_c Does anyone have idea about solving this kind of error?Article: 140369
On May 10, 8:08=A0pm, Samuel Thomas Kerr <stk...@cs.purdue.edu> wrote: > Hi guys, I'd like to get started with FPGAs and I'm looking for a good > development board to get started with. > > Could you please point me to some good boards? Hello Samuel, A board that I have really enjoyed using and is very affordable is the Spartan-3E Starter Kit. This board has a ton of example projects ranging from the very basics all the way up to running ucLinux. At $149 it is hard to beat the price. http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm If you are looking for the most cost effective board then there is the Spartan 3A evaluation kit which goes for $49. It is not as powerful but will let you get your feet wet. http://www.em.avnet.com/evk/home/0,4534,CID%253D46501%2526CCD%253DUSA%2526S= ID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF2%2526CTP%253D= EVK,00.html?SUL=3Dspartan3a-evl And finally, if you are interested in getting involved with an open source design then you could look at my open source FPGA board which is a work in progress and can be found at: http://www.gadgetfactory.net Jack Gassett http://www.GadgetFactory.net Home of the ButterFly Platform, an open source FPGA hardware and software project.Article: 140370
On Sun, 10 May 2009 22:08:59 -0400, Samuel Thomas Kerr <stkerr@cs.purdue.edu> wrote: >Hi guys, I'd like to get started with FPGAs and I'm looking for a good >development board to get started with. > >Could you please point me to some good boards? Digilent has quite a few http://digilent.us/. Also look at http://www.fpga4fun.com/ (for info) and the companion site http://www.knjn.com/ (for the boards). -- Rich Webb Norfolk, VAArticle: 140371
My code is virtually this same thing. The tool tells me I am trying to infer two ports using distributed memory which it can't do. Rick On May 9, 5:26=A0pm, Sandro <sdro...@netscape.net> wrote: > Rick, > I hope this can help... > below you can find the code to infer dual port-ram with > both port sharing the same clock. > I suppose the secret could be using a shared variable (instead of a > signal) as RAM... > > regards > Sandro > > entity ramInference is > =A0 generic ( > =A0 =A0 g_data_w : natural :=3D 9; > =A0 =A0 g_addr_w : natural :=3D 11 > =A0 =A0 ); > =A0 port ( > =A0 =A0 i_clkA =A0: in =A0std_logic; > =A0 =A0 --i_clkB =A0: in =A0std_logic; > =A0 =A0 i_enA =A0 : =A0 =A0 std_logic; > =A0 =A0 i_weA =A0 : =A0 =A0 std_logic; > =A0 =A0 i_addrA : in =A0std_logic_vector (g_addr_w - 1 downto 0); > =A0 =A0 i_dataA : in =A0std_logic_vector (g_data_w - 1 downto 0); > =A0 =A0 o_dataA : out std_logic_vector (g_data_w - 1 downto 0); > > =A0 =A0 i_enB =A0 : =A0 =A0 std_logic; > =A0 =A0 i_weB =A0 : =A0 =A0 std_logic; > =A0 =A0 i_addrB : in =A0std_logic_vector (g_addr_w - 1 downto 0); > =A0 =A0 i_dataB : in =A0std_logic_vector (g_data_w - 1 downto 0); > =A0 =A0 o_dataB : out std_logic_vector (g_data_w - 1 downto 0) > =A0 =A0 ); > end ramInference; > > architecture Behavioral of ramInference is > > =A0 constant c_ram_sz : natural :=3D 2**(g_addr_w); > > =A0 type t_ram is array (c_ram_sz - 1 downto 0) of > =A0 =A0 std_logic_vector (g_data_w - 1 downto 0); > > =A0 shared variable v_ram : t_ram :=3D ( > =A0 =A0 1 =A0 =A0 =A0=3D> X"05", > =A0 =A0 2 =A0 =A0 =A0=3D> X"08", > =A0 =A0 3 =A0 =A0 =A0=3D> X"1A", > =A0 =A0 -- ... > =A0 =A0 others =3D> X"00" > =A0 =A0 ); > > begin > > =A0 p_portA : process (i_clkA) > =A0 begin > =A0 =A0 if rising_edge(i_clkA) then > =A0 =A0 =A0 if (i_enA =3D '1') then > =A0 =A0 =A0 =A0 -- READ FIRST > =A0 =A0 =A0 =A0 o_dataA(g_data_w - 1 downto 0) <=3D v_ram(conv_integer > (i_addrA)); > =A0 =A0 =A0 =A0 -- WRITE AFTER > =A0 =A0 =A0 =A0 if (i_weA =3D '1') then > =A0 =A0 =A0 =A0 =A0 v_ram(conv_integer(i_addrA)) :=3D i_dataA(g_data_w - = 1 downto > 0); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > =A0 p_portB : process (i_clkA) > =A0 begin > =A0 =A0 if rising_edge(i_clkA) then > =A0 =A0 =A0 if (i_enB =3D '1') then > =A0 =A0 =A0 =A0 -- WRITE FIRST > =A0 =A0 =A0 =A0 if (i_weB =3D '1') then > =A0 =A0 =A0 =A0 =A0 v_ram(conv_integer(i_addrB)) :=3D i_dataB(g_data_w - = 1 downto > 0); > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 -- READ AFTER > =A0 =A0 =A0 =A0 o_dataB(g_data_w - 1 downto 0) <=3D v_ram(conv_integer > (i_addrB)); > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process; > > end Behavioral;Article: 140372
I know I'm a little late on this thread, but offer my two cents,
on what we use, and a warning as well.
We use dual-port RAMS (same clock) with inference, and don't have
trouble. It's in verilog, and it's READ_FIRST. So two strikes
against it for what you're looking for Rick. (you want VHDL, and
WRITE_FIRST, I beleive). We call this our "mem2rw1clk" module.
But here's what we do (minus header/etc):
always @( posedge clk )
begin
if( en0 )
begin
if( wren0 )
mem[ addr0 ] <= wdata0;
rdata0 <= mem[ addr0 ];
end
end
always @( posedge clk )
begin
if( en1 )
begin
if( wren1 )
mem[ addr1 ] <= wdata1;
rdata1 <= mem[ addr1 ];
end
end
So, two almost identical always blocks, operating on the same RAM.
Since we use non-blocking assignments, the READ_FIRST is implied
(correctly by XST).
Works, and we've been using it for many designs no trouble.
Now the warning:
We use almost the EXACT same structure for implementing a pseudo
dual port - i.e. an independant READ port, and a WRITE port
(same clock) "mem1r1w1clk". I.e. the type of memory you'd
use for a synchronous fifo. The logic is again clearly coded for
READ_FIRST.
Well, XST was (sometimes) inferring WRITE_FIRST. So, simulation
vs implementation mismatch. It only mattered in a few places
we were specifically ALWAYS reading the same location as we
were writing in the same cycle. You get quite different results.
Spent 2-3 weeks on the bench figuring out this one.
So - check the XST report to make sure it's inferring the
correct READ_FIRST vs. WRITE_FIRST behaviour. XST can get things
wrong here.
Regards,
Mark
Article: 140373
On May 11, 12:43=A0pm, Mark <m...@cacurry.net> wrote:
> I know I'm a little late on this thread, but offer my two cents,
> on what we use, and a warning as well.
>
> We use dual-port RAMS (same clock) with inference, and don't have
> trouble. =A0It's in verilog, and it's READ_FIRST. =A0So two strikes
> against it for what you're looking for Rick. =A0(you want VHDL, and
> WRITE_FIRST, I beleive). =A0We call this our "mem2rw1clk" module.
>
> But here's what we do (minus header/etc):
>
> always @( posedge clk )
> begin
> =A0 if( en0 )
> =A0 begin
> =A0 =A0 if( wren0 )
> =A0 =A0 =A0 mem[ addr0 ] <=3D wdata0;
> =A0 =A0 rdata0 <=3D mem[ addr0 ];
> =A0 end
> end
>
> always @( posedge clk )
> begin
> =A0 if( en1 )
> =A0 begin
> =A0 =A0 if( wren1 )
> =A0 =A0 =A0 mem[ addr1 ] <=3D wdata1;
> =A0 =A0 rdata1 <=3D mem[ addr1 ];
> =A0 end
> end
>
> So, two almost identical always blocks, operating on the same RAM.
> Since we use non-blocking assignments, the READ_FIRST is implied
> (correctly by XST).
>
> Works, and we've been using it for many designs no trouble.
>
> Now the warning:
>
> We use almost the EXACT same structure for implementing a pseudo
> dual port - i.e. an independant READ port, and a WRITE port
> (same clock) "mem1r1w1clk". =A0 =A0I.e. the type of memory you'd
> use for a synchronous fifo. =A0The logic is again clearly coded for
> READ_FIRST.
>
> Well, XST was (sometimes) inferring WRITE_FIRST. =A0So, simulation
> vs implementation mismatch. =A0It only mattered in a few places
> we were specifically ALWAYS reading the same location as we
> were writing in the same cycle. You get quite different results.
> Spent 2-3 weeks on the bench figuring out this one.
>
> So - check the XST report to make sure it's inferring the
> correct READ_FIRST vs. WRITE_FIRST behaviour. =A0XST can get things
> wrong here.
>
> Regards,
>
> Mark
I am surprised about the interest in write_first vs read_first.
The read output during a write operation came really about as an
afterthought. ("It's easy, the port is already there, so it costs
nothing").
But why do you want to read from the same location that you are
writing to?
Especially when you are reading what you already know, since you
simultaneously are writing it (which was the original mode).
Then we found that read-before-write was an easy modification, and
more valuable.
But still: why do you read from the write address, when you have a
separate read port with its own dedicated addressing available?
But, judging from the interest in this thread, it seems to be
valuable.
Peter Alfke
Article: 140374On May 11, 7:46=A0pm, rickman <gnu...@gmail.com> wrote: > My code is virtually this same thing. =A0The tool tells me I am trying > to infer two ports using distributed memory which it can't do. Rick, I don't know! It works fine to me (webpack ISE 10.1.03 - linux). Did you try to use shared variable ? In your previous example I saw only "<=3D" instead of ":=3D" to "assign" a shared variable... Sandro
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