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> Yes, I haven't had any problems with that. Thanks for the feedback Sean, I've tried it again and it's working now! Now I can (at last) have a unified project template! Nial.Article: 140276
Sorry if this has been covered already. I am developing a testbench for a design and I want the behavioral models for external devices to use random parameters within the constraints of the data sheets. I figured out how to start up a sim with a seed variable in Modelsim, but now I'm confused about how to use that seed. Say I have two processes, each controlling one aspect of an ADC. Does each process have its own random number stream or do they share some global random number stream? In other words, does each process access a global seed or do they each maintain their own seeds. I was thinking that a global seed may be dangerous because it may change in a non-deterministic fashion. Here is an example with local seeds. The first process controls the ADC convert to busy timing, the second process controls the prop delay through a mux. Each takes the initial value for the seed from the generic for the testbench and then keeps a local copy of the seed. Is this the right way to do this? procedure rand_time( variable seed1, seed2 : inout positive; min, max : in integer; result : out time ) is variable rand : real; begin uniform(seed1, seed2, rand); result := (integer(real(min) + (rand * (real(max)-real(min)) ) ))* 1 ps; end procedure; -- ADC busy timing convert : process variable s1 : integer; variable s2 : integer; variable t6 : time; variable tconv : time; variable init : std_logic; begin -- Init seeds from generic if not already initialized if(init /= '1')then s1 := gSEED; s2 := s1/2 + 50; init := '1'; end if; busy_n <= '1'; wait until falling_edge(convst_n); if(cs_n = '0')and(shtdn_n = '1')then rand_time(s1, s2, MIN_T6, MAX_T6, t6); rand_time(s1, s2, MIN_TCONV, MAX_TCONV, tconv); busy_n <= '0' after t6; wait for (tconv - t6); busy_n <= '1'; dtemp <= din; end if; end process convert; -- mux timing mux : process (en_n, mux_sel) variable s1: integer; variable s2: integer; variable p : time; variable init : std_logic; begin -- Init seeds from generic if not already initialized if(init /= '1')then s1 := gSEED; s2 := s1/2 + 50; init := '1'; end if; rand_time(s1, s2, MIN_DELAY, MAX_DELAY, p); if(en_n = '1') then dout <= (others => 'Z') after p; else dout(15 downto 12) <= mux_sel after p; dout(11 downto 0) <= (others => '0') after p; end if; end process mux;Article: 140277
On Thu, 7 May 2009 04:25:18 -0700 (PDT) recoder <kurtulmehtap@gmail.com> wrote: > Hi FPGA Gurus, > I need to get a Gigabit Ethernet message, change its destination > IP,change some bits in the message(process) and send it out. I figure > out that I need 2 GigE ports to do that. I don't want to pay for the > MAC, so the board should be built with the Virtex 5 FPGAs or Altera > alternatives. > Does a board like this exists? You don't want to pay for a GbE MAC, so instead you want a Virtex 5? I don't want to pay for a flight to Los Angeles, so instead I'm going to buy my own jet and go to flight school. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 140278
On May 6, 2:48=A0pm, "M.Z." <mzdkm...@gmail.com> wrote:
> Hi Rick,
>
> I have had similar problems with the 'Generics, Parameters' under
> 'Synthesis Options'. I could get it to work in a simple example, but
> synthesis did not react on the value for a more complex design.
>
> But there is an alternative through the 'Other XST Command Line
> Options', which is last line in the window with 'Generics,
> Parameters'. You can then use the XST command line syntax, that
> Jan Pech mentioned, thus '-generics {BIDIR=3DTRUE CHANNELS=3D1}'. That
> worked for me.
>
> Good luck,
> Morten
I had thought of that. But it doesn't work an better. Here is the
error message I get when I try it.
WARNING:Xst:2705 - Value 'FPGA_FAMILY_SPARTAN_3' is not a valid value
WARNING:Xst:2312 - Ignoring definition of generic 'DEVICE_FAM' because
of bad value provided
The option lines I tried were
-generics {DEVICE_FAM=3DFPGA_FAMILY_SPARTAN_3}
and
-generics{DEVICE_FAM=3DFPGA_FAMILY_SPARTAN_3}
I also tried it with quotes and got this error message.
ERROR:Xst - CheckCondition -
Xst_HdlConst_Utility::ConvertIntegerToType : unable to adjust constant
<"FPGA_FAMILY_SPARTAN_3"> (type array [1 to 21] of char) to type enum
(fpga_family_spartan_3, fpga_family_lattice_xp, ).
-generics {DEVICE_FAM=3D"FPGA_FAMILY_SPARTAN_3"}
and
-generics{DEVICE_FAM=3D"FPGA_FAMILY_SPARTAN_3"}
I believe I also tried it with spaces around the =3D sign, but the
manual clearly say not to leave spaces there.
I am starting to think the problem is the use of an enumerated value
rather than a string constant or a numerical constant. I changed it
to an integer and it still does not work when using a constant name.
But if an integer value is used, it works ok. It would seem that the
generic input function in XST does not work with symbols, only
values.
Rick
Article: 140279There is no Global seed. The seeds are stored in the seed variables (s1 and s2 in each process) you have. If you monitored them you'd notice that they change every time you call the uniform function, and hence why they are of mode "inout". So in effect there is no "random number stream" as you put it - just a formula that gives you a value based on s1 and s2, and s1 and s2 are changed after each call. This is useful because it allows repeatability of random streams. You can check output by seeding the expected output sequence with the same seeds you initialised the input sequence with.Article: 140280
> procedure rand_time( > variable seed1, seed2 : inout positive; > min, max : in integer; > result : out time > ) is > variable rand : real; > begin > uniform(seed1, seed2, rand); > result := (integer(real(min) + (rand * (real(max)-real(min)) ) ))* 1 > ps; > end procedure; Another point: this function doesnt have the correct probability for min and max occuring. If n is the probability for any value occuring, the values of Min and Max themselves have a probability of n/2. This is because the integer conversion function rounds to nearest rather than truncate which means min and max only have a 0-0.5 range each, rather than 0-1.0. eg: Min = 0, Max = 3. result Actual output before rounding 0.0-0.5 0 0.5-1.5 1 1.5-2.5 2 2.5-3.0 3 Therefore 1 and 2 are each twice as likely to occur than 0 and 3. I have a very similar procedure for integers, and found the solution to the problem thus (thanks to who posted the random testing package the other week :) ): procedure rand_int( variable seed1, seed2 : inout positive; min, max : in integer; result : out integer) is variable rand : real; variable val_range : real; begin assert (max >= min) report "Rand_int: Range Error" severity Failure; uniform(seed1, seed2, rand); val_range := real(Max - Min + 1); result := integer( trunc(rand * val_range )) + min; end procedure; This increases theArticle: 140281
rickman wrote:
> But if an integer value is used, it works ok. It would seem that the
> generic input function in XST does not work with symbols, only
> values.
The last time I tried this,
many years ago on Mentor Leo,
only integers worked for top generics.
That is when I started using a package declaration above
the top synthesis entity declaration.
That way, I can use whatever I types I like.
package foo_pkg is
type template_t is (v_rst, a_rst, s_rst, so_rst);
-- ...
end package uart_pkg;
use work.foo_pkg.all;
entity foo is
generic (template_g : template_t := v_rst);
port (
clock : in std_ulogic;
reset : in std_ulogic;
...
-- Mike Treseler
Article: 140282I am using block rams in three places in my design. One of them is what some call a pseudo dual port with a write port and a read port. Another has a read/write port and a second read port. Both of these have been successfully inferred using some code I found here. However, the third block ram has two read/write ports although they share a common clock. I have not been able to infer this third block ram. I did some searching here and found a number of posts on the subject. But I still have not found anything that will infer full dual port block ram. Anyone else have success? RickArticle: 140283
"leevv" <leevv@mail.ru> wrote in message news:26e4d8a3-8437-4498-a929-550be1b7a67a@m24g2000vbp.googlegroups.com... > 1) XPS_INTC v1.00a synchronization FFs for the edge-type interrupts. I've just checked what's included in EDK11.1. This problem has been fixed in the XPS_INTC v2.00a. However, speaking of synchronizers there is a more general problem of controlling synchronizers' MTBF in any of the EDK IP cores. Essentially there need to be MAX_DELAY constraint added for each and every such syncronizer, because otherwise the tools have no idea that you need more time to resolve metastabilty than would be required to satisfy setup/hold time. Some useful links on the topic: http://forums.xilinx.com/t5/PLD-Blog/Metastable-Delay-in-Virtex-FPGAs/ba-p/7996 www.xilinx.com/support/documentation/application_notes/xapp094.pdf http://www.aspenlogic.com/images/alj001.pdf /MikhailArticle: 140284
On May 7, 11:57=A0am, rickman <gnu...@gmail.com> wrote: > I am using block rams in three places in my design. =A0One of them is > what some call a pseudo dual port with a write port and a read port. > Another has a read/write port and a second read port. =A0Both of these > have been successfully inferred using some code I found here. > However, the third block ram has two read/write ports although they > share a common clock. =A0I have not been able to infer this third block > ram. > > I did some searching here and found a number of posts on the subject. > But I still have not found anything that will infer full dual port > block ram. > > Anyone else have success? > > Rick Rick, Xilinx uses the terms "true dual-port" when both ports are read/ write, and "simple dual-port" when one is read, the other write. True dual port is obviously a superset of simple dual port, but there is one limitation: True dual-port cannot handle the widest data path (the one that simple dual port can handle). The reason is that true dual port needs four data buses to connect to the BRAM. Hope this helps. Peter Alfke, from home.Article: 140285
Dear All, I'm wondering whether to use 10/100 Ethernet and CAN controller chips (two of each) in a new design or just put cores from OpenCores inside an FPGA (which we will need in both cases). I'm (still) new to FPGA's and have never used cores from OpenCores. Has anybody used these cores? Are they reliable and ready for production use? The third alternative is to buy commercial IP blocks, but I'm afraid they might cost more than the old-fashioned way (the production volumes will be relatively small). I'd appreciate any facts and/or opinions. :) -jmArticle: 140286
On Thu, 7 May 2009 11:57:34 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >I am using block rams in three places in my design. One of them is >what some call a pseudo dual port with a write port and a read port. >Another has a read/write port and a second read port. Both of these >have been successfully inferred using some code I found here. >However, the third block ram has two read/write ports although they >share a common clock. I have not been able to infer this third block >ram. > >I did some searching here and found a number of posts on the subject. >But I still have not found anything that will infer full dual port >block ram. > >Anyone else have success? No, I'm banging my head against the same issue right now. The XST User Guide for version 11 says it can be done, but I haven't yet installed ISE11. Can't seem to do it in Quartus either. Nor can I get Synplify or Precision to understand it, though in fairness I haven't done enough rummaging in the docs yet. Back to the dreaded component wizards, I guess :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140287
On May 7, 3:45 pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On May 7, 11:57 am, rickman <gnu...@gmail.com> wrote:
>
> > I am using block rams in three places in my design. One of them is
> > what some call a pseudo dual port with a write port and a read port.
> > Another has a read/write port and a second read port. Both of these
> > have been successfully inferred using some code I found here.
> > However, the third block ram has two read/write ports although they
> > share a common clock. I have not been able to infer this third block
> > ram.
>
> > I did some searching here and found a number of posts on the subject.
> > But I still have not found anything that will infer full dual port
> > block ram.
>
> > Anyone else have success?
>
> > Rick
>
> Rick, Xilinx uses the terms "true dual-port" when both ports are read/
> write, and "simple dual-port" when one is read, the other write.
> True dual port is obviously a superset of simple dual port, but there
> is one limitation:
> True dual-port cannot handle the widest data path (the one that simple
> dual port can handle). The reason is that true dual port needs four
> data buses to connect to the BRAM.
> Hope this helps.
> Peter Alfke, from home.
Thanks for the reply. I am only using 18 bit wide memory, so that
should still be workable with true dual port ram. I am also only
asking for half the size of a single block ram. I assume the tools
are capable of setting the high order address bit to a constant.
Just in case anyone would like to see the code...
DPT_INFR: process (SysClk)
begin
if (rising_edge(SysClk)) then
DatRdAddr <= DatAddr;
RetRdAddr <= RetAddr;
if (DatPop = '0') then
InstRAM(to_integer(unsigned(DatAddr))) <= std_logic_vector
(DatToS);
end if;
if (RetPop = '0') then
InstRAM(to_integer(unsigned(RetAddr))) <= std_logic_vector
(RetToS);
end if;
end if;
end process DPT_INFR;
DatMem <= InstRAM(to_integer(unsigned(DatRdAddr)));
RetMem <= InstRAM(to_integer(unsigned(RetRdAddr)));
--
Rick
Article: 140288Hi! I've heard that FPGAs are good for doing some cryptography... Do any of you have experience in cryptography projects and FPGAs? What tools are available? (better if they are free). I suppose I have to code in C/C++ and then synthesize that code to the hardware using a tool? Thanks,Article: 140289
On May 7, 4:04=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 7 May 2009 11:57:34 -0700 (PDT), rickman <gnu...@gmail.com> > wrote: > > >I am using block rams in three places in my design. =A0One of them is > >what some call a pseudo dual port with a write port and a read port. > >Another has a read/write port and a second read port. =A0Both of these > >have been successfully inferred using some code I found here. > >However, the third block ram has two read/write ports although they > >share a common clock. =A0I have not been able to infer this third block > >ram. > > >I did some searching here and found a number of posts on the subject. > >But I still have not found anything that will infer full dual port > >block ram. > > >Anyone else have success? > > No, I'm banging my head against the same issue right now. =A0 > The XST User Guide for version 11 says it can be done, > but I haven't yet installed ISE11. =A0Can't seem to do it in > Quartus either. =A0Nor can I get Synplify or Precision > to understand it, though in fairness I haven't done > enough rummaging in the docs yet. > > Back to the dreaded component wizards, I guess :-( > -- > Jonathan Bromley, Consultant I seem to recall that a thread here just a few months ago came to the same conclusion. But I also found info saying that it could be done, they just didn't give examples that were for "Write First" read access which I need. I also recall that one of the problems was that most of the code specifies some particular operation when both ports write to the same address simultaneously while the ram operation is undefined. I think there is a similar issue when one port writes to an address while the other port reads the same address. Because of a possible mismatch between synthesis and simulation, they don't infer a block ram or infer a block ram with additional logic. In my case I'm getting 9000 FFs! You would think if there were an inference solution, they would make it crystal clear in the docs, wouldn't you? RickArticle: 140290
Xin Xiao <spam@spam.com> wrote: > I've heard that FPGAs are good for doing some cryptography... > Do any of you > have experience in cryptography projects and FPGAs? What exactly do you want to do in cryptography. There have been stories about brute force cracking of DES, for example, using FPGAs. > What tools are available? (better if they are free). > I suppose I have to code in C/C++ and then synthesize that > code to the hardware using a tool? As far as I know, that is pretty much never a good way to do it. The big advantage to using FPGAs is that you can do many operations in parallel. Starting with a serial algorithm is unlikely to result in, for example, a systolic array processor. -- glenArticle: 140291
>> Nor can I get Synplify or Precision
>> to understand it, though in fairness I haven't done
>> enough rummaging in the docs yet.
OK, I take it all back, I was doing something
stupid - no change there then :-)
Precision Synthesis correctly generated
write-first dual-port blockRAM in Spartan3
from this code:
reg [DATA_BITS-1:0] mem [0:(1<<ADRS_BITS)-1];
always @(posedge clock0) begin
if (WrEna0) mem[adrs0] = dataWr0;
dataRd0 <= mem[adrs0];
end
always @(posedge clock1) begin
if (WrEna1) mem[adrs1] = dataWr1;
dataRd1 <= mem[adrs1];
end
but NOTE CAREFULLY that I kept the two clocks separate;
with a common clock, I got the anti-contention circuit
(equality check on addresses for simultaneous write).
So I don't know how this would pan out if I were to
put this block down into a bigger design where clock0
and clock1 happened to be the same signal.
XST gave me the right results for write-first (use <=
instead of = in the write assignments) even with a
single clock, but I haven't yet sorted out the read-first
form.
I'll try to do some more work on this with up-to-date
versions of the various tools and report back.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 140292
On 7 Maj, 15:23, Sean Durkin <news_MO...@tuxroot.de> wrote:
> Nial Stewart wrote:
> > It would be really convenient to be able to declare an $Altera_Libraries
> > environmental variable and use this in Modelsim.ini, the way the $Model_Tech
> > one is. This could be set once for the machine then the same directories
> > copied/revision controlled machine independantly.
>
> > I've played about with this but haven't had any sucess.
>
> > Has anyone got anything similar to work?
>
> Yes, I haven't had any problems with that.
>
> In my case it's Xilinx libraries, and I put them in the directory
> defined by the $XILINX environment variable, wich I can use in the
> modelsim.ini, so this should work for you as well.
>
> I suspect there's a problem with the environment variable itself. I know
> that in Linux/UNIX it matters in what startup script you define the
> variable in. It might be that you put it in ~/.bash_profile, and that
> isn't executed for non-login shells or something (I could never wrap my
> head around this sort of stuff...). In Windows this should not be an issue.
>
> I'd first check if the variable is in fact available in ModelSim. Start
> ModelSim like you usually do, and check the variable ("set
> env(altera_libraries)" or something). If that doesn't give you the right
> value, then you need to define the variable somewhere else.
>
> In some Linux distros you have /etc/profile.local for that kind of stuff
> (variables that should be set for all users and all shells) or a
> /etc/bash.bashrc that is executed for every Bash started (bur not for
> ZSH or whatever else is there).
>
> HTH,
> Sean
>
> --
> Replace "MONTH" with the three-letter abbreviation of the current month
> (simple, eh?).
_
Instead of getting lost in your (personal account or
computer)'s .bashrc
.bash_profile .login etc. try using a script - that goes with the
design
(i.e. checked in with source code) - that sets up the necessary
environment for the design.
This script should point out paths to tool and tool-version binaries,
library mappings to precompiled combinations of xilinx/altera with
modelsim/actel with synplify/leonardo etc...
In a unix-like environment you can "source" this file to setup
environment
variables to do just that. Cygwin will give you this on a NT/XP
computer,
maybe .bat files can to??
Regards -- Pontus
Article: 140293
Jukka Marin wrote:
> I'm wondering whether to use 10/100 Ethernet and CAN controller chips
> (two of each) in a new design or just put cores from OpenCores inside
> an FPGA (which we will need in both cases).
If you are in a hurry, use the chips.
> I'm (still) new to FPGA's
> and have never used cores from OpenCores. Has anybody used these cores?
Not after looking at the code.
> Are they reliable and ready for production use?
Probably not.
> The third alternative is to buy commercial IP blocks, but I'm afraid
> they might cost more than the old-fashioned way (the production volumes
> will be relatively small).
That is correct.
> I'd appreciate any facts and/or opinions. :)
The above is 100% opinion.
-- Mike Treseler
Article: 140294On Thu, 2009-05-07 at 19:53 +0000, Jukka Marin wrote: > I'm wondering whether to use 10/100 Ethernet and CAN controller chips > (two of each) in a new design or just put cores from OpenCores inside > an FPGA (which we will need in both cases). I'm (still) new to FPGA's > and have never used cores from OpenCores. Has anybody used these cores? > Are they reliable and ready for production use? > > I'd appreciate any facts and/or opinions. :) We are using OpenCores CAN controller for some time now (with a SoC on Xilinx FPGA). Works great, using it for Low- and HighSpeed CAN (transceiver next to FPGA) - nothing to complain about :-). It has the well-known SJA1000 interface, ... JoachimArticle: 140295
You can simplify this greatly by using the packages that I developed. They layer on top of procedure uniform. Packages and usage notes are available at: http://www.synthworks.com/downloads/index.htm The presentation focuses on randomizing integers, however, time values can be generated by multiplying by 1 ns. To inspire you, your process would be: Compile packages - directions are in the download Use SynthWorks.RandomPkg.all ; -- reference package process variable RV : RandomPType ; -- declare randomization variable begin -- Initialize Seed -- done once RV.SetSeed( (7, 1) ) ; -- optional if you only are doing one thread of randomization ... p := 1 ns * RV.RandInt(MIN_DELAY, MAX_DELAY) ; Cheers, Jim SynthWorks VHDL Training P.S. We teach randomization plus self-checking, transaction-based testing, and verification data structures (linked-lists, scoreboards, memories), in our VHDL Testbenches and Verification classes. See: http://www.synthworks.com/vhdl_testbench_verification.htmArticle: 140296
On May 7, 1:38=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> >> =A0Nor can I get Synplify or Precision
> >> to understand it, though in fairness I haven't done
> >> enough rummaging in the docs yet.
>
> OK, I take it all back, I was doing something
> stupid - no change there then :-)
>
> Precision Synthesis correctly generated
> write-first dual-port blockRAM in Spartan3
> from this code:
>
> =A0 reg [DATA_BITS-1:0] mem [0:(1<<ADRS_BITS)-1];
>
> =A0 always @(posedge clock0) begin
> =A0 =A0 if (WrEna0) mem[adrs0] =3D dataWr0;
> =A0 =A0 dataRd0 <=3D mem[adrs0];
> =A0 end
> =A0 always @(posedge clock1) begin
> =A0 =A0 if (WrEna1) mem[adrs1] =3D dataWr1;
> =A0 =A0 dataRd1 <=3D mem[adrs1];
> =A0 end
>
> but NOTE CAREFULLY that I kept the two clocks separate;
> with a common clock, I got the anti-contention circuit
> (equality check on addresses for simultaneous write).
> So I don't know how this would pan out if I were to
> put this block down into a bigger design where clock0
> and clock1 happened to be the same signal.
>
> XST gave me the right results for write-first (use <=3D
> instead of =3D in the write assignments) even with a
> single clock, but I haven't yet sorted out the read-first
> form.
>
> I'll try to do some more work on this with up-to-date
> versions of the various tools and report back.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
Here is a short Xiinx tutorial:
When you write, you also ("or free") perform a read operation on the
same port, at the same address.
Clock timing is internally manipulated such that you either read first
before writing, or write first before reading. You can also select to
not update the read output.
This can get tricky when you use both ports with a common address. The
small timing adjustment might not be big enough to cover up any
possible clock timing differences between the two ports.
All this is irrelevant if you do not care about the "free" read output
during a write access, or you know that you will never access the same
location from both ports "simultaneously".
Peter Alfke
Article: 140297
hi all,
i wanted to port map a single bit of type std_logic_vector to a
single port of type std_logic but faced difficulty in doing so. is
this actually possible. if yes please give me some suggestions.
any suggestions would be highly appreciated.
thank you
Article: 140298<prashant.gyawali@gmail.com> wrote in message news:298f454e-1329-4f95-a648-bc6815bebb7c@d38g2000prn.googlegroups.com... > hi all, > i wanted to port map a single bit of type std_logic_vector to a > single port of type std_logic but faced difficulty in doing so. is > this actually possible. if yes please give me some suggestions. > any suggestions would be highly appreciated. > thank you If 'some_vec' is the std_logic_vector inside the component and 'some_bit' is the std_logic that you're trying to connect to one of the bits of the vector (assuming it to be bit 0 here) then... zz : entity work.blah port map(some_vec(0) => some_bit) If it is the other way around then... zz : entity work.blah port map(some_bit => some_vec(0)) KJArticle: 140299
On May 7, 9:06=A0pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On May 7, 1:38=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > >> =A0Nor can I get Synplify or Precision
> > >> to understand it, though in fairness I haven't done
> > >> enough rummaging in the docs yet.
>
> > OK, I take it all back, I was doing something
> > stupid - no change there then :-)
>
> > Precision Synthesis correctly generated
> > write-first dual-port blockRAM in Spartan3
> > from this code:
>
> > =A0 reg [DATA_BITS-1:0] mem [0:(1<<ADRS_BITS)-1];
>
> > =A0 always @(posedge clock0) begin
> > =A0 =A0 if (WrEna0) mem[adrs0] =3D dataWr0;
> > =A0 =A0 dataRd0 <=3D mem[adrs0];
> > =A0 end
> > =A0 always @(posedge clock1) begin
> > =A0 =A0 if (WrEna1) mem[adrs1] =3D dataWr1;
> > =A0 =A0 dataRd1 <=3D mem[adrs1];
> > =A0 end
>
> > but NOTE CAREFULLY that I kept the two clocks separate;
> > with a common clock, I got the anti-contention circuit
> > (equality check on addresses for simultaneous write).
> > So I don't know how this would pan out if I were to
> > put this block down into a bigger design where clock0
> > and clock1 happened to be the same signal.
>
> > XST gave me the right results for write-first (use <=3D
> > instead of =3D in the write assignments) even with a
> > single clock, but I haven't yet sorted out the read-first
> > form.
>
> > I'll try to do some more work on this with up-to-date
> > versions of the various tools and report back.
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
>
> Here is a short Xiinx tutorial:
> When you write, you also ("or free") perform a read operation on the
> same port, at the same address.
> Clock timing is internally manipulated such that you either read first
> before writing, or write first before reading. You can also select to
> not update the read output.
> This can get tricky when you use both ports with a common address. The
> small timing adjustment might not be big enough to cover up any
> possible clock timing differences between the two ports.
>
> All this is irrelevant if you do not care about the "free" read output
> during a write access, or you know that you will never access the same
> location from both ports "simultaneously".
> Peter Alfke
I don't think anyone has a problem understanding how the parts work.
The issue we are having is how to specify the hardware we want in the
HDL.
Rick
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