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> what about using those few random bits You currently create for driving > a chain of registers and adders used in pseudo noise sequences? Well, the problem is that the random bits generated by a LFSR will be the same after a certain amout of time. And I should really have around 50.000 independed values from each other!Article: 135126
Aldec's riviera has some linting, vcom accepts -lint as an argument. I don't know about active hdl. HTH -- PontusArticle: 135127
"knight" <krsheshu@gmail.com> wrote in message news:9435ad0e-1a3b-4397-96e3-02d522d01268@e39g2000hsf.googlegroups.com... > Hi > > how can i represent any number in 32 bit signed 1QN format.. > Let the number be 1.5 > > From web search... http://www.actel.com/ipdocs/CoreCORDIC_DS.pdf Table 3 HTH., Syms.Article: 135128
Hello all, I'm working with an microblaze system and I'm trying to work with a Micron MT48LC16M16 memory and something strange happens, It seem than I can read positions all position but if I try to write in positions 00 and 01 nothing changes and if I write something in positions 02 and 03 they seems to be written in position 00 and 01. It happens the same with the rest of the memory. Any idea?. RegardsArticle: 135129
Check your address/data bit order and pinout. Many Xilinx EDK modules have the MSB on bit 0, while many realworld chips have the LSB on what they call bit 0.Article: 135130
On 16 sep, 22:44, "MM" <mb...@yahoo.com> wrote: > > If it were me, I'd use one parallel, and one USB. =A0Or two USB. =A0Two > > parallel adapters on one PC is asking for trouble... > > Two USB cables are not supported as far as I know. I am not sure about 2 > parallel. I did try using 1 USB and 1 parallel in the past and it worked. > > /Mikhail The FPGA TIM connection is only for JTAG Parallel IV. There is no USB posibility.Article: 135131
> Well, the problem is that the random bits generated by a LFSR will be > the same after a certain amout of time. And I should really have around > 50.000 independed values from each other! You can seed a streamcipher from the LFSR, and then use the streamcipher output as your 50000 independant values.Article: 135132
> The FPGA TIM connection is only for JTAG Parallel IV. What's TIM? /MikhailArticle: 135133
On Sep 17, 5:38=A0am, Klaus Niedermayer <Klaus_Niederma...@yahoo.com> wrote: > > what about using those few random bits You currently create for driving > > a chain of registers and adders used in pseudo noise sequences? > > Well, the problem is that the random bits generated by a LFSR will be > the same after a certain amout of time. And I should really have around > 50.000 independed values from each other! 50 000 is really a small number, typical for a 16-bit LFSR. Nothing stops you from making the LFSR much longer, like 40 to 100 bits, which pushes the repetition out millions and trillions of times. Peter AlfkeArticle: 135134
On 4 set, 22:53, lixia....@gmail.com wrote:
> On 7=D4=C223=C8=D5, =CF=C2=CE=E74=CA=B134=B7=D6, lixia....@gmail.com wrot=
e:
>
>
>
> > hi all,
> > I'm trying to partially reconfigure my device (XC2VP30 on XUP board)
> > through ICAP. I have my
>
> > ICAP attached to OPB which is attached to MicroBlaze.In bitgen.ut file
> > I have set the value of mode pins (M2M1M0) to 1 (PULLUP). So it is not
> > set on 101 which is JTAG mode. The value of persist is NO.Initially my
> > OPB clock frequency is 25MHz .The system contains a hwicap, a
> > uartlite and mdm all attached to the opb. . I'm using EDK9.1.
>
> > i tried to start with an exmaple xhwicap_srp_example.c, but even the
> > part of initialize can't go through;when using XHI_XC2VP30 instead of
> > HWICAP_DEVICEID ,the initialize seems success,but the return of
> > Xhwicap_DeviceRead() is "device is busy",so the following function
> > can't execute.In other word,the deviceread of icap can't sucess,and it
> > leads to device busy and the program hangs.
>
> > Besides,i find out that the program hangs on the setting of RNC
> > register in the Xhwicap_DeviceWrite() function,but the size and offset
> > regiser can be set successfully,
> > I don't get what the problem is.
>
> > In bitgen.ut file I have set the value of mode pins (M2M1M0) to 1
> > (PULLUP). So it is not set on 101 which is JTAG mode,and perisit is
> > set to No.And on the borad ,the config mode controlled by sw9 is not
> > JTAG too.
>
> > i don't know if there is something else need to be noticed?
>
> > I really appreciate it if you could kindly help me out with it.
>
> > Thanks a lot beforehand,
>
> > lixia
>
> my problem is solved when i choose v1_00_b for the ip and v1_00_a for
> the driver.
> thank you for fatma's reply!
I had the same problems that you have, then I change the versions of
ip and driver like you says and now i can execute the function
XHwIcap_DeviceRead. Now, i can read/write the memory range of icap but
only using pointers like this:
char* ptr;
ptr =3D (char *)XPAR_OPB_HWICAP_0_BASEADDR+offset;
*(ptr) =3D 1;
printf("(%x):%x\n", rnc,*rnc);
When I use functions like:
XHwIcap_mGetBram(Xuint32 BaseAddress, Xuint32 Offset)
XHwIcap_StorageBufferRead (XHwIcap *InstancePtr, Xuint32 Address)
....
my system hangs! What's happening?
Other doubt: There are some sequence that I have to flow ? because
when a try to get id code (using XHwIcap_GetConfigReg) from icap AFTER
call HwIcap_DeviceRead, thats not work. When I call
XHwIcap_GetConfigReg before HwIcap_DeviceRead it works fine!
thanks beforeahand rodolfo
Article: 135135Hi: I am testing a code for the Analog-to-Digital Converter that has the Spartan-3A FPGA Starter Kit (LTC1407A-1). The converted value from the ADC is displayed on the LCD. Without sending voltage input to the VINA (Channel 0), when I command the ADC to take a sample of the channel, I get the 11111111111111 value as the digital value that the ADC converted. -->> Is it normal to get that value, when the ADC samples the channel and when I have not sent any voltage to that pin/channel? Thanks, mArticle: 135136
Yeah but you go to Xilinx web page and Spartan E isn't on their main pages. I wondering if they are still new-design items. "Eric Smith" <eric@brouhaha.com> wrote in message news:m3tzcfodpt.fsf@donnybrook.brouhaha.com... > Brad Smallridge wrote: >> What happend to the Spartan E? > > If you mean Spartan-3E, nothing happened to it. It's still > readily available.Article: 135137
On Sep 17, 12:40=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > > If you mean Spartan-3E, nothing happened to it. =A0It's still > > readily available. http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/index= .htmArticle: 135138
On Sep 17, 7:37=A0am, osquillar <ogm101...@hotmail.com> wrote: > Hello all, I'm working with an microblaze system and I'm trying to > work with a Micron MT48LC16M16 memory and something strange happens, > It seem than I can read positions all position but if I try to write > in positions 00 and 01 nothing changes and if I write something in > positions 02 and 03 they seems to be written in position 00 and 01. It > happens the same with the rest of the memory. > > Any idea?. > > Regards Are you using a development board or have you rolled your own? If you produced your own board, check the power pins for proper hookup. It's too wasy to have power not hooked up properly through your part and "accidentally" power the device through address or data lines biasing the protection diodes.Article: 135139
Klaus Niedermayer wrote: > Hi > > I would like to implement an encryption algorithm on my FPGA. The > problem that I face here is that I need to generate each time I run > the algorithms 6 different random masks with 32-bits each. So I am > wondering if anyone has a suggestion how to do that best? Until now I > used LFSR to generate some single bits randomly, however now I should > have in some way "independed" masks for 50.000 different runs. > > Thanks! > Klaus The big question is: just random or secret? If you need IVs (initialization vectors for some encryption modes) then a long enough LFSR or any other pseudo-random number generator should be OK. On the other hand if you need random KEYS that have to be truly random, no matter what algorithm you use, you will need a source of random bits with enough entropy. That's why many programs ask to randomly type on the keyboard or move a mouse when generating random keys.Article: 135140
Klaus Niedermayer wrote: > Hi > > I would like to implement an encryption algorithm on my FPGA. The > problem that I face here is that I need to generate each time I run > the algorithms 6 different random masks with 32-bits each. So I am > wondering if anyone has a suggestion how to do that best? Until now I > used LFSR to generate some single bits randomly, however now I should > have in some way "independed" masks for 50.000 different runs. I saw recent news of a startup offering IP, but that's unlikely to be on real FPGA silicon yet :) All you can get on a FPGA is quasi-random, but you can push the 'quasi' to make attack harder. With a simple LFSR, they follow the same pattern from reset. However, you may be able to hide that, with for example, seeding from SRAM, and using a Pre-INC into a block of SRAM - the sram contents will change after long power offs, and insufficent cycle power which tend to preserve RAM values, will also preserve the counter value, and so tend to fetch another ram location. You can also build Ring oscillators, to get more variables into the process. - ie you add lots of layers, and in unexpected ways. -jgArticle: 135141
On 17 sep, 17:28, jetm...@hotmail.com wrote: > Check your address/data bit order and pinout. =A0Many Xilinx EDK modules > have the MSB on bit 0, while many realworld chips have the LSB on what > they call bit 0. Hello, yes I tried with the address bit order and same result. I have a flash sharing the same address and data bus and works fine.Article: 135142
On 17 sep, 23:20, John_H <newsgr...@johnhandwork.com> wrote: > On Sep 17, 7:37=A0am, osquillar <ogm101...@hotmail.com> wrote: > > > Hello all, I'm working with an microblaze system and I'm trying to > > work with a Micron MT48LC16M16 memory and something strange happens, > > It seem than I can read positions all position but if I try to write > > in positions 00 and 01 nothing changes and if I write something in > > positions 02 and 03 they seems to be written in position 00 and 01. It > > happens the same with the rest of the memory. > > > Any idea?. > > > Regards > > Are you using a development board or have you rolled your own? > If you produced your own board, check the power pins for proper > hookup. =A0It's too wasy to have power not hooked up properly through > your part and "accidentally" power the device through address or data > lines biasing the protection diodes. I rolled my own board. I checked the power and ground supply pins and all is correct. I use the gdb debugger for my application and opening the memory window I see that effect, writing in address 00 has no effect but writing in address 02 the datas seems to be written in address 00 and writing in address 06 the datas are written in address 04, and the value of the address 02 and 06 remains 0xffff. I'm using the mch_opb_sdram controller for this pourpose.Article: 135143
Rob <BertyBooster@googlemail.com> wrote: >Hi fellow forumers, > >We currently have lots of designs implemented with different versions >of ISE. Often when a bug needs to be fixed on an old design the >engineer will check out the code and find that it was last compiled >with an older version of ISE. The user will therefore usually migrate >to the latest version they have installed on their computer. In the >past some designs have simply not built because of things like syntax >changes with UCF files, but I am also worried about more subtle >problems that might arise from using the newer ISE version. >Also, when compiling large designs, a user's computer is utilised >quite heavily (especially memory) limiting what can be done on that PC >until the build finishes. > >For these reasons I was thinking of having an "ISE build PC" which has >all of the versions of ISE we use installed on it. Then, using build >scripts (tcl??), the build process can be automated and the process >will be 100% repeatable and can be performed on an expensive behemoth >PC rather than the user's work station. > >The thing is, I'm not sure how to implement such a thing, or indeed >whether it is a sensible plan. I've had a look through the Xilinx Tcl >stuff and there doesn't seem to be a way of getting a version for the >tools that are being invoked. >Has anyone implemented anything like this? Is it sensible?? This is not difficult. Setting the 'Xilinx' environment variable is enough to select the proper build tools. When using a batch file to build a design this is fairly easy. If you use terminal server, you could create a user for each ISE version and set the environment variable accordingly. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 135144
"John_H" http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/index.htm OK, so what? Doesn't say anything.Article: 135145
On Sep 17, 3:45=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > "John_H"http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_se= ries... > > OK, so what? Doesn't say anything. And you haven't said anything either. You keep saying "Spartan-E" yet inferring "Spartan-3E" despite a 2nd underscore of this difference. Xilinx is still selling devices introduced 10 years ago. The S3E series is rather new, does not address the same market as S3A (or S3 for some parts) and will be around for a very long time as witnessed by the history of Xilinx device offerings. If you have a specific (long) timeframe, contacting your Xilinx sales rep would seem to make the most sense. Digilent has in the past been able to offer the boards to the public directly after an initial period of time. The S3E board was available with the microblaze development kit board version for a short period before it disappeared only to return a few months later. Xilinx emplys Digilent to design the boards and ends up limited as to what they can offer on their website at what time. So. What is your real question and please be a little more complete in what you ask.Article: 135146
On Sep 17, 3:23=A0pm, osquillar <ogm101...@hotmail.com> wrote: > On 17 sep, 23:20, John_H <newsgr...@johnhandwork.com> wrote: > > > > > > > On Sep 17, 7:37=A0am, osquillar <ogm101...@hotmail.com> wrote: > > > > Hello all, I'm working with an microblaze system and I'm trying to > > > work with a Micron MT48LC16M16 memory and something strange happens, > > > It seem than I can read positions all position but if I try to write > > > in positions 00 and 01 nothing changes and if I write something in > > > positions 02 and 03 they seems to be written in position 00 and 01. I= t > > > happens the same with the rest of the memory. > > > > Any idea?. > > > > Regards > > > Are you using a development board or have you rolled your own? > > If you produced your own board, check the power pins for proper > > hookup. =A0It's too wasy to have power not hooked up properly through > > your part and "accidentally" power the device through address or data > > lines biasing the protection diodes. > > I rolled my own board. I checked the power and ground supply pins and > all is correct. I use the gdb debugger for my application and opening > the memory window I see that effect, writing in address 00 has no > effect but writing in address 02 the datas seems to be written in > address 00 and writing in address 06 the datas are written in address > 04, and the value of the address 02 and 06 remains 0xffff. > I'm using the mch_opb_sdram controller for this pourpose.- Hide quoted te= xt - > > - Show quoted text - Perhaps timing is an issue? Do you have the Tco for the address, the Tsu and Th of the memory, and the Tskew of the clock between the two devices? Are any of the address pins shorted to something else on the board? Are you sure? Have you written to all addresses or just the 5 (or so) you've mentioned so far?Article: 135147
I guess, John, I want to know if there is any reason to design with the Spartan-3E now? I know that Xilinx supports their chips for a long time. I called Digilent and a friendly fellow by the name of Jim said that they helped with the design of the Spartan-3AN starter kit, but they don't sell it. And it appears that the kits, the Spartan-3E starter kit and the NEXYS2, have Spartan-3E chips. I do not have a specific long term use for this product as you suggested. I am a Virtex user. Brad Smallridge Ai Vision "John_H" <newsgroup@johnhandwork.com> wrote in message news:d38eb984-c2ad-4289-b0d1-a95e14e0d2d9@b2g2000prf.googlegroups.com... On Sep 17, 3:45 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > "John_H"http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series... > > OK, so what? Doesn't say anything. And you haven't said anything either. You keep saying "Spartan-E" yet inferring "Spartan-3E" despite a 2nd underscore of this difference. Xilinx is still selling devices introduced 10 years ago. The S3E series is rather new, does not address the same market as S3A (or S3 for some parts) and will be around for a very long time as witnessed by the history of Xilinx device offerings. If you have a specific (long) timeframe, contacting your Xilinx sales rep would seem to make the most sense. Digilent has in the past been able to offer the boards to the public directly after an initial period of time. The S3E board was available with the microblaze development kit board version for a short period before it disappeared only to return a few months later. Xilinx emplys Digilent to design the boards and ends up limited as to what they can offer on their website at what time. So. What is your real question and please be a little more complete in what you ask.Article: 135148
Brad Smallridge wrote: > I guess, John, I want to know if there is any > reason to design with the Spartan-3E now? > > I know that Xilinx supports their chips for > a long time. > > I called Digilent and a friendly fellow by the > name of Jim said that they helped with the design > of the Spartan-3AN starter kit, but they don't > sell it. And it appears that the kits, the Spartan-3E > starter kit and the NEXYS2, have Spartan-3E chips. > > I do not have a specific long term use for this > product as you suggested. I am a Virtex user. > > Brad Smallridge > Ai Vision Do you want an externally configured device without dedicated DSP hardware with a higher logic-to-I/O ratio that's not an outrageously large device available for the next 5-10 years? If so, Spartan-3E is probably your choice. S3E is cheaper on a comparable basis to S3. S3E has more logic per I/O than S3A. S3E has a lower top-end than S3: S31600E vs S35000(?) S3A is I/O optimized to give the smallest die for a package-optimized I/O count with the logic filled in the rest of the space. S3A-DSP has dedicated DSP blocks. S3AN has on-board configuration memory for more secure device applications. Rather than S3, then S4, then S5 lines, Xilinx chose to fractionate their S3-style offerings to more effectively address specific market segments, perhaps to avoid people dismissing the other family members as "dead." There is no rumor of any of these devices disappearing. The S3A/N devices are just the latest. The S3E may not be on the FRONT page of the Xilinx site but is 2(-3) clicks away.Article: 135149
Hi all, 1. I have a not gate of TTL logic it has 20ns delay to the input i have given the square wave of 5nsec what will be the output. will the output be the square wave since the delayof the logic is more than the freq of operation doe the not gate work? and if it works upto what freq i can work...... for the same question what will be the output if the input is a sine wave instead of square wave. 2. max how many fanouts can we have for 2 input and gate. On what factors the fanout of a design depends. I think it depends on the voltage the output is driving. 3. for a single Dff (with D as input and Q as outpu and Clk as clock in) what will be the max Freqency it can operate.... i feel the min Time period req is only the tC-Q dealy (Propagation delay of the FF no need to consider the Tsetup time as only One FF is available for Time calculation). Thanks & Regards kil
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