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Messages from 135175

Article: 135175
Subject: Re: Info request about Synplify and Foundation usage
From: flatiron@libero.it
Date: Fri, 19 Sep 2008 04:04:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 16 Set, 18:12, flati...@libero.it wrote:
> Dear all,
> I'm try to use VHDL code with some old XC5202PQ100-6 part that I've
> from my old design. Old design was did by using Foundation 2.1i and
> Schematic Entry, now I'm searching a way to use the VHDL coding to do
> some simple example and learn VHDL. My Foundation tools was only a
> base installation then I don't have the Express feature then no VHDL
> compiler will available, but I've the Synplify 9.2 tool and I can make
> the mapping of VHDL circuit. Now I'm asking if there is a way to
> export the mapped file trough the netlist description (xnf, edf) into
> the old Foundation and merge this device with other device into the
> Schematic Editor. In other word there is a way to import into the
> Foundation tool a device, like a black box then into the device
> library and then use it for the design flow implement stage?
>
> Thanks for reply.
>
> Regards
> Grinch

No one have idea how to do it?

Thanks for your time.

Regards
Grinch

Article: 135176
Subject: What software do use big organizations for Logic Synthesis from HDL?
From: "psihodelia@googlemail.com" <psihodelia@googlemail.com>
Date: Fri, 19 Sep 2008 04:06:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello guys,

we are small young startup from North Europe. We are looking for the
useful information about what Software for Logic Synthesis from VHDL/
Verilog do use different big organizations, like Apple or AMD?

Do they prefer Synopsys or something else to produce gate level
netlists from HDLs ?

Thanks in advance!

Article: 135177
Subject: Re: Clock Enable safe?
From: KJ <kkjennings@sbcglobal.net>
Date: Fri, 19 Sep 2008 05:05:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 19, 4:10=A0am, "t.bartz...@gmx.net" <t.bartz...@gmx.net> wrote:
> On Sep 19, 9:22=A0am, PatC <p...@REMOVETHISpatocarr.com> wrote:
>
>
>
>
>
> > t.bartz...@gmx.net wrote:
> > > The edge-detection is done via two D-FFs connected serially and by an
> > > AND-gate with one negated input,
> > > so the output of the first FF goes into the non-negated and the outpu=
t
> > > of the second into the negated.
> > > The corresponding VHDL code is as follows:
>
> > =A0 =A0If you want to be absolutely sure that this circuit won't go
> > metastable, I'd use three FFs instead of two, and use the last two to
> > generate the enable. The first FF may go metastable, but the other two
> > will be safe.
>
> > proc_FF1 : process (osc)
> > begin
> > =A0 =A0 if (rising_edge(osc)) then
> > =A0 =A0 =A0 =A0ff1_out <=3D ENCODER_SIGNAL;
> > =A0 =A0 =A0 =A0ff2_demet <=3D ff1_out;
> > =A0 =A0 =A0 =A0ff3_demet <=3D ff2_demet;
> > =A0 =A0 end if;
> > end process;
>
> > edge_detected_pulse <=3D ff2_demet and (not ff3_demet);
>
> Hi!
>
> That's what I've feared!
> Ergo: My actual design in fact contains metastability of a certain
> probability. I've also thought about the idea of insertion of a
> further FFs but I've wanted to get shure... Thank you for support!
>

You won't rid yourself of metastability by adding another flop, but
you will be greatly reducing the probability by adding another flop,
at the cost of added latency (maybe that's important, maybe not).  You
could greatly reduce the probability of metastability even more by
adding two, three, four....

Also, the clock rate is important.  Metastability takes some amount of
time to resolve, it doesn't matter if that time comes from adding
flops to a shift chain or simply a slower clock.  A single flop that
is clocked at 10 MHz will be more immune to having something bad
happen due to metastability than a two flop shift chain running at 100
MHz.  In the former case one clock cycle is 100 ns, in the second it
is only 10 ns.

Traditionally, most folks bring in async signals into a 2 flop shift
chain and use the output of that as the synchronous version of that
async signal so adding the second flop as previously suggested is good
enough, but you should take a moment to scan a paper or two about just
what causes metastability in the first place to educate yourself so
you'll know the tradeoffs.

KJ

Article: 135178
Subject: Re: Help~ How to develope with FPGA board?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 19 Sep 2008 13:13:14 +0100
Links: << >>  << T >>  << A >>
On Fri, 19 Sep 2008 01:22:23 -0700 (PDT), KJ <lkjrsy@gmail.com> wrote:

>Hello everyone.
>
>I'm a very beginner wiht FPGA board like following.
>http://hitechglobal.com/catalog/product_info.php?cPath=1&products_id=199
>
>This board contains Virtex5 FXT. I think that I need a ISE 10.1 to
>support it.
>Following is what I'm think of the development procedure.
>
>(1) Make VHDL codes for Virtex5 FXT in ISE 10.1 (?)
Yes.

>(2) Synthesis/Translate/Palce&Part and Simulation
No. Simulate first. Only when the design is working in simulation, go
through Synthesis etc.

(Actually it is worth Synthesis on key parts of the design as you go
along, alongside Simulation, to check their size and speed is good
enough for your purpose)


>In (1), someone told me that I don't need ISE and usually if I
>purchase the FPGA board, software comes along with that. is this
>right?

No. If you bought 100 of the boards, why would you need 100 copies of
the expensive software?

The free WebPack supports the smallest V5 chips. If you have got the
smallest version of this board, with the V5LXT50, I think Webpack
supports that. But for the bigger V5FXT70 on this board you definitely
need both full ISE and a separate simulator. 

(The simulator built into ISE10.1 will work with small designs, but
probably not for anything using the PowerPC blocks in that FPGA.)

>In (3), How to configure the chip? I have never done this before.
>Could you explanin the procedure of configuration?
> This board has the
>flash memory for FPGA configuration and storage.

While developing designs, you will probably configure via JTAG over the
USB cable. Other ways of configuring should be described in the board's
documentation.

- Brian

Article: 135179
Subject: Re: What software do use big organizations for Logic Synthesis from
From: morphiend <morphiend@gmail.com>
Date: Fri, 19 Sep 2008 06:29:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 19, 7:06=A0am, "psihode...@googlemail.com"
<psihode...@googlemail.com> wrote:
> Hello guys,
>
> we are small young startup from North Europe. We are looking for the
> useful information about what Software for Logic Synthesis from VHDL/
> Verilog do use different big organizations, like Apple or AMD?
>
> Do they prefer Synopsys or something else to produce gate level
> netlists from HDLs ?
>
> Thanks in advance!

Since this is on ca.FPGA I'll respond from the FPGA standpoint:

Usually, the tool for the logic synthesis is the one provided by the
vendor of the FPGA. In other words, if I'm building for an Altera
FGPA, I'll use Altera's tools (Quartus). If I'm working on Xilinx
parts, I'll use Xilinx tools (ISE).

-- Mike

Article: 135180
Subject: Re: What software do use big organizations for Logic Synthesis from HDL?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 19 Sep 2008 15:50:37 +0100
Links: << >>  << T >>  << A >>
On Fri, 19 Sep 2008 04:06:51 -0700 (PDT), "psihodelia@googlemail.com"
<psihodelia@googlemail.com> wrote:

>we are small young startup from North Europe. We are looking for the
>useful information about what Software for Logic Synthesis from VHDL/
>Verilog do use different big organizations, like Apple or AMD?
>
>Do they prefer Synopsys or something else to produce gate level
>netlists from HDLs ?

First, note that "big organizations" usually have access to
pretty much any tools they need, although they may have a
particularly favourable relationship with one specific tool
vendor and therefore have an in-house tool flow built around
those tools.

Second, note too that some of the really big cutting-edge chip
companies (IBM, Intel, ...) have in-house tools for some or
all of the flow.  That doesn't stop them using the usual
commercial tools as well, of course.

When targeting ASIC/custom technology, front-end (RTL) 
synthesis is dominated by Synopsys Design Compiler, 
Cadence RTL Compiler, and Magma (BlastFusion I think, 
but I'm not sure); there are others, but I don't think 
I'm misrepresenting anyone by saying that those three 
have the lion's share of the market between them.
John Cooley's website "deepchip.com" is a good place 
to look for gossip and statistics, but of course - like 
any snapshot based on what self-selected users say - it 
should be taken with a pinch of salt.

Morphiend told you that FPGAs are usually synthesized with
FPGA-vendor tools, where Xilinx and Altera are dominant.  
I am quite sure that in terms of design starts (number of new
designs synthesized) he's right, but it would be very wrong
to ignore the third-party FPGA synthesis tools where
Mentor Graphics' "Precision Synthesis" and Synplicity's
"Synplify" product are probably the best-known.  Historically
these third-party tools have offered better language support
and better optimization than the free or cheap vendor-specific
tools, but many people have reported really excellent results
from ISE and Quartus recently so it may be that the gap is
closing.  These third-party tools may also offer big-project
features such as partitioning of a big design across multiple
FPGAs, although you probably expect to pay more for those
additional tricks.

Recently, Synopsys acquired Synplicity.  That's interesting.

So, it's quite a complicated picture...
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 135181
Subject: Re: Help~ How to develope with FPGA board?
From: "Tony Burch" <tony@burched.com.au>
Date: Sat, 20 Sep 2008 01:01:10 +1000
Links: << >>  << T >>  << A >>

"KJ" <lkjrsy@gmail.com> wrote in message 
news:8f945df8-f4b2-4ed7-9fe8-b991348eb1f7@z11g2000prl.googlegroups.com...
> Hello everyone.
>
> I'm a very beginner wiht FPGA board like following.
> http://hitechglobal.com/catalog/product_info.php?cPath=1&products_id=199
>
> This board contains Virtex5 FXT. I think that I need a ISE 10.1 to
> support it.
> Following is what I'm think of the development procedure.
>
> (1) Make VHDL codes for Virtex5 FXT in ISE 10.1 (?)
> (2) Synthesis/Translate/Palce&Part and Simulation
> (3) Download bitstream into the Chip (?)
> (4) Testing
>
> In (1), someone told me that I don't need ISE and usually if I
> purchase the FPGA board, software comes along with that. is this
> right?
>
> In (3), How to configure the chip? I have never done this before.
> Could you explanin the procedure of configuration?
>                                                 This board has the
> flash memory for FPGA configuration and storage.
>                                                  But, I don't know
> how to use it.

Hi KJ,

Since you are just getting started, perhaps you could have a look at some of 
the videos at http://www.burched.com

Click on Free_Videos to see the first 6 (very informative) and then it's 
less than $20 to view more.

Best regards,
Tony Burch




Article: 135182
Subject: Re: What software do use big organizations for Logic Synthesis from HDL?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 19 Sep 2008 16:12:06 +0100
Links: << >>  << T >>  << A >>

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:88e7d4lvorohjdnkbrf3j91khq520fm250@4ax.com...
> On Fri, 19 Sep 2008 04:06:51 -0700 (PDT), "psihodelia@googlemail.com"
> <psihodelia@googlemail.com> wrote:
>
..snip
>
> Recently, Synopsys acquired Synplicity.  That's interesting.

Or perhaps worrying...

According to a statement by Aart de Geus they purchased Synplicity for the 
Hardi line:

"Because we are stressing the systems, embedded software and related 
sectors. We acquired Virtio Corp of the US in August 2006, picking up its 
Innovator software for virtual hardware prototyping. We acquired Synplicity 
for its HAPS, which is the FPGA board for hardware prototyping. Now we can 
provide software developers with both software and hardware prototyping 
methods."

http://techon.nikkeibp.co.jp/article/HONSHI/20080826/156958/

Lets hope Synplify is not going the same way as FPGA Express/FPGA 
Compiler/DC-FPGA......

Hans
www.ht-lab.com



Article: 135183
Subject: Re: Help~ How to develope with FPGA board?
From: "Krzysztof Kepa" <blondikkPLACEHOLDER@pocztaPLACEHOLDER.fm>
Date: Fri, 19 Sep 2008 17:14:12 +0100
Links: << >>  << T >>  << A >>

"Tony Burch" <tony@burched.com.au> wrote in message 
news:48d3beb4$0$4451$afc38c87@news.optusnet.com.au...
>
> Since you are just getting started, perhaps you could have a look at some 
> of the videos at http://www.burched.com
>
KJ,

You could also have a look at online course at http://www.appliedvhdl.com.

It contains number of free videos and design templates. Also the virtual 
FPGA lab facility is on the way...

Topics covered:

Module 1: VHDL capture to hardware (basic combinational logic system)
1.1 > Introduction, Hardware Demonstration, Project Files  11 mins
1.2 > Invoking ISE tools, creating ISE Project, Viewing RTL and Technology 
Schematic  11 mins
1.3 > VHDL Testbench creation and VHDL Simulation. Creation of simulator 
macro files.
         Viewing Placed & Routed Design  11 mins
1.4 > Structural VHDL  6 mins
1.5 > Top (FPGA) Level VHDL Simulation  10 mins
1.6 > VHDL Synthesis & FPGA H/W Implementation. Viewing P&R Design in FPGA.


Module 2: VHDL capture to hardware for synchronous (register-based) system
2.1 > VHDL Capture to Hardware Implementation for synchronous / 
register-based systems  4 mins
2.2 > Register-based system block diagram. Project files. Xilnx ISE Project 
creation  4 mins
2.3 > D Flip Flop VHDL Model. Synthesising VHDL and Viewing RTL Schematic. 
7 mins
2.4 > DFF VHDL testbench and simulation  8 mins
2.5 > FPGA Top level VHDL model. FPGA Top level simulation / VHDL testbench 
11 mins
2.6 > FPGA Implementation, FPGA pinout, generating FPGA configuration 
bitstream.  10 mins
2.7 > VHDL coding recommendations

Module 3: VHDL for 'above gate-level' combinational model description
3.1 > Introduction, Overview of application, overview of laboratory files  6 
mins
3.2 > Multiplexer function, Entity declaration, MUX using if-then-else, VHDL 
and concurrency  8 mins
3.3 > if-then-else statement syntax, inferring latches (often incorrectly) 
and flip flops  6 mins
3.4 > Mux using Case & Concurrent statements  7 mins
3.5 > Simulation of muxAndDecEx1, sensitivity list rules, top level VHDL 
models and simulation  8 mins
3.6 > FPGA hardware implementation and demonstration of hardware operation 
4 mins

Module 4: VHDL for efficient testbenches
4.1 > Applying TB stimulus using: For Loop, Stimulus Array, Text Stimulus 
File

Regards,
Krzysztof 



Article: 135184
Subject: Peter says Good Bye
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 19 Sep 2008 09:54:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
After 13 years and >2000 postings I will retire from comp.arch.fpga.
I think I have helped some, informed many, and irritated only a few.
It has been a significant part of my life, and I will miss it. (But I
will keep lurking from home).
Xilinx asked me to organize the user documentation for the next
generations of Virtex and Spartan devices.
That keeps me real busy, and I hope you will appreciate the results in
due course.
Cheers, Good-Bye und Auf Wiedersehen !
Peter Alfke

Article: 135185
Subject: Re: Xilinx Spartan E
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 19 Sep 2008 10:37:09 -0700
Links: << >>  << T >>  << A >>
Thanks John.



Article: 135186
Subject: Synplify Pro derived clock going out as port
From: "surendar" <surendar1983@yahoo.com>
Date: Fri, 19 Sep 2008 13:18:43 -0500
Links: << >>  << T >>  << A >>
Hello,

I have 2 questions

1)
Input port clock is devided and used in the internal logic as well it is
going out as a port clock.

What would be SDC syntax for synplify pro?

I tried following, but div2 clock not going to some internal logic,
instead its using the original clock.

"define_clock -name {n:div2clk} -period 20 -clockgroup originalclock"
also tried :
"define_clock -name {n:div2clk} -period 20 -clockgroup div2clock"

2) there is another clock div4
and div2, div4 are multiplexed and one clock goes out.

How should I constrain them and what's their clockgroup?

Any suggestions please..



Article: 135187
Subject: Re: Peter says Good Bye
From: Antonio Pasini <removethis_antonio.pasini@alice.it>
Date: Fri, 19 Sep 2008 21:50:48 +0200
Links: << >>  << T >>  << A >>
Il 19/09/2008 18.54, Peter Alfke ha scritto:
> After 13 years and >2000 postings I will retire from comp.arch.fpga.
> I think I have helped some, informed many, and irritated only a few.
> It has been a significant part of my life, and I will miss it. (But I
> will keep lurking from home).
> Xilinx asked me to organize the user documentation for the next
> generations of Virtex and Spartan devices.
> That keeps me real busy, and I hope you will appreciate the results in
> due course.
> Cheers, Good-Bye und Auf Wiedersehen !
> Peter Alfke

Bye, Peter!

Thanks a lot for your contribution to this group.

In the past years, I always found your posts informative and helpful.

I see Xilinx withdrawing from this group. It's a big mistake.

Yes, you helped many of us!

At least, you helped me taking a decision, nine years ago (wow.. time 
goes so fast...)

If it wasn't for the Xilinx presence on this group (and that means you, 
Austin, and some others), being a totally newbie considering A vs. X, I 
would't have choosen Xilinx at the time.

I didn't know enough to choose wisely about silicon; instead, I found 
Xilinx presence here so much helpful to make the company look more 
"easy" to talk with than A. That had a big influence on decision.

No money spent on advertising, seminars, or whatever will ever come near 
to the feeling I had at the time, seeing someone writing here with a 
@xilinx account. Period.

Yes, I registered on Xilinx web forums. No, it's not the same thing. 
Never will, not at all.

Here I come mainly to relax for fun and pleasure after work, also.
And to learn, having fun in the process.

There, I go when I have a precise problem, searching for a solution, 
quickly.

But I know you know this, and I suppose and hope this is your decision.

But I have a feeling that the new Xilinx "course" is *so* much worse 
than before. At least, my feeling about the company changed drastically 
during the last months, from many little signals.

It's a real pity.

Good luck to your next job!









Article: 135188
Subject: Re: Peter says Good Bye
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 19 Sep 2008 12:55:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Peter,

Your time on this forum has been greatly appreciated.

May your travels bring you great joy and the work you produce bring
greater success to those of us who rely on good documentation and, in
turn, to Xilinx as well.

Your participation will be missed!

A great deal of respect and regards,
- John Handwork

Article: 135189
Subject: WebPack on CentOS 5 ?
From: Jon Elson <jmelson@wustl.edu>
Date: Fri, 19 Sep 2008 15:34:19 -0500
Links: << >>  << T >>  << A >>
Hello, all,

I just set up a new system with CentOS 5 (based on Red Hat Enterprise 
Linux) and tried to install WebPack 10.1 on it.  It says :

Product is not supported on "Linux x86_64" platform.

But, I'm PRETTY sure this is NOT a 64-bit system.  The /proc/version 
output reads :

Linux version 2.6.18-92.1.10.el5 (mockbuild@builder10.centos.org) (gcc 
version 4.1.2 20071124 (Red Hat 4.1.2-42)) #1
  SMP Tue Aug 5 07:42:41 EDT 2008

That looks pretty much like a 32-bit CPU to me.  The CPUs read out as :

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 23
model name      : Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz
stepping        : 6

Any ideas?  Is WebPack totally restricted to just a couple OS versions?
(we have a Xilinx educational license available here, but it apparently 
involves a LOT of paperwork, so they wanted me to try WebPack first and 
see if that would work for me.)

Thanks for any info.

Jon

Article: 135190
Subject: Is it hard to detect an ucf sytax error?
From: Marlboro <ccon67@netscape.net>
Date: Fri, 19 Sep 2008 13:48:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
Remember back in the old days, the Xlnx sw can detect your ucf syntax
error almost immediately and point out which error whih c line.. blah
blah..

But in the 10.1 (dont know what happened to the others), it take like
10 minnutes or so to do some blah blah translate then it ends up to
tell that your ucf got a problem.  Then you have fix the ucf file then
re-run everything.. then take another 10 minutes to find out your ucf
has another syntax error, what's the progress here?

Article: 135191
Subject: Re: WebPack on CentOS 5 ?
From: Andy Botterill <andy@plymouth2.demon.co.uk>
Date: Fri, 19 Sep 2008 21:51:19 +0100
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> Hello, all,
> 
> I just set up a new system with CentOS 5 (based on Red Hat Enterprise 
> Linux) and tried to install WebPack 10.1 on it.  It says :
> 
> Product is not supported on "Linux x86_64" platform.

I have webpack 10.1 and have recently moved to 10.1.02 on fedora 8 64 
bit system (x86_64). Synthesis is OK. My design is quite small so am not 
pushing the software much.

I'm not sure if licenses prevent installation or only execution?
> 
> But, I'm PRETTY sure this is NOT a 64-bit system.  The /proc/version 
> output reads :
> 
> Linux version 2.6.18-92.1.10.el5 (mockbuild@builder10.centos.org) (gcc 
> version 4.1.2 20071124 (Red Hat 4.1.2-42)) #1
>  SMP Tue Aug 5 07:42:41 EDT 2008
> 
> That looks pretty much like a 32-bit CPU to me.  The CPUs read out as :
> 
> processor       : 0
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 23
> model name      : Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz
> stepping        : 6
> 
> Any ideas?  Is WebPack totally restricted to just a couple OS versions?
> (we have a Xilinx educational license available here, but it apparently 
> involves a LOT of paperwork, so they wanted me to try WebPack first and 
> see if that would work for me.)
> 
> Thanks for any info.
> 
> Jon

Article: 135192
Subject: Re: Synplify Pro derived clock going out as port
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Fri, 19 Sep 2008 15:02:09 -0600
Links: << >>  << T >>  << A >>
surendar wrote:
> Hello,
> 
> I have 2 questions
> 
> 1)
> Input port clock is devided and used in the internal logic as well it is
> going out as a port clock.
> 
> What would be SDC syntax for synplify pro?
> 
> I tried following, but div2 clock not going to some internal logic,
> instead its using the original clock.
> 
> "define_clock -name {n:div2clk} -period 20 -clockgroup originalclock"
> also tried :
> "define_clock -name {n:div2clk} -period 20 -clockgroup div2clock"
> 
> 2) there is another clock div4
> and div2, div4 are multiplexed and one clock goes out.
> 
> How should I constrain them and what's their clockgroup?
> 
> Any suggestions please..
> 
> 
I don't understand why the output clocks need any constraint.  To 
Synplify, that clock net does not drive anything, so no constraint 
should be needed.

PS if you are outputting a source-synchronous clock, you should use a 
DDR register to make a clock mirror.
-Kevin

Article: 135193
Subject: Re: Peter says Good Bye
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Fri, 19 Sep 2008 15:06:20 -0600
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> After 13 years and >2000 postings I will retire from comp.arch.fpga.
> I think I have helped some, informed many, and irritated only a few.
> It has been a significant part of my life, and I will miss it. (But I
> will keep lurking from home).
> Xilinx asked me to organize the user documentation for the next
> generations of Virtex and Spartan devices.
> That keeps me real busy, and I hope you will appreciate the results in
> due course.
> Cheers, Good-Bye und Auf Wiedersehen !
> Peter Alfke

Das ist ja schade.  I hope Xilinx continues its sanctioned participation 
in some degree.  This is an important forum.  With my workmates being 
distributed ever more remotely, this is a primary source of advice for me.
-Kevin

Article: 135194
Subject: Re: Peter says Good Bye
From: "Steve Knapp" <steveD.O.TknappA.Tprevailing-technologyD.O.Tcom>
Date: Fri, 19 Sep 2008 14:36:07 -0700
Links: << >>  << T >>  << A >>
Hi Peter,

I'm sure that I speak for most comp.arch.fpga readers in saying that you 
will be greatly missed!  Your postings and contributions are always helpful 
and informative.  Thank you also for all the help you provided outside of 
comp.arch.fpga via direct E-mail and for always being a champion for Xilinx 
users (and even occasionally for the other vendors as well).  Although you 
aren't officially a Field Application Engineer, I can safely say that you've 
been responsible for a good number of Xilinx design wins.

Best of luck in the new role.  I look forward to seeing the next generation 
Virtex, Spartan, and documentation.

===============================================
Steven K. Knapp
Prevailing Technology, Inc.
Web:  www.prevailing-technology.com


Article: 135195
Subject: Re: LED lights flashing while LCD shows chars, Spartan-3A
From: "Steve Knapp" <steveD.O.TknappA.Tprevailing-technologyD.O.Tcom>
Date: Fri, 19 Sep 2008 14:51:25 -0700
Links: << >>  << T >>  << A >>
> My question is:
> Do you know where can I find information that tells, for example, what
> means an  'on'  LED0 and/or LED3, from time to time, while the LCD is
> showing the characters?

I looked at the Spartan-3A Starter Kit board schematic, but it does not 
appear that the character LCD pins are shared with the LEDs.
http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf

Do you have other outputs in the design?  Are those output pins defined a 
LOCation in the UCF file?  It could be that output pins with an unassigned 
pin location are landing on the LED pins.

===============================================
Steven K. Knapp
Prevailing Technology, Inc.
Web:  www.prevailing-technology.com 


Article: 135196
Subject: Re: WebPack on CentOS 5 ?
From: General Schvantzkopf <schvantzkopf@yahoo.com>
Date: Fri, 19 Sep 2008 17:31:31 -0500
Links: << >>  << T >>  << A >>
On Fri, 19 Sep 2008 15:34:19 -0500, Jon Elson wrote:

> Hello, all,
> 
> I just set up a new system with CentOS 5 (based on Red Hat Enterprise
> Linux) and tried to install WebPack 10.1 on it.  It says :
> 
> Product is not supported on "Linux x86_64" platform.
> 
> But, I'm PRETTY sure this is NOT a 64-bit system.  The /proc/version
> output reads :
> 
> Linux version 2.6.18-92.1.10.el5 (mockbuild@builder10.centos.org) (gcc
> version 4.1.2 20071124 (Red Hat 4.1.2-42)) #1
>   SMP Tue Aug 5 07:42:41 EDT 2008
> 
> That looks pretty much like a 32-bit CPU to me.  The CPUs read out as :
> 
> processor       : 0
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 23
> model name      : Intel(R) Core(TM)2 Duo CPU     E8500  @ 3.16GHz
> stepping        : 6
> 
> Any ideas?  Is WebPack totally restricted to just a couple OS versions?
> (we have a Xilinx educational license available here, but it apparently
> involves a LOT of paperwork, so they wanted me to try WebPack first and
> see if that would work for me.)
> 
> Thanks for any info.
> 
> Jon

Do a uname -a, that will tell you if it's running 64 bits CentOS5. The 
hardware is definitely 64 bit. If you are running 64 CentOS you can always 
put a 32 bit VM on it to install the tools. The 32 bit tools should be 
able to run natively on 64 bit CentOS, it's just the installer that's 
complaining. BYW make sure that you have Motif and the compat libraries 
installed.


Article: 135197
Subject: Re: Clock Enable safe?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 19 Sep 2008 15:00:00 -0800
Links: << >>  << T >>  << A >>
KJ wrote:
(snip)

> You won't rid yourself of metastability by adding another flop, but
> you will be greatly reducing the probability by adding another flop,
> at the cost of added latency (maybe that's important, maybe not).  You
> could greatly reduce the probability of metastability even more by
> adding two, three, four....

Metastability is exponential.  You never get rid of it,
but can reduce it to extremely low probability.

> Also, the clock rate is important.  Metastability takes some amount of
> time to resolve, it doesn't matter if that time comes from adding
> flops to a shift chain or simply a slower clock.  A single flop that
> is clocked at 10 MHz will be more immune to having something bad
> happen due to metastability than a two flop shift chain running at 100
> MHz.  In the former case one clock cycle is 100 ns, in the second it
> is only 10 ns.

In a good design, the propagation delay through some parts
of the logic will be a reasonable fraction, maybe 80%,
of the clock cycle.  (Including skew, and anything else
reasonably predictable.)   If for a 100MHz clock that
gave a metastability event every minute, (every
6000000000 clock cycles)

If the clock frequency was reduced, such that the clock
cycle was 20% longer the resolution time would double
and the effect would be seen every (6000000000)**2
clock cycles, or about once in 11415 years.

If you have a second FF with minimal delay, the
resolution time is five times that available
when propagation delay takes 80% of the time,
decreases the probability to once in
(6000000000)**5 clock cycles, or about one
in 2e33 years.  That should be lone enough
for most of us.

> Traditionally, most folks bring in async signals into a 2 flop shift
> chain and use the output of that as the synchronous version of that
> async signal so adding the second flop as previously suggested is good
> enough, but you should take a moment to scan a paper or two about just
> what causes metastability in the first place to educate yourself so
> you'll know the tradeoffs.

People are not very good at getting the feel of exponentials,
even scientists.  There was a recent Dilbert cartoon where
someone attends a seminar on how to turn $100 into $1,000,000.
Sounds too good to be true, but the answer is to put it
in the bank at 10% interest (well, not so easy right now)
for about 97 years.  How many know that 1.1**97 is more
than 10,000 without a calculator?  (I didn't.)

-- glen


Article: 135198
Subject: Re: interview questions ........
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 19 Sep 2008 15:22:26 -0800
Links: << >>  << T >>  << A >>
ekavirsrikanth@gmail.com wrote:

> 1. I have a not gate of TTL logic it has 20ns delay to the input i
> have given the square wave of 5nsec what will be the output. will the
> output be the square wave since the delayof the logic is more than the
> freq of operation doe the not gate work? and if it works upto what
> freq i can work...... for the same question what will be the output if
> the input is a sine wave instead of square wave.

The delay is related to various RC time constants inside
the gate and the output load.  The amplitude at the output
will be greatly reduced at higher frequencies, but might still
be visible on a scope.

(I once knew someone who built an FM transmitter with a
74S04 as the final output driver. Pretty much an analog
device at 100MHz.)

> 2. max how many fanouts can we have for 2 input and gate. On what
> factors the fanout of a design depends. I think it depends on the
> voltage the output is driving.

Usually the size of the output transistors.

> 3. for a single Dff (with D as input and Q as outpu and Clk as clock
> in) what will be the max Freqency it can operate.... i feel the min
> Time period req is only the tC-Q dealy (Propagation delay of the FF no
> need to consider the Tsetup time as only One FF is available for Time
> calculation).

Setup time is important.  If you connect Qbar to D such
that it will toggle every cycle you can see that setup
time and hold time are important.

-- glen


Article: 135199
Subject: Re: Peter says Good Bye
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Sat, 20 Sep 2008 00:38:00 +0100
Links: << >>  << T >>  << A >>
On Fri, 19 Sep 2008 09:54:27 -0700 (PDT), Peter Alfke <peter@xilinx.com>
wrote:

>After 13 years and >2000 postings I will retire from comp.arch.fpga.
>I think I have helped some, informed many, and irritated only a few.
>It has been a significant part of my life, and I will miss it. (But I
>will keep lurking from home).

You'll be missed. Thanks for the help and advice you have given over the
years.

- Brian



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