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Threads Starting Dec 2008
136686: 08/12/01: ikki: what is the difference between post-synthesis simulation and timing simulation?
136687: 08/11/30: Thomas Stanka: Re: what is the difference between post-synthesis simulation and
136691: 08/12/01: denish: using memory of spartan 3sd1800a dsp fpga
136698: 08/12/02: <ales.gorkic@gmail.com>: Re: using memory of spartan 3sd1800a dsp fpga
136696: 08/12/01: John: Use Chipscope libCseJtag.dll
136740: 08/12/03: John: Re: Use Chipscope libCseJtag.dll
136697: 08/12/02: <uraniumore238@gmail.com>: reading registers
136699: 08/12/02: Per: Re: reading registers
136714: 08/12/02: Hal Murray: Re: reading registers
136702: 08/12/02: Sean Durkin: Re: reading registers
136705: 08/12/02: Gabor: Re: reading registers
136713: 08/12/02: John_H: Re: reading registers
136704: 08/12/02: papppanas: how to read images from a microSD card ?
136707: 08/12/02: H. Peter Anvin: Re: how to read images from a microSD card ?
136708: 08/12/02: papppanas: Re: how to read images from a microSD card ?
136709: 08/12/02: papppanas: Re: how to read images from a microSD card ?
136711: 08/12/02: Mike Treseler: Re: how to read images from a microSD card ?
136712: 08/12/02: John_H: Re: how to read images from a microSD card ?
136715: 08/12/02: H. Peter Anvin: Re: how to read images from a microSD card ?
136721: 08/12/03: papppanas: Re: how to read images from a microSD card ?
136706: 08/12/02: bjzhangwn@gmail.com: problem about V5 PCI Express endpoint
136710: 08/12/02: Mike Treseler: Re: problem about V5 PCI Express endpoint
136717: 08/12/02: bjzhangwn@gmail.com: Re: problem about V5 PCI Express endpoint
136716: 08/12/02: <reganireland@gmail.com>: CameraLink Deserilization and Module Constraint Files
136733: 08/12/03: Martin Thompson: Re: CameraLink Deserilization and Module Constraint Files
136741: 08/12/03: Gabor: Re: CameraLink Deserilization and Module Constraint Files
136748: 08/12/03: <reganireland@gmail.com>: Re: CameraLink Deserilization and Module Constraint Files
136718: 08/12/02: <carl.horton08@gmail.com>: Hold Time Requirement
136719: 08/12/03: backhus: Re: Hold Time Requirement
136722: 08/12/03: Hal Murray: Re: Hold Time Requirement
136720: 08/12/02: Muzaffer Kal: Re: Hold Time Requirement
136770: 08/12/04: Hal Murray: Re: Hold Time Requirement
136742: 08/12/03: Gabor: Re: Hold Time Requirement
136760: 08/12/04: <carl.horton08@gmail.com>: Re: Hold Time Requirement
136724: 08/12/03: Josip: Dynamical alteration of signal path
136725: 08/12/03: Uwe Bonnes: Re: Dynamical alteration of signal path
136730: 08/12/03: Josip: Re: Dynamical alteration of signal path
136739: 08/12/03: Hal Murray: Re: Dynamical alteration of signal path
136726: 08/12/03: Glen Herrmannsfeldt: Re: Dynamical alteration of signal path
136731: 08/12/03: Josip: Re: Dynamical alteration of signal path
136788: 08/12/05: Josip: Re: Dynamical alteration of signal path
136727: 08/12/03: Jonathan Bromley: Re: Dynamical alteration of signal path
136728: 08/12/03: Josip: Re: Dynamical alteration of signal path
136732: 08/12/03: Jonathan Bromley: Re: Dynamical alteration of signal path
136735: 08/12/03: Brian Drummond: Re: Dynamical alteration of signal path
136729: 08/12/03: <giorgos.puiklis@gmail.com>: Back-annotated simulation for Xilinx devices
136736: 08/12/03: Brian Drummond: Re: Back-annotated simulation for Xilinx devices
136737: 08/12/03: Amal: VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x
136743: 08/12/03: H. Peter Anvin: Relationship between high and low speed clocks
136744: 08/12/03: Jonathan Bromley: Re: Relationship between high and low speed clocks
136747: 08/12/03: H. Peter Anvin: Re: Relationship between high and low speed clocks
136745: 08/12/03: KJ: Re: Relationship between high and low speed clocks
136750: 08/12/03: KJ: Re: Relationship between high and low speed clocks
136746: 08/12/03: Hal Murray: Re: Relationship between high and low speed clocks
136751: 08/12/03: KJ: Re: Relationship between high and low speed clocks
136752: 08/12/03: H. Peter Anvin: Re: Relationship between high and low speed clocks
136755: 08/12/03: Hal Murray: Re: Relationship between high and low speed clocks
136756: 08/12/04: H. Peter Anvin: Re: Relationship between high and low speed clocks
136769: 08/12/04: Hal Murray: Re: Relationship between high and low speed clocks
136771: 08/12/04: H. Peter Anvin: Re: Relationship between high and low speed clocks
136749: 08/12/03: KJ: Re: Relationship between high and low speed clocks
136753: 08/12/04: Symon: Re: Relationship between high and low speed clocks
136754: 08/12/03: Venkat: Query on Xilinx Nomenclature
136757: 08/12/04: Jonathan Bromley: Re: Query on Xilinx Nomenclature
136767: 08/12/04: Prevailing over Technology: Re: Query on Xilinx Nomenclature
136777: 08/12/04: Jon Elson: Re: Query on Xilinx Nomenclature
136798: 08/12/05: Jon Elson: Re: Query on Xilinx Nomenclature
136780: 08/12/04: Venkat: Re: Query on Xilinx Nomenclature
136758: 08/12/04: ALuPin@web.de: Timing analysis of related clocks
136762: 08/12/04: KJ: Re: Timing analysis of related clocks
136763: 08/12/04: Gabor: Re: Timing analysis of related clocks
136764: 08/12/04: ALuPin@web.de: Re: Timing analysis of related clocks
136759: 08/12/04: Giorgos_P: Xilinx-ISE nets names after placement & routing
136765: 08/12/04: Mike Treseler: Re: Xilinx-ISE nets names after placement & routing
136778: 08/12/04: Mike Treseler: Re: Xilinx-ISE nets names after placement & routing
136774: 08/12/04: Giorgos_P: Re: Xilinx-ISE nets names after placement & routing
136787: 08/12/05: Enes Erdin: Re: Xilinx-ISE nets names after placement & routing
136793: 08/12/05: Giorgos_P: Re: Xilinx-ISE nets names after placement & routing
136761: 08/12/04: <carl.horton08@gmail.com>: Which terms include the setup time and hold time in Xilinx ISE timing
136766: 08/12/04: Sebastien Bourdeauducq: Preventing PAR from routing signals in closed area groups
136790: 08/12/05: Markus: Re: Preventing PAR from routing signals in closed area groups
136829: 08/12/08: Markus: Re: Preventing PAR from routing signals in closed area groups
136792: 08/12/05: Sebastien Bourdeauducq: Re: Preventing PAR from routing signals in closed area groups
136768: 08/12/04: Dale: Project/File corruption problem with ISE 10.1
136772: 08/12/04: Brad Smallridge: Re: Project/File corruption problem with ISE 10.1
136802: 08/12/06: Brian Drummond: Re: Project/File corruption problem with ISE 10.1
136773: 08/12/04: Gabor: Re: Project/File corruption problem with ISE 10.1
136794: 08/12/05: Bryan: Re: Project/File corruption problem with ISE 10.1
136775: 08/12/04: Aiken: Modelsim warning message
136813: 08/12/06: Jonathan Bromley: Re: Modelsim warning message
136776: 08/12/04: Poonam: PCI9656RDK from PLX Technologies
136779: 08/12/04: wasifgreen: Problems using minimal CPU design by Tim Boescke
136781: 08/12/04: Venkat: Equivalent ASIC Gate Estimate
136782: 08/12/04: Glen Herrmannsfeldt: Re: Equivalent ASIC Gate Estimate
136785: 08/12/05: Andreas Ehliar: Re: Equivalent ASIC Gate Estimate
136786: 08/12/05: Kim Enkovaara: Re: Equivalent ASIC Gate Estimate
136791: 08/12/05: Jon Beniston: Re: Equivalent ASIC Gate Estimate
136795: 08/12/05: beky4kr@gmail.com: Re: Equivalent ASIC Gate Estimate
136797: 08/12/05: LittleAlex: Re: Equivalent ASIC Gate Estimate
136826: 08/12/08: Andreas Ehliar: Re: Equivalent ASIC Gate Estimate
136825: 08/12/07: Venkat: Re: Equivalent ASIC Gate Estimate
136783: 08/12/04: <reganireland@gmail.com>: XAPP485 Equivalent for Spartan 3
136784: 08/12/04: <brimdavis@aol.com>: V5 JTAG download weirdness
136807: 08/12/05: <brimdavis@aol.com>: Re: V5 JTAG download weirdness
136815: 08/12/06: Gabor: Re: V5 JTAG download weirdness
136817: 08/12/06: <brimdavis@aol.com>: Re: V5 JTAG download weirdness
136789: 08/12/05: water9580@yahoo.com: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM controller)
136796: 08/12/05: LittleAlex: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
136800: 08/12/05: Gabor: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
136804: 08/12/05: water9580@yahoo.com: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
136799: 08/12/05: Amal: SystemVerilog OOP and OVM Summary
136801: 08/12/05: Mike Treseler: Re: SystemVerilog OOP and OVM Summary
136814: 08/12/06: cms: Re: SystemVerilog OOP and OVM Summary
136983: 08/12/17: vlsichipdesigner@gmail.com: Re: SystemVerilog OOP and OVM Summary
136803: 08/12/05: freespace@gmail.com: Invalid devices when initialising scan chain with Nexys2
136805: 08/12/05: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
136806: 08/12/05: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
136809: 08/12/06: Glen Herrmannsfeldt: Re: Invalid devices when initialising scan chain with Nexys2
136824: 08/12/07: Sean Durkin: Re: Invalid devices when initialising scan chain with Nexys2
136810: 08/12/06: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
136819: 08/12/07: Oscar: Re: Invalid devices when initialising scan chain with Nexys2
136830: 08/12/08: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
136831: 08/12/08: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
138006: 09/02/03: freespace@gmail.com: Re: Invalid devices when initialising scan chain with Nexys2
136808: 08/12/05: xilinx_user: How to save added signals to waveform viewer
136860: 08/12/09: lecroy7200@chek.com: Re: How to save added signals to waveform viewer
136812: 08/12/06: simax: Xiic with low lvl interrupts
136836: 08/12/08: Bryan: Re: Xiic with low lvl interrupts
136818: 08/12/07: Nemesis: ISE doesn't work after a crash
136820: 08/12/07: Mike Treseler: Re: ISE doesn't work after a crash
136821: 08/12/07: Nemesis: Re: ISE doesn't work after a crash
136823: 08/12/07: Mike Treseler: Re: ISE doesn't work after a crash
136834: 08/12/08: Nemesis: Re: ISE doesn't work after a crash
136837: 08/12/08: Mike Treseler: Re: ISE doesn't work after a crash
136840: 08/12/08: Nemesis: Re: ISE doesn't work after a crash
136839: 08/12/08: Nemesis: Re: ISE doesn't work after a crash
136822: 08/12/07: <no_spa2005@yahoo.fr>: Re: ISE doesn't work after a crash
136838: 08/12/08: Andy Peters: Re: ISE doesn't work after a crash
136841: 08/12/08: Gabor: Re: ISE doesn't work after a crash
136846: 08/12/08: lecroy7200@chek.com: Re: ISE doesn't work after a crash
136848: 08/12/08: Gabor: Re: ISE doesn't work after a crash
136853: 08/12/08: Nemesis: Re: ISE doesn't work after a crash
136854: 08/12/09: Nemesis: Re: ISE doesn't work after a crash
136827: 08/12/07: NRClark: Inverting bus connection order in Verilog
136828: 08/12/07: H. Peter Anvin: Re: Inverting bus connection order in Verilog
136832: 08/12/08: Jonathan Bromley: Re: Inverting bus connection order in Verilog
136855: 08/12/09: Jonathan Bromley: Re: Inverting bus connection order in Verilog
136859: 08/12/09: Markus: Re: Inverting bus connection order in Verilog
136842: 08/12/08: Gabor: Re: Inverting bus connection order in Verilog
136858: 08/12/09: KJ: Re: Inverting bus connection order in Verilog
136833: 08/12/08: <xiaoling.li@fme.fujitsu.com>: encrypted and unencrypted design in the same device
136835: 08/12/08: Krzysztof Kepa: Re: encrypted and unencrypted design in the same device
136903: 08/12/11: <karthick.ramu@gmail.com>: Re: encrypted and unencrypted design in the same device
136905: 08/12/11: Eric Smith: Re: encrypted and unencrypted design in the same device
136843: 08/12/08: Digi Suji: Xilinx UNISIM/SIMPRIM libraries
136844: 08/12/08: Gabor: Re: Xilinx UNISIM/SIMPRIM libraries
136863: 08/12/09: Digi Suji: Re: Xilinx UNISIM/SIMPRIM libraries
136865: 08/12/09: Gabor: Re: Xilinx UNISIM/SIMPRIM libraries
136845: 08/12/08: <benwang08@gmail.com>: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136856: 08/12/09: <fredrik_he_lang@hotmail.com>: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136857: 08/12/09: <fredrik_he_lang@hotmail.com>: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136862: 08/12/09: Barry: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136864: 08/12/09: <benwang08@gmail.com>: Re: Can DDR2 work with Xilinx Virtex-5 at 400 MHz?
136849: 08/12/08: Venkat: FPGA-ASIC Migration
136850: 08/12/08: H. Peter Anvin: Re: FPGA-ASIC Migration
136851: 08/12/08: <kal@dspia.com>: Re: FPGA-ASIC Migration
136852: 08/12/09: Kim Enkovaara: Re: FPGA-ASIC Migration
136861: 08/12/09: Mike Treseler: Re: FPGA-ASIC Migration
136866: 08/12/09: Rob: Sampling a clock
136867: 08/12/09: KJ: Re: Sampling a clock
136868: 08/12/09: Rob: Re: Sampling a clock
136869: 08/12/10: Stef: Re: Sampling a clock
136870: 08/12/10: Per: Re: Sampling a clock
136880: 08/12/10: doug: Re: Sampling a clock
136883: 08/12/10: doug: Re: Sampling a clock
136886: 08/12/10: Rob: Re: Sampling a clock
136873: 08/12/10: Mike Treseler: Re: Sampling a clock
136871: 08/12/10: KJ: Re: Sampling a clock
136874: 08/12/10: Rob: Re: Sampling a clock
136876: 08/12/10: KJ: Re: Sampling a clock
136878: 08/12/10: Rob: Re: Sampling a clock
136879: 08/12/10: <bsp0524@gmail.com>: Re: Sampling a clock
136881: 08/12/10: Rob: Re: Sampling a clock
136896: 08/12/11: colin: Re: Sampling a clock
136897: 08/12/11: KJ: Re: Sampling a clock
136875: 08/12/10: <ooze3d@gmail.com>: Looking for FPGA engineer for HD camera project
136877: 08/12/10: LittleAlex: Re: Looking for FPGA engineer for HD camera project
136884: 08/12/10: <ooze3d@gmail.com>: Re: Looking for FPGA engineer for HD camera project
136941: 08/12/15: Finn S. Nielsen: Re: Looking for FPGA engineer for HD camera project
136942: 08/12/15: kadhiem_ayob: Re: Looking for FPGA engineer for HD camera project
136882: 08/12/10: <google@schwarzers.de>: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
136888: 08/12/11: Matthias Alles: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
136895: 08/12/11: hardbreaker: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
136908: 08/12/12: <ales.gorkic@gmail.com>: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
136885: 08/12/10: mpthompson: Adding 128Kx8 SRAM to Spartan 3E FPGA
136890: 08/12/11: <ales.gorkic@gmail.com>: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136891: 08/12/11: <ales.gorkic@gmail.com>: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136893: 08/12/11: Brian Drummond: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136899: 08/12/11: Bryan: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136900: 08/12/11: mpthompson: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
136887: 08/12/10: Ben D: mapping to custom architecture
136889: 08/12/11: Andreas Ehliar: Re: mapping to custom architecture
136904: 08/12/11: Brian Drummond: Re: mapping to custom architecture
136894: 08/12/11: Brian Drummond: Re: mapping to custom architecture
136906: 08/12/11: Ben D: Re: mapping to custom architecture
136892: 08/12/11: Andreas Ehliar: Doubt about the maximum speed of FPGA clock nets
136915: 08/12/12: lecroy7200@chek.com: Re: Doubt about the maximum speed of FPGA clock nets
136917: 08/12/13: Prevailing over Technology: Re: Doubt about the maximum speed of FPGA clock nets
136923: 08/12/14: Nico Coesel: Re: Doubt about the maximum speed of FPGA clock nets
136925: 08/12/14: Andreas Ehliar: Re: Doubt about the maximum speed of FPGA clock nets
136898: 08/12/11: Marlboro: How to insert ChipScope
136901: 08/12/11: Gabor: Re: How to insert ChipScope
136907: 08/12/12: Markus: Re: How to insert ChipScope
136902: 08/12/11: Jan: Re: How to insert ChipScope
136909: 08/12/12: <ales.gorkic@gmail.com>: Re: How to insert ChipScope
136912: 08/12/12: Mike Treseler: Re: How to insert ChipScope
136911: 08/12/12: Gael Paul: Re: How to insert ChipScope
136910: 08/12/12: taco: dsp boards with multiple AD channels question
136914: 08/12/12: Al Clark: Re: dsp boards with multiple AD channels question
136919: 08/12/13: John Adair: Re: dsp boards with multiple AD channels question
136913: 08/12/12: raph: BUFGMUX placement
136950: 08/12/15: Symon: Re: BUFGMUX placement
136989: 08/12/17: Symon: Re: BUFGMUX placement
136952: 08/12/15: Gael Paul: Re: BUFGMUX placement
136957: 08/12/15: raph: Re: BUFGMUX placement
136965: 08/12/16: <ales.gorkic@gmail.com>: Re: BUFGMUX placement
137012: 08/12/18: raph: Re: BUFGMUX placement
136916: 08/12/13: Nadav Rotem: Online C-to-FPGA tool
136918: 08/12/13: Thomas Stanka: Re: Online C-to-FPGA tool
136921: 08/12/13: laserbeak43: Re: Online C-to-FPGA tool
136922: 08/12/13: Nadav Rotem: Re: Online C-to-FPGA tool
136920: 08/12/13: Roger: WebPACK installation
136924: 08/12/13: googler: new to FPGA
136926: 08/12/14: rickman: Re: new to FPGA
136927: 08/12/14: John Adair: Re: new to FPGA
136928: 08/12/14: <secureasm@gmail.com>: FIFO with External Memory
136929: 08/12/14: Peter Alfke: Re: FIFO with External Memory
136933: 08/12/14: Hal Murray: Re: FIFO with External Memory
136935: 08/12/14: Hal Murray: Re: FIFO with External Memory
136932: 08/12/14: Gabor: Re: FIFO with External Memory
136934: 08/12/14: Peter Alfke: Re: FIFO with External Memory
136940: 08/12/15: <secureasm@gmail.com>: Re: FIFO with External Memory
136930: 08/12/14: GrIsH: i2c interface
136931: 08/12/14: Gabor: Re: i2c interface
136936: 08/12/14: Brad Smallridge: Re: i2c interface
136975: 08/12/16: Brad Smallridge: Re: i2c interface
136955: 08/12/15: GrIsH: Re: i2c interface
136956: 08/12/15: GrIsH: Re: i2c interface
136958: 08/12/16: KJ: Re: i2c interface
136960: 08/12/15: GrIsH: Re: i2c interface
136970: 08/12/16: bish: Re: i2c interface
136972: 08/12/16: KJ: Re: i2c interface
136973: 08/12/16: KJ: Re: i2c interface
136978: 08/12/16: KJ: Re: i2c interface
136979: 08/12/16: KJ: Re: i2c interface
136937: 08/12/14: <sreenivas.jyothi@gmail.com>: Duty Cycle change effects on Internal reg's
136938: 08/12/14: Peter Alfke: Re: Duty Cycle change effects on Internal reg's
137448: 09/01/17: glen herrmannsfeldt: Re: Duty Cycle change effects on Internal reg's
137416: 09/01/14: <sreenivas.jyothi@gmail.com>: Re: Duty Cycle change effects on Internal reg's
137430: 09/01/15: Peter Alfke: Re: Duty Cycle change effects on Internal reg's
137443: 09/01/16: Gabor: Re: Duty Cycle change effects on Internal reg's
137446: 09/01/16: Peter Alfke: Re: Duty Cycle change effects on Internal reg's
136939: 08/12/14: <sreenivas.jyothi@gmail.com>: clock reducing leads what
136982: 08/12/16: Thomas Stanka: Re: clock reducing leads what
136943: 08/12/15: dajjou: JTAG / IMPACT / VIRTEX
136945: 08/12/15: Jan Bruns: Re: JTAG / IMPACT / VIRTEX
136948: 08/12/15: Uwe Bonnes: Re: JTAG / IMPACT / VIRTEX
136947: 08/12/15: dajjou: Re: JTAG / IMPACT / VIRTEX
136949: 08/12/15: dajjou: Re: JTAG / IMPACT / VIRTEX
136954: 08/12/15: Gabor: Re: JTAG / IMPACT / VIRTEX
136944: 08/12/15: Svenn Are Bjerkem: Extracting SDF from part of a design in ISE possible?
136946: 08/12/15: Svenn Are Bjerkem: Re: Extracting SDF from part of a design in ISE possible?
136951: 08/12/15: wzab: Synthesizable & open 4DDR Infiniband core
136953: 08/12/15: David Tweed: Re: Synthesizable & open 4DDR Infiniband core
136966: 08/12/16: wzab: Re: Synthesizable & open 4DDR Infiniband core
136961: 08/12/16: Giorgos_P: Leonardo scl05u synthesis-library datasheet
136962: 08/12/16: HT-Lab: Re: Leonardo scl05u synthesis-library datasheet
136967: 08/12/16: HT-Lab: Re: Leonardo scl05u synthesis-library datasheet
136964: 08/12/16: Giorgos_P: Re: Leonardo scl05u synthesis-library datasheet
136963: 08/12/16: <Sudhir.Singh@email.com>: Problem with infering BRAM in XST
136971: 08/12/16: Jason Agron: Re: Problem with infering BRAM in XST
136976: 08/12/16: Brad Smallridge: Re: Problem with infering BRAM in XST
136998: 08/12/17: <Sudhir.Singh@email.com>: Re: Problem with infering BRAM in XST
137014: 08/12/18: rickman: Re: Problem with infering BRAM in XST
136968: 08/12/16: Derek Simmons: Altera Quartus II - 64 bit?
137013: 08/12/18: H. Peter Anvin: Re: Altera Quartus II - 64 bit?
137018: 08/12/18: Subroto Datta: Re: Altera Quartus II - 64 bit?
136969: 08/12/16: Vivek Menon: Sign extension issue in Xilinx Multiplier CoreGen version10
136974: 08/12/16: Lorenz Kolb: Re: Sign extension issue in Xilinx Multiplier CoreGen version10
136977: 08/12/16: Jan: Microblaze without external ram
136981: 08/12/17: backhus: Re: Microblaze without external ram
136988: 08/12/17: jeffg: Re: Microblaze without external ram
136980: 08/12/16: Matt Ettus: Gigabit Ethernet PHY without NDA?
136984: 08/12/17: Allan Herriman: Re: Gigabit Ethernet PHY without NDA?
136986: 08/12/17: John Adair: Re: Gigabit Ethernet PHY without NDA?
136991: 08/12/17: Nico Coesel: Re: Gigabit Ethernet PHY without NDA?
136999: 08/12/17: H. Peter Anvin: Re: Gigabit Ethernet PHY without NDA?
137000: 08/12/18: Matt Ettus: Re: Gigabit Ethernet PHY without NDA?
136985: 08/12/17: =?windows-1252?Q?GaLaKtIkUs=99?=: LEON3 processor
136990: 08/12/17: Jon Beniston: Re: LEON3 processor
136996: 08/12/18: Symon: Re: LEON3 processor
137011: 08/12/18: raph: Re: LEON3 processor
136987: 08/12/17: danmarco: xilinx: FSL - FSL_Has_Data vs FSL_S_Exists
136992: 08/12/17: <jetmarc@hotmail.com>: V4FX PPC405: DCR bus and synchronization
136993: 08/12/17: denish: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit
136994: 08/12/17: Brad Smallridge: Re: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit hidden by declaration of 'ps' at line 651
137009: 08/12/18: Brian Drummond: Re: # ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit hidden by declaration of 'ps' at line 651
136995: 08/12/17: MM: Advanced google group search doesn't work?
136997: 08/12/18: Symon: Re: Advanced google group search doesn't work?
137004: 08/12/18: Symon: Re: Advanced google group search doesn't work?
137010: 08/12/18: MM: Re: Advanced google group search doesn't work?
137001: 08/12/18: Digi Suji: Xilinx BRAM and Synthesis
137002: 08/12/18: Symon: Re: Xilinx BRAM and Synthesis
137017: 08/12/18: Digi Suji: Re: Xilinx BRAM and Synthesis
137003: 08/12/18: vaibhav: Memory Allocation for ISE tools in Linux
137005: 08/12/18: Svenn Are Bjerkem: Looking for a strategy to identify nets in post-map netlist
137016: 08/12/18: KJ: Re: Looking for a strategy to identify nets in post-map netlist
137028: 08/12/19: Mike Treseler: Re: Looking for a strategy to identify nets in post-map netlist
137043: 08/12/20: Svenn Are Bjerkem: Re: Looking for a strategy to identify nets in post-map netlist
137006: 08/12/18: <kharray.bassas@gmail.com>: virtex 5 decryptor
137007: 08/12/18: miloje984: IMPACT: Verification fails with inidirect SPI programming
137008: 08/12/18: General Schvantzkoph: iCore7 vs Core2 NCSim Performance?
137015: 08/12/18: Neil Steiner: FPGA partial/catastrophic failure mode question
137021: 08/12/19: Chris Maryan: Re: FPGA partial/catastrophic failure mode question
137025: 08/12/19: Neil Steiner: Re: FPGA partial/catastrophic failure mode question
137022: 08/12/19: Gabor: Re: FPGA partial/catastrophic failure mode question
137026: 08/12/19: Neil Steiner: Re: FPGA partial/catastrophic failure mode question
137032: 08/12/19: Jeff Cunningham: Re: FPGA partial/catastrophic failure mode question
137023: 08/12/19: Allan Herriman: Re: FPGA partial/catastrophic failure mode question
137027: 08/12/19: Neil Steiner: Re: FPGA partial/catastrophic failure mode question
137029: 08/12/19: glen herrmannsfeldt: Re: FPGA partial/catastrophic failure mode question
137030: 08/12/19: Neil Steiner: Re: FPGA partial/catastrophic failure mode question
137031: 08/12/19: glen herrmannsfeldt: Re: FPGA partial/catastrophic failure mode question
137042: 08/12/20: Hal Murray: Re: FPGA partial/catastrophic failure mode question
137036: 08/12/20: Thomas Stanka: Re: FPGA partial/catastrophic failure mode question
137019: 08/12/19: =?ISO-8859-1?Q?Gerrit_Sch=FCnemann?=: Custom IP Core DMA (Xilinx Virtex II Pro)
137020: 08/12/19: greenlean@gmail.com: Re: Custom IP Core DMA (Xilinx Virtex II Pro)
137033: 08/12/19: Jeff Cunningham: Re: Custom IP Core DMA (Xilinx Virtex II Pro)
137024: 08/12/19: <secureasm@gmail.com>: PCR Reastamping
137034: 08/12/19: Jamie Morken: PLL and clock in altera cyclone 2 fpga
137035: 08/12/20: Lorenz Kolb: Re: PLL and clock in altera cyclone 2 fpga
137039: 08/12/20: Mike Treseler: Re: PLL and clock in altera cyclone 2 fpga
137040: 08/12/20: glen herrmannsfeldt: Re: PLL and clock in altera cyclone 2 fpga
137041: 08/12/20: KJ: Re: PLL and clock in altera cyclone 2 fpga
137047: 08/12/20: Gary Pace: Re: PLL and clock in altera cyclone 2 fpga
137037: 08/12/20: <benwang08@gmail.com>: Large BRAM synthesis
137038: 08/12/20: Lorenz Kolb: Re: Large BRAM synthesis
137046: 08/12/20: Lorenz Kolb: Re: Large BRAM synthesis
137044: 08/12/20: <benwang08@gmail.com>: Re: Large BRAM synthesis
137045: 08/12/20: Nico Coesel: Re: Large BRAM synthesis
137062: 08/12/21: Gael Paul: Re: Large BRAM synthesis
137048: 08/12/21: rickman: Bit width in CPU cores
137049: 08/12/21: rickman: Re: Bit width in CPU cores
137063: 08/12/21: Elizabeth D Rather: Re: Bit width in CPU cores
137065: 08/12/21: Coos Haak: Re: Bit width in CPU cores
137068: 08/12/21: Hal Murray: Re: Bit width in CPU cores
137076: 08/12/21: Elizabeth D Rather: Re: Bit width in CPU cores
137098: 08/12/23: Hal Murray: Re: Bit width in CPU cores
137099: 08/12/23: Hal Murray: Re: Bit width in CPU cores
137093: 08/12/23: Coos Haak: Re: Bit width in CPU cores
137052: 08/12/21: Hal Murray: Re: Bit width in CPU cores
137059: 08/12/21: Jecel: Re: Bit width in CPU cores
137060: 08/12/21: m_l_g3: Re: Bit width in CPU cores
137061: 08/12/21: rickman: Re: Bit width in CPU cores
137064: 08/12/21: foxchip: Re: Bit width in CPU cores
137071: 08/12/21: rickman: Re: Bit width in CPU cores
137072: 08/12/21: rickman: Re: Bit width in CPU cores
137073: 08/12/21: rickman: Re: Bit width in CPU cores
137075: 08/12/21: rickman: Re: Bit width in CPU cores
137077: 08/12/22: Jeremy Bennett: Re: Bit width in CPU cores
137083: 08/12/22: rickman: Re: Bit width in CPU cores
137088: 08/12/22: m_l_g3: Re: Bit width in CPU cores
137089: 08/12/22: m_l_g3: Re: Bit width in CPU cores
137090: 08/12/22: rickman: Re: Bit width in CPU cores
137094: 08/12/23: Arnim: Re: Bit width in CPU cores
137096: 08/12/22: rickman: Re: Bit width in CPU cores
137106: 08/12/23: rickman: Re: Bit width in CPU cores
137128: 08/12/24: Bruce McFarling: Re: Bit width in CPU cores
137050: 08/12/21: Jamie Morken: filtering decimation of a signal
137053: 08/12/21: kadhiem_ayob: Re: filtering decimation of a signal
137051: 08/12/21: Antti: Programming Actel A3P with SVF files
137055: 08/12/21: Antti: Re: Programming Actel A3P with SVF files
137054: 08/12/21: RealInfo: FPGA for Contoll
137056: 08/12/21: Lorenz Kolb: Re: FPGA for Contoll
137058: 08/12/21: RealInfo: Re: FPGA for Contoll
137069: 08/12/21: Hal Murray: Re: FPGA for Contoll
137084: 08/12/22: rickman: Re: FPGA for Contoll
137057: 08/12/21: Jan Decaluwe: Why MyHDL?
137066: 08/12/21: Mike Treseler: Re: Why MyHDL?
137067: 08/12/21: Jan Decaluwe: Re: Why MyHDL?
137070: 08/12/21: Mike Treseler: Re: Why MyHDL?
137079: 08/12/22: Jan Decaluwe: Re: Why MyHDL?
137074: 08/12/22: Andreas Ehliar: Re: Synthesis Problem
137078: 08/12/22: Digi Suji: Synthesis Problem
137080: 08/12/22: Jonathan Bromley: Re: Synthesis Problem
137087: 08/12/22: Jonathan Bromley: Re: Synthesis Problem
137169: 08/12/29: Mike Treseler: Re: Synthesis Problem
137092: 08/12/22: Digi Suji: Re: Synthesis Problem
137151: 08/12/28: rickman: Re: Synthesis Problem
137081: 08/12/22: kashif: Need help with the I/O Standard
137082: 08/12/22: <valwn@silvtrc.org>: Re: Need help with the I/O Standard
137085: 08/12/22: <cpandya@yahoo.com>: Need comment on the following Verilog always block
137086: 08/12/22: Jonathan Bromley: Re: Need comment on the following Verilog always block
137091: 08/12/22: Jan: Adding userports to a custom peripheral in XPS
137095: 08/12/22: jeremywwebb@gmail.com: Re: Adding userports to a custom peripheral in XPS
137105: 08/12/23: Jan: Re: Adding userports to a custom peripheral in XPS
137107: 08/12/23: Lorenz Kolb: Re: Adding userports to a custom peripheral in XPS
137101: 08/12/23: Lorenz Kolb: Re: Adding userports to a custom peripheral in XPS
137097: 08/12/22: Andrew W. Hill: EDK map error 1492 - incompatible programming error
137112: 08/12/23: Gabor: Re: EDK map error 1492 - incompatible programming error
146984: 10/04/07: DougW: Re: EDK map error 1492 - incompatible programming error
137114: 08/12/23: Andrew W. Hill: Re: EDK map error 1492 - incompatible programming error
137100: 08/12/23: <kharray.bassas@gmail.com>: bitstream protection
137102: 08/12/23: <santhosh_h_98@yahoo.com>: DFFR using DFF (only, may be extra gates)
137104: 08/12/23: Lorenz Kolb: Re: DFFR using DFF (only, may be extra gates)
137110: 08/12/23: Jonathan Bromley: Re: DFFR using DFF (only, may be extra gates)
137113: 08/12/23: Hal Murray: Re: DFFR using DFF (only, may be extra gates)
137115: 08/12/23: Muzaffer Kal: Re: DFFR using DFF (only, may be extra gates)
137119: 08/12/23: Jonathan Bromley: Re: DFFR using DFF (only, may be extra gates)
137120: 08/12/23: Muzaffer Kal: Re: DFFR using DFF (only, may be extra gates)
137116: 08/12/23: Muzaffer Kal: Re: DFFR using DFF (only, may be extra gates)
137118: 08/12/23: Muzaffer Kal: Re: DFFR using DFF (only, may be extra gates)
137108: 08/12/23: Gabor: Re: DFFR using DFF (only, may be extra gates)
137111: 08/12/23: gabor: Re: DFFR using DFF (only, may be extra gates)
137117: 08/12/23: Gabor: Re: DFFR using DFF (only, may be extra gates)
137125: 08/12/24: Thomas Stanka: Re: DFFR using DFF (only, may be extra gates)
137236: 09/01/05: John Eaton: Re: DFFR using DFF (only, may be extra gates)
137240: 09/01/05: John Eaton: Re: DFFR using DFF (only, may be extra gates)
137289: 09/01/07: John Eaton: Re: DFFR using DFF (only, may be extra gates)
137287: 09/01/07: <jprovidenza@yahoo.com>: Re: DFFR using DFF (only, may be extra gates)
137307: 09/01/08: gabor: Re: DFFR using DFF (only, may be extra gates)
137103: 08/12/23: Karl: which HLL for HPC applications implementation?
137109: 08/12/23: rickman: Re: which HLL for HPC applications implementation?
137122: 08/12/24: glen herrmannsfeldt: Re: which HLL for HPC applications implementation?
137121: 08/12/23: Karl: Re: which HLL for HPC applications implementation?
137123: 08/12/23: rickman: Re: which HLL for HPC applications implementation?
137124: 08/12/23: rickman: Re: which HLL for HPC applications implementation?
137127: 08/12/24: Jan Decaluwe: Re: which HLL for HPC applications implementation?
137129: 08/12/24: Colin Paul Gloster: Re: which HLL for HPC applications implementation?
137146: 08/12/28: Jeremy Bennett: Re: which HLL for HPC applications implementation?
137126: 08/12/24: rajesh: Generation of WR and RD signal for ASYNC FIFO
137131: 08/12/24: Mike Treseler: Re: Generation of WR and RD signal for ASYNC FIFO
137136: 08/12/27: rajesh: Re: Generation of WR and RD signal for ASYNC FIFO
137141: 08/12/27: KJ: Re: Generation of WR and RD signal for ASYNC FIFO
137160: 08/12/29: rajesh: Re: Generation of WR and RD signal for ASYNC FIFO
137130: 08/12/24: Massi: PCI newbie problems
137132: 08/12/24: Mike Treseler: Re: PCI newbie problems
137133: 08/12/24: <newman5382@yahoo.com>: Re: PCI newbie problems
137135: 08/12/26: Charles Gardiner: Re: PCI newbie problems
137140: 08/12/27: Charles Gardiner: Re: PCI newbie problems
137139: 08/12/27: Massi: Re: PCI newbie problems
137134: 08/12/24: <bybell@gmail.com>: gtkwave website has moved
137137: 08/12/27: dajjou: JTAG USB interface
137138: 08/12/27: Uwe Bonnes: Re: JTAG USB interface
137142: 08/12/28: <valwn@silvtrc.org>: Re: JTAG USB interface
137343: 09/01/09: <job@amontec.com>: Re: JTAG USB interface
137143: 08/12/28: RealInfo: FPGA > ASIC
137144: 08/12/28: Lorenz Kolb: Re: FPGA > ASIC
137145: 08/12/28: Muzaffer Kal: Re: FPGA > ASIC
137148: 08/12/28: Nico Coesel: Re: FPGA > ASIC
137147: 08/12/28: Charles Gardiner: Re: FPGA > ASIC
137149: 08/12/28: RealInfo: Re: FPGA > ASIC
137150: 08/12/28: General Schvantzkoph: Re: FPGA > ASIC
137171: 08/12/30: Thomas Stanka: Re: FPGA > ASIC
137159: 08/12/29: glen herrmannsfeldt: Re: FPGA > ASIC
137164: 08/12/29: john_griessen: Re: FPGA > ASIC
137166: 08/12/29: Mike Treseler: Re: FPGA > ASIC
137176: 08/12/30: Jeff Cunningham: Re: FPGA > ASIC
137192: 09/01/01: whygee: Re: FPGA > ASIC
137184: 08/12/30: Jon Elson: Re: FPGA > ASIC
137155: 08/12/29: <wojtek2u@wp.pl>: Is Implementation in ISE10.1.03 really better than in ISE9.2.03 ???
137170: 08/12/29: Mike Treseler: Re: Is Implementation in ISE10.1.03 really better than in ISE9.2.03
137156: 08/12/29: RealInfo: DIP PACKAGE ?
137157: 08/12/29: H. Peter Anvin: Re: DIP PACKAGE ?
137158: 08/12/29: H. Peter Anvin: Re: DIP PACKAGE ?
137161: 08/12/29: Jonathan Bromley: Re: DIP PACKAGE ?
137162: 08/12/29: <bknpk@hotmail.com>: Code Indentation
137165: 08/12/29: Nicolas Matringe: Re: Code Indentation
137167: 08/12/29: Teece: How do I xor two signals in VHDL?
137168: 08/12/30: Mark McDougall: Re: How do I xor two signals in VHDL?
137175: 08/12/30: Brian Drummond: Re: How do I xor two signals in VHDL?
137172: 08/12/30: Antti: Xilinx QUIZ 2008
137173: 08/12/30: Lorenz Kolb: Re: Xilinx QUIZ 2008
137181: 08/12/30: Lorenz Kolb: Re: Xilinx QUIZ 2008
137174: 08/12/30: Antti: Re: Xilinx QUIZ 2008
137189: 08/12/31: MM: Re: Xilinx QUIZ 2008
137191: 08/12/31: Gavin Scott: Re: Xilinx QUIZ 2008
137226: 09/01/04: Hal Murray: Re: Xilinx QUIZ 2008
137203: 09/01/02: Antti: Re: Xilinx QUIZ 2008
137204: 09/01/02: Antti: Re: Xilinx QUIZ 2008
137223: 09/01/04: Antti: Re: Xilinx QUIZ 2008
137229: 09/01/04: Antti: Re: Xilinx QUIZ 2008
137579: 09/01/22: Antti: Re: Xilinx QUIZ 2008
137177: 08/12/30: cpld-fpga-asic: FPGA/CPLD Design Group on LinkedIn
137178: 08/12/30: Antti: Re: FPGA/CPLD Design Group on LinkedIn
137185: 08/12/30: rickman: Re: FPGA/CPLD Design Group on LinkedIn
137186: 08/12/30: Antti: Re: FPGA/CPLD Design Group on LinkedIn
137179: 08/12/30: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Digilent
137180: 08/12/30: Antti: Re: Digilent
137183: 08/12/30: =?ISO-8859-1?Q?St=E9phane_Goujet?=: Re: Digilent
137182: 08/12/30: John Adair: Re: Digilent
137264: 09/01/06: Prevailing over Technology: Re: Digilent
137187: 08/12/31: aleksa: One-channel >> multi-channel serial DAC
137188: 08/12/31: Frank Buss: Re: One-channel >> multi-channel serial DAC
137190: 08/12/31: Digi Suji: 7 Segment LED Display - BASYS board
137194: 08/12/31: rickman: Re: 7 Segment LED Display - BASYS board
137207: 09/01/02: Dave Pollum: Re: 7 Segment LED Display - BASYS board
137193: 08/12/31: bish: error in synthesizing in ise although correct behavioral simulation
137197: 09/01/01: Brian Drummond: Re: error in synthesizing in ise although correct behavioral simulation
137200: 09/01/01: bish: Re: error in synthesizing in ise although correct behavioral
137206: 09/01/02: Gabor: Re: error in synthesizing in ise although correct behavioral
137210: 09/01/02: bish: Re: error in synthesizing in ise although correct behavioral
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