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On Dec 17, 2:16 am, Allan Herriman <allanherri...@hotmail.com> wrote: > Matt Ettus <boysc...@gmail.com> wrote in news:3dbf05f8-b8cb-4036-800e- > 940af73ce...@n33g2000pri.googlegroups.com: > > The problem is that all of them require an NDA just to see the > > datasheet. Because I intend to publish the design (this is open > > source hardware), I am not in a position where I can sign an NDA. In > > fact, there are FPGA development boards out there with published > > schematics that have a page marked "this page redacted due to an NDA > > on the Marvell 88E1111". This seems nuts to me. I mean, what could > > possibly be NDA-worthy in the datasheet for a 4 year old part that > > implements a technology (GbE) which is nearly a decade old? > > > Does anyone have any suggestions as to non-NDA encumbered GbE PHY > > chips? All I need is GMII or RGMII. > > The last time I looked at PHYs (a few years ago), the good ones required > NDAs for the datasheets, and the ones that didn't have NDAs weren't worth > using. > > I don't see how this clashes with open source hardware though. You need > to document the design of the interface to the PHY but this isn't the > same thing as violating the NDA for the PHY datasheet. The fact that other users have been forced to redact pages of schematics tells me that this is a serious problem. Plus, all the source code is open as well, so who knows what secret registers that might reveal. Besides, I don't want to reward such bad behavior by these chip companies. Can you imagine how hard it would be to design anything if every chip you used had NDAs attached to it? I did find the ET1011C from LSI (formerly Agere). It is cheap, low power, available, and they give out the datasheets without an NDA. Anybody have any experience with it? Thanks, MattArticle: 137001
Hi, I have a design which includes a SRAM from Artisan. I synthesized the whole design using Cadence PKS-shell and simulated the netlist using +delay_mode_zero command line directive in NC-Verilog. It worked fine. I have three questions. 1)Now I am synthesizing the same design in Xilinx ISE 10.1 with a Xilinx's BRAM instead of Artisan's SRAM and simulating it with the UNISIM Library along with +delay_mode_zero option in NC-Verilog, I do not get the expected result. Can any please tell me where could be the problem? 2)What should I do to make the design work without using +delay_mode_zero option? 3)How can a SDF file be generated in Xilinx to do post-synthesis simulation? Thank youArticle: 137002
Digi Suji wrote: > Hi, > > I have a design which includes a SRAM from Artisan. I synthesized the > whole design using Cadence PKS-shell and simulated the netlist using > +delay_mode_zero command line directive in NC-Verilog. It worked fine. > I have three questions. > > 1)Now I am synthesizing the same design in Xilinx ISE 10.1 with a > Xilinx's BRAM instead of Artisan's SRAM and simulating it with the > UNISIM Library along with +delay_mode_zero option in NC-Verilog, I do > not get the expected result. Can any please tell me where could be the > problem? > Xilinx BRAM is synchronous and Artisan SRAM is asynchronous?Article: 137003
Hello All, Can anyone tell me the exact procedure to dedicate physical memory for Xilinx applications in Linux? I know that we need to set the priority using the =93nice=94 command but I require the steps to do it. I have done it for windows using boot.ini file. Appreciate your inputs. Thanks & Regards, VaibhavArticle: 137004
Or, just in CAF.. http://groups.google.com/groups/search?q=isocm&as_ugroup=comp.arch.fpga For more info, you could try this guide... http://groups.google.com/group/alt.fan.dejanews/msg/ad859feb20e08def HTH., Syms. Symon wrote: > http://groups.google.com/groups/search?q=ISOCM > > MM wrote: >> Hi all, >> >> I've been trying to find posts related to ISOCM in Virtex-4 and it >> seems as the google advanced group search got broken... Anyone else >> noticed this? >> >> /MikhailArticle: 137005
Hi, I am currently debugging a post P&R implementation netlist. SDF + VHDL simulate nicely in Modelsim and I am looking for a way to inspect waveforms from signals inside the "gate" level netlist. Since synthesizer and optimizer removes a lot of nets during their work, not all points from the RTL netlist will be available in the PPR netlist, that I am aware of. From reading the dev.pdf I found no clear indication that this is possible. Currently I am looking at preserving some hierarchies in the hope that the signals at the borders of the hierarchy will be available. Still the PR process give those nets different names than the original RTL simulation gave. I am looking for tools/options to tools to automagically generate a .do file for Modelsim (some scripting needed) to get a side-by-side gate and RTL simulation working. Any ideas/comments? -- SvennArticle: 137006
Good evening folks, I m studying the different ways adopted by altera xilinx and lattice to secure bitstream. As a priori knowledge , XILINX (virtex5) method is the most efficient but i still have some questions about this. => When the decryptor start to run ? after receiving the first configurable data (written to FDRI register) ? or after verifying the ECC of the first frame ? => if an encrypted bitstream is loaded to FPGA with a wrong key, the decryptor starts to run anyway ? => there is no other solution to replace the backup battery ? Thank you .Article: 137007
Hi, We have one problem regarding Indirect SPI programming using Impact. On our PCB we have Atmel ATDB642D SPI Flash memory (8CN3,CASON) connected to Spartan-3A XC3S1400AFG676. When we try to program the Flash memory using direct sPI programming method everything works just fine. But when we try to program the memory using indirect SPI programming method the verification fails. During programming SPI lines between memory and Xilinx are active, and SPI communication is doing fine. We see that the code is well downloaded to memory because the FPGA configures well when the board is reset. Nevertheless, the verification fails. Besides that, when we try to perform readback from the memory, we get that memory is filled with zeros, but that obviously is not the case. Readback have been done in JTAG mode. During readback (CCLK, CS, MISO, MOSI SPI) lines which connect SPI memory to Xilinx FPGA are inactive and there is no communication. When we perform indirect SPI method, M[2:0] bits are set for master SPI mode and VS[2:0] bits are set to fast read. Xilinx Prom memory is disabled during programming. We tried to change VS[2:0] to read command, but the problem was not solved. We use Xilinx ISE 10.1 software. I have tried this on Spartan 3a evolution board with xc3sa700 chip and ATDB16 memory chip and this works fine. Thank you in advance, Regards, Ivan Milojevic Serbia, BelgradeArticle: 137008
Has anyone compared the performance of NCSim on a Core2 vs the iCore7? I'm about to get a new system for doing Verilog simulations and I'd like to know how iCore7s perform relative to the Core2.Article: 137009
On Wed, 17 Dec 2008 11:23:57 -0800 (PST), denish <dinesh.twanabasu@gmail.com> wrote: >simulation of the code in ise resulted following error in modelsim ># ** Error: netgen/map/stepper_drive_map.vhd(6692): Physical unit >hidden by declaration of 'ps' at line 651 > I could not figure out what the error actually means. The message tells you exactly what it means. Treat "ps" as if it were a reserved word, and don't use it as an identifier for anything else in your design. Same goes for other units of time, fs, us, ms etc. I believe it isn't technically a reserved word but a pre-declared identifier from the "std" library. Declaring a local "ps" hides the predeclared unit of time (physical unit) and, apart from anything else, will cause confusion to anyone trying to maintain the code. In short; just don't! - Brian.Article: 137010
Thanks Symon. This works. I used to use http://groups.google.com/advanced_search?hl=en&q=&hl=en& and now it seems broken... /Mikhail "Symon" <symon_brewer@hotmail.com> wrote in message news:gic7ln$pl3$1@news.motzarella.org... > http://groups.google.com/groups/search?q=ISOCM > > MM wrote: >> Hi all, >> >> I've been trying to find posts related to ISOCM in Virtex-4 and it >> seems as the google advanced group search got broken... Anyone else >> noticed this? >> >> /Mikhail > >Article: 137011
for more specific question you shoiud poost here : http://tech.groups.yahoo.com/group/leon_sparc/ On Dec 18, 2:01=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Try harder. These searches might help:- > > how to google > > calculate power consumption site:xilinx.com > calculate power consumption site:altera.com > > Good luck, Syms. > > GaLaKtIkUsT wrote: > > Hi everybody, > > I googled for energy consumprtion of LEON3 processor but didn't find > > anything. > > I need statistics of statis/dynamic power consumption for FPGA > > (Xilinx, Altera) and ASIC. > > > Thanks in advance > >Article: 137012
leon3 is a 32 bit softprocessors (see www.gaisler.com, part of grlib, a complete IP library (amba bus for ddr, ddr2, eth, vga, usb, ...), so it is a rather big design , IMHO very well done, and this bufgmuxes are not useless... people at gaisler do provide (all is opensource) implementations for xilinx starter kits (spartan 3E1600 and 3Adsp18000) but their test tools are ise9.2 mine is ISEwebpack 10.1 + sp3. I can't downgrade tools suite. ISE9.2 success during PAR but not ISE10.1 (can't place bufgmuxes) see link in leon_sparc discussion for more... and in addition to that, there are ddr2 memory access failures, but it is an other question On Dec 17, 2:59=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > Raph, > > Yes it is. You're using too many clocks. If you insist on using all these > clocks, you are on the way to destruction. (BTW, I spent 2 seconds > googling - how to do fpga clocking - and found an apparently decent artic= le > explaining why this is true. You did google for an answer, right? Maybe n= ot, > here's the link...http://www.design-reuse.com/articles/4854/fpga-clock-sc= hemes.html) > > Whatever, I suggest you RTM.http://www.xilinx.com/support/documentation/u= ser_guides/ug331.pdf > Try the section "Quadrant Clock Routing", like you were told to do in the > original error message. > Finally, if you post again, tell us specifically for what you're using ea= ch > of all these clocks, and ask questions about what you don't understand in > the user guide linked above. > Good luck, Symon. > > raph wrote: > > thanks for your replies but it is not that... > > if you are interested see : > > >http://tech.groups.yahoo.com/group/leon_sparc/message/14447 > > > On Dec 15, 3:55 pm, Gael Paul <gael.p...@gmail.com> wrote: > >> Hi Raph, > > >> I suggest checking your Leon3 configuration. It is likely that you > >> have a ASIC configuration with clock-gating. When targeting an FPGA, > >> I believe you should get a single clock per core. > > >> - gael > >Article: 137013
Derek Simmons wrote: > Altera list Windows XP x64 as a supported platform for their > development tools. Does anybody know, from experience, if the tool > chain is compiled to take advantage of the larger memory space? The Linux version definitely is. I would assume that the Windows version is too, by now. -hpaArticle: 137014
On Dec 17, 10:27=A0pm, Sudhir.Si...@email.com wrote: > Thanks guys for your replies. > I have been using a component which has inferable BRAM VHDL code from > Xilinx docs. I use this component in my design whenever I need a BRAM. > Brad, yeah you do need a shared variable to get the two write ports. > > Cheers > Sudhir > > On Dec 17, 10:06=A0am, "Brad Smallridge" <bradsmallri...@dslextreme.com> > wrote: > > > Xilinx is promoting the "read address" register > > method now to infer BRAM's so there's got to > > be a read register to latch the address. When you > > add a register outside the BRAM, to speed things > > up as you say, perhaps the synthesizer doesn't > > know what address register it should consider the > > BRAM read address register or, worse, you don't > > have a BRAM address register latch at all within > > the BRAM. > > > You also have to have, I believe, shared variables > > in order to get two write ports. Check me on this. Is this true even if both ports are using the same clock? I want to use a dual port BRAM to allow independent access to the same memory, but both processes use the same clock. Can that be done in one process and XST will still recognize it as a BRAM? I guess I could look at the Xilinx docs.... RickArticle: 137015
Is it true that when FPGAs fail, they typically experience sudden and complete failure, rather than gradual localized degradation? The question stems from comments that I received from a reviewer, concerning the ability to arbitrarily relocate circuitry inside an FPGA. This reviewer had heard it said that sudden and complete failure was the norm, in which case the ability to move circuitry elsewhere in the same device would be pointless. I would appreciate comments from anybody with actual experience in the matter. I am interested if your thoughts both with respect to normal aging, and to damage from radiation or other effects. NeilArticle: 137016
"Svenn Are Bjerkem" <svenn.bjerkem@googlemail.com> wrote in message news:5a368377-2c24-4ae6-aef8-101921828291@x16g2000prn.googlegroups.com... > Hi, > I am currently debugging a post P&R implementation netlist. SDF + VHDL > simulate nicely in Modelsim and I am looking for a way to inspect > waveforms from signals inside the "gate" level netlist. > > Any ideas/comments? > I'd suggest NOT debugging a P&R netlist at all unless you have very strong reason for believing that the synthesis operation has produced something in error. Even then, I've found that other methods are more useful for finding the root cause of an error. If the real board is acting differently than the simulation model (which is presumably the reason for trying to debug the post P&R model) then instead I'd suggest the following plan of attack: - Peruse all synthesis warnings for the usual culprits (incomplete sensitivity lists, combinatorial logic loops, etc.).. The goal is to understand why each warning is 'OK' for your design without any hand waving, fixing all warnings that are not. A goal of 0 warnings while nice, is many times not always possible. - Review timing analysis setup and results. Some of the culprits here are entering incorrect values for the required setup time or clock to output time. A subset of timing analysis is of course crossing clock domains. Make sure your tool is performing timing analysis across clock domains. Although most people 'know' where these crossings are and will properly take care of them, it's not unusual to miss a crossing. Darn near every time completing the above steps will negate the supposed need for post route simulation...and it will take far less time and effort to do so. Kevin JenningsArticle: 137017
On Dec 18, 3:26=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > Digi Suji wrote: > > Hi, > > > I have a design which includes =A0a SRAM from Artisan. I synthesized th= e > > whole design using Cadence PKS-shell and simulated the netlist using > > +delay_mode_zero command line directive in NC-Verilog. It worked fine. > > I have three questions. > > > 1)Now I am synthesizing the same design in Xilinx ISE 10.1 with a > > Xilinx's BRAM instead of Artisan's SRAM and simulating it with the > > UNISIM Library along with +delay_mode_zero option in NC-Verilog, I do > > not get the expected result. Can any please tell me where could be the > > problem? > > Xilinx BRAM is synchronous and Artisan SRAM is asynchronous? yes, artisan SRAM is asynchronus. wat shud I do?Article: 137018
On Dec 16, 6:39=A0am, Derek Simmons <dereks...@gmail.com> wrote: > Altera list Windows XP x64 as a supported platform for their > development tools. Does anybody know, from experience, if the tool > chain is compiled to take advantage of the larger memory space? > > Sincerely, > Derek Simmons Hello Derek, Quartus II 8.0 and more recent versions are available in both 32 and 64 bit versions for the Windows XP and Linux Platforms. Hope this helps, - Subroto Datta Altera Corp.Article: 137019
Hi, I did an XPS Project utilizing the PowerPCs and an custom IP core. Now I would like to gain DMA to the DDR Memory on the XUP Board from the custom IP. Is there a "direct" connection to a memory controller available/suitable, or should I utilize the PLB? The idea is to measure some fast data with the core, write it to the memory and then process it with the PowerPC. Thanks in advance JohnArticle: 137020
On 19 dic, 10:38, Gerrit Sch=FCnemann <slime...@web.de> wrote: > Hi, > I did an XPS Project utilizing the PowerPCs and an custom IP core. Now I > would like to gain DMA to the DDR Memory on the XUP Board from the > custom IP. Is there a "direct" connection to a memory controller > available/suitable, or should I utilize the PLB? > The idea is to measure some fast data with the core, write it to the > memory and then process it with the PowerPC. > > Thanks in advance > > John I recomend you to use EDK and ISE 10.1 and forget using DMA. Instead of that you should use PLB master access from your IP Core and Burst transaction mode, it work fine (and the peripheral wizzard is very usefull). The DMA of the ipif interface don't work in EDK 9.1, one of the necesary bus signal never sets. If you are using ZBT memories in your design, maybe you could use XCL port type in the MCMP from Xilinx. I have not teste this and the other possibilities yet, but I know that XCL is working. Please feedback if you gain direct accese to memory from the IP Core, using NPI or SDMA. Good luck..Article: 137021
Do you mean partial reconfiguration? If those words are foreign to you, look it up on the Xilinx or Altera websites. I'm unfamiliar with the procedure in detail, but understand that it's commonly done. The key point is to lock down all of the configuration that is/isn't changing (presumably to specific area groups, then there exists a mechanism for changing the remaining circuitry. ChrisArticle: 137022
On Dec 18, 9:34=A0pm, Neil Steiner <neil.stei...@east.isi.edu> wrote: > Is it true that when FPGAs fail, they typically experience sudden and > complete failure, rather than gradual localized degradation? > > The question stems from comments that I received from a reviewer, > concerning the ability to arbitrarily relocate circuitry inside an FPGA. > =A0 This reviewer had heard it said that sudden and complete failure was > the norm, in which case the ability to move circuitry elsewhere in the > same device would be pointless. > > I would appreciate comments from anybody with actual experience in the > matter. =A0I am interested if your thoughts both with respect to normal > aging, and to damage from radiation or other effects. > > Neil Our experience has been that there are extremely low rates of field failure in the FPGA's that we use (mostly Xilinx, some Lattice and a few Altera). The types of failure that are typically localized are usually upset events rather than silicon degradation. However I must emphasize that our company does not deliver products into aerospace applications where they are exposed to large amounts of radiation. When a part fails, we generally replace it without looking to see if the failure was localized. Our view of the symptoms is that it doesn't work with our standard pattern, so it's broken. Where I have seen localized degradation (partial burn-out) it has been on I/O drivers. This generally leads to an unusable device without some rewiring at the board level. There are clearly applications for your idea at the manufacturing defect level, however. For example Xilinx uses parts that are only tested to work with a particular pattern for their volume discount ASIC-replacement program. In addition to the reduced test time and therefore cost, this theoretically improves yields. Obviously the ability to use parts with manufacturing defects for general use would be a big plus to Xilinx, especially on the high-end parts that tend to have lower yields (check out the price tags on the XC2V8000 if you want to see what low yield does to cost). If the defects could be mapped reliably you may have usable parts with an effectively slightly smaller fabric size at a fraction of the price or the "perfect" silicon. In order for this sort of application to get to volume use, however you would need to apply the relocation at the tail end of the build process. It is unlikely that large-scale users of these devices will want to run place&route for every chip that goes out the door. Small-scale users like ASIC-simulation where the bitstream is generally only used once would benefit from this. Regards, GaborArticle: 137023
Neil Steiner <neil.steiner@east.isi.edu> wrote in news:494B083B.8090902 @east.isi.edu: > Is it true that when FPGAs fail, they typically experience sudden and > complete failure, rather than gradual localized degradation? > > The question stems from comments that I received from a reviewer, > concerning the ability to arbitrarily relocate circuitry inside an FPGA. > This reviewer had heard it said that sudden and complete failure was > the norm, in which case the ability to move circuitry elsewhere in the > same device would be pointless. > > I would appreciate comments from anybody with actual experience in the > matter. I am interested if your thoughts both with respect to normal > aging, and to damage from radiation or other effects. > > Neil In the one genuinely faulty part that I've seen, it was a very localised failure in the middle of the fabric, and rerunning the P&R tools with some trivial code change (which makes it use different resources) could mask the fault. This was repeatable, and definitely due to a bad spot on the die. Oh, it was an engineering sample. I assume the fault was due to inadequate testing at the factory rather than some field failure. I've also seen failures on early production parts or engineering samples due to preliminary speed files having overly optimistic timing. This causes problems when the P&R tools use a slower part of the die. In that case, moving to a different part of the die could improve matters. But the real fix is to wait for the supplier to finalise the speed files. Perhaps your reviewer was thinking about the sort of failures associated with exceeding the absolute maximum ratings of the part. Regards, AllanArticle: 137024
Hi, Do you ever had to do with the "PCR Restamping" ? You know efficient solution to solve the problem ? Thanks. Kappa.
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