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Good Morning, I have just acquired a Nexys 2 dev board but am having problems connecting to it. I have followed the instructions for the Adept Suite installation, but when I run ExPort, the device is not present. When I configure and choose to 'add module', it is not listed as one of the connected USB modules. The device is being detected by Windows as 'ONBOARD USB', and the attempted automatic driver installation fails. Is there a specific driver I should be using? I used one of these boards last year on another computer and don't remember having any issues with this, but it comes up in my Windows Hardware Manager as an exclamation mark error, called ONBOARD USB. Thanks, ReganArticle: 137301
Furthermore, the board does not seem to pass the onboard diagnostics boot sequence. The switches control the LEDs, but the 7segs are dim and don't say PASS nor FAIL nor RUN, and there is no sign of a 'snake game' that should commence once the diags are done. Do you think I may have inherited a dead board?Article: 137302
I wrote a program based on Xilinx embbed PowerPc 405 in XUP board
ml310 , the system applies a timer interrupt mode. In main() I launch
timer and then enter a while cycle in which I check the flag of time
over. Now the problem is the interrupt cannot return, if I apply a
xil_printf instruction in the while cycle, the interrupt can return
and reaction on the time over flag. Does anybody know the cause? How
can I resolve the problem?. My program is as follow:
#include "xparameters.h"
#include "stdio.h"
#include "xutil.h"
#include "xbasic_types.h"
#include "xintc_l.h"
#include "xintc.h"
#include "xexception_l.h"
#include "xtmrctr.h"
#include "xtmrctr_l.h"
static XTmrCtr myTimer;
static XIntc myIntc;
Xuint8 f_timeover;
//---------------timer interrupt routine------------------------
void timer_a_int_handler(void *CallBackRef, Xuint8 TmrCtrNumber)
{
//Clear the interrupt
XIntc_Acknowledge
(&myIntc,XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
f_timeover=1;
}
//-------------------main()--------------
int main (void) {
print("-- Entering main() --\r\n");
xil_printf("Initialize the timer 0\r\n");
XTmrCtr_Initialize(&myTimer, XPAR_XPS_TIMER_0_DEVICE_ID);
XTmrCtr_SelfTest(&myTimer, 0);
XTmrCtr_SetOptions(&myTimer,(Xuint8)0,XTC_INT_MODE_OPTION |
XTC_DOWN_COUNT_OPTION );
XTmrCtr_SetHandler(&myTimer,(XTmrCtr_Handler)
timer_a_int_handler,NULL);
XIntc_Initialize(&myIntc, XPAR_XPS_INTC_0_DEVICE_ID);
XIntc_Connect(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
(XInterruptHandler)XTmrCtr_InterruptHandler, &myTimer);
XIntc_Start(&myIntc, XIN_REAL_MODE);
XIntc_Enable(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
XExc_Init();
XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT,(XExceptionHandler)
XIntc_DeviceInterruptHandler,(void*)0);
XExc_mEnableExceptions(XEXC_NON_CRITICAL);
//Set the timer to expire 6 seconds
XTmrCtr_SetResetValue(&myTimer, (Xuint8)0, 6 * 50000000);
xil_printf("Will launch the timer...\r\n");
XTmrCtr_Start(&myTimer, (Xuint8)0);
while(1){
if(f_timeover==1){
break;
}
/*
else{
xil_printf("main\r\n");
}
*/
// if I uncomment the above "else" sentence, then the program work
well
}
XTmrCtr_Stop (&myTimer, (Xuint8)0);
xil_printf("Now in main()\r\n");
print("-- Exiting main() --\r\n");
return 0;
}
Article: 137303On Jan 7, 1:49=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > Svenn Are Bjerkem <svenn.bjer...@googlemail.com> writes: > > > of the newer tools weren't available back then. We currently use > > Subversion for anything and I find it kind of awkward to use for RTL. > > Would you care to elaborate? It is probably the branching and merging that I find awkward, using the trunk for everything works fine. Problem is when two branches should be maintained simultaneously. Files supposed to be common in two branches will differ as soon as somebody change that file in one of the branches. In CVS branch could be done on a file so that changes on that file would be the difference between two branches and not the whole codebase as in svn. I have understood that it is possible to use external properties, but this isn't reuse of files, it is common files that is part of the design. -- SvennArticle: 137304
Hi!
You should declare the f_timeover as volatile. Otherwise the compiler
will probably optimize the if-statement in your while loop away. You
could check the object code for this by disassembling it.
Matthias
moonbirch@163.com schrieb:
> I wrote a program based on Xilinx embbed PowerPc 405 in XUP board
> ml310 , the system applies a timer interrupt mode. In main() I launch
> timer and then enter a while cycle in which I check the flag of time
> over. Now the problem is the interrupt cannot return, if I apply a
> xil_printf instruction in the while cycle, the interrupt can return
> and reaction on the time over flag. Does anybody know the cause? How
> can I resolve the problem?. My program is as follow:
> #include "xparameters.h"
> #include "stdio.h"
> #include "xutil.h"
> #include "xbasic_types.h"
> #include "xintc_l.h"
> #include "xintc.h"
> #include "xexception_l.h"
> #include "xtmrctr.h"
> #include "xtmrctr_l.h"
>
> static XTmrCtr myTimer;
> static XIntc myIntc;
>
> Xuint8 f_timeover;
>
> //---------------timer interrupt routine------------------------
> void timer_a_int_handler(void *CallBackRef, Xuint8 TmrCtrNumber)
> {
> //Clear the interrupt
> XIntc_Acknowledge
> (&myIntc,XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
> f_timeover=1;
>
> }
> //-------------------main()--------------
> int main (void) {
> print("-- Entering main() --\r\n");
>
> xil_printf("Initialize the timer 0\r\n");
> XTmrCtr_Initialize(&myTimer, XPAR_XPS_TIMER_0_DEVICE_ID);
> XTmrCtr_SelfTest(&myTimer, 0);
> XTmrCtr_SetOptions(&myTimer,(Xuint8)0,XTC_INT_MODE_OPTION |
> XTC_DOWN_COUNT_OPTION );
> XTmrCtr_SetHandler(&myTimer,(XTmrCtr_Handler)
> timer_a_int_handler,NULL);
>
> XIntc_Initialize(&myIntc, XPAR_XPS_INTC_0_DEVICE_ID);
> XIntc_Connect(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
> (XInterruptHandler)XTmrCtr_InterruptHandler, &myTimer);
> XIntc_Start(&myIntc, XIN_REAL_MODE);
> XIntc_Enable(&myIntc, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
>
> XExc_Init();
> XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT,(XExceptionHandler)
> XIntc_DeviceInterruptHandler,(void*)0);
> XExc_mEnableExceptions(XEXC_NON_CRITICAL);
>
>
> //Set the timer to expire 6 seconds
> XTmrCtr_SetResetValue(&myTimer, (Xuint8)0, 6 * 50000000);
>
> xil_printf("Will launch the timer...\r\n");
> XTmrCtr_Start(&myTimer, (Xuint8)0);
>
> while(1){
> if(f_timeover==1){
> break;
> }
>
> /*
>
> else{
>
> xil_printf("main\r\n");
> }
>
> */
>
> // if I uncomment the above "else" sentence, then the program work
> well
> }
>
> XTmrCtr_Stop (&myTimer, (Xuint8)0);
> xil_printf("Now in main()\r\n");
> print("-- Exiting main() --\r\n");
> return 0;
> }
Article: 137305you hit the point,thank you!Article: 137306
> Obvious alternatives are CVS and git. Have people found new favourite > tools since then? We are mainly using Mercurial, which is a distributed revision control system like git. Previously, we used SVN for many years. Compared to SVN, the distributed way of revision control is much more flexible. Because each developer carries the whole repository with him, checkins can be made locally without network connection and shared with other developers in a peer-to-peer fashion. Furthermore, this approach provides a much faster workflow (because most operations such as commit, diff, log etc. are performed locally) and it gives us a backup solution as a side effect. We choose Mercurial over git because we found the source code of git very hard to understand (it is a mix of Perl, C, and some script magic). In contrast, Mercurial is written Python and pretty OS independent. We also evaluated bzr (also a distributed solution and also written Python) but found it to scale badly with very large projects and not as mature and reliable as Mercurial. We also found the the experiences made by SUN with choosing a revision control system for OpenSolaris valuable: http://www.opensolaris.org/os/community/tools/scm/dscmreqdoc/ (read on by following the menu items on the left) -- NormanArticle: 137307
On Dec 23 2008, 7:57=A0am, santhosh_h...@yahoo.com wrote:
> Hi,
>
> I know DFF is:
>
> module DFF(d,clk,q) ;
> =A0 =A0 =A0input d, clk ;
> =A0 =A0 =A0output reg q ;
>
> =A0 =A0 =A0always @(posedge clk)
> =A0 =A0 =A0 =A0 =A0 =A0q<=3D d ;
> endmodule
>
> Now I need to implement ASYNCHRONOUS RESET flip flop
> using DFF ONLY, may be some extract logic. HOW CAN I DO THAT ?
>
> The implemented circuit MUST WORK AS FOLLOWS:
>
> module DFFR(d,clk,r, q) ;
> =A0 =A0 =A0input d, clk,r ;
> =A0 =A0 =A0output reg q ;
>
> =A0 =A0 =A0always @(posedge clk or posedge r)
> =A0 =A0 =A0 =A0 =A0 if (r) q <=3D 0 ;
> =A0 =A0 =A0 =A0 =A0 else =A0q<=3D d ;
> endmodule
>
> Please give the code or diagram. I am curious about this.
>
> Sant
Well, it seems that we lost the OP a long time ago, but this
sparked my curiosity, so I gave it some more thought and it
seems to me that unless you want to create edge-triggered
circuits from gates, the only way to accomplish this is
to use more than one DFF (in addition to some gates). One
possible solution is:
module DFFR(
input D,
input CLK,
input R,
output Q
);
wire q_int, rst_int, rst_hold, rst_clr;
DFF main_dff (.d (D), .clk (CLK), .q (q_int));
DFF rst_dff (.d (rst_int & !R), .clk (CLK), .q (rst_clr));
assign rst_int =3D R | rst_hold;
assign rst_hold =3D rst_int & !rst_clr;
assign Q =3D q_int & !rst_int;
endmodule
The second DFF creates the clear function for rst_int
which holds the internal reset signal until the next
rising edge of the clock.
This will have some issues in simulation if your
DFF primitive does not have an initial value. You
can work around this my asserting R long enough to
encompass one rising egde of CLK.
Regards,
Gabor
Article: 137308The company tool here is CVS, accessed via the "Super CVS" feature of the Mentor HDL Designer GUI toll that is mandated. There are a number of company-standard and project-specific preferences and policies that make life awkward in certain circumstances. I'm not a fan... CV accessed raw via the command-line is a powerful and flexible tool for version management, although rather venerable.Article: 137309
On Thu, 8 Jan 2009 01:17:44 -0800 (PST), nfeske <norman.feske@genode-labs.com> wrote: >> Obvious alternatives are CVS and git. Have people found new favourite >> tools since then? > >We are mainly using Mercurial, which is a distributed revision control >system like git. Previously, we used SVN for many years. Compared to >SVN, the distributed way of revision control is much more flexible. I am using Mercurial too, and liking it; the distributed repository approach makes more sense, since we have several sites and occasional failures to the "central" host. One problem was encountered when our software guy tried to adopt Mercurial: its script to import an entire project history from SVN didn't work. Has anyone looked at Monotone? It's another distributed system which has had honourable mention for reliability, on comp.lang.ada, whose folks tend to care about such things. - BrianArticle: 137310
On Jan 7, 2:11 pm, Andy <jonesa...@comcast.net> wrote: > > I also noticed the OP's comments delineating the nested levels of if > statements. It should also be noted that if-statements can be labeled, > and if they are, the corresponding end if must include the label: > > clock: if rising_edge(clk) then > ... > end if clock; > > The advantage of this over comments is that labels are checked and > enforced by the compiler; comments are not. > > Andy Wow! about time a language allowed labels on ifs. I've been doing it for years with comments I don't even realize I'm doing it. > > * The OP's final signal assignment outside the clocked if-statement is > not synthesizeable (at least not correctly) because it it is from > another signal (signal_out_temp). If however, signal_out_temp were a > variable, then it would be synthesizeable, at least by some tools. > Signals assigned from expressions of variable(s), after and outside > the clocked if-statement, result in registered references to the > variable(s) being combinatorially assigned to the output signal. If > there were operators or function calls in the expression, those would > be implemented combinatorially after the registered variable values. Well the synth only complained when I took SIGNAL_OUT_TEMP, SIGNAL_IN out of the sensitivity list, can you elaborate a little more on what you feel is not synthesizeable with the original code?Article: 137311
Hello Everyone, I am not too far removed from college and have just begun a project to evaluate ultrasound devices on the information receiving side using a FPGA. I have very limited verilog programming experience. We most likely will be using VHDL in the future for optimization. Anyways we are using the Spartan3A board http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm Could I get some references to learn how to use the ISE program and help with programming in Verilog? The ISE program is espeically intimidating. Thanks for helping me cut down the learning curve.Article: 137312
On Jan 7, 5:06 pm, rickman <gnu...@gmail.com> wrote:
> On Jan 7, 12:36 pm, jleslie48 <j...@jonathanleslie.com> wrote:
>
>
>
>
>
> > You still have me scratching my head on this. Lets look at my example:
>
> > if (mycount >= DEBOUNCE_COUNT) then --{3
> > SIGNAL_OUT_TEMP <= SIGNAL_IN;
> > mycount := 0;
> > end if; --3}
>
> > in this code, DEBOUNCE_COUNT is a constant 5, so are you saying
> > that the lines:
> > SIGNAL_OUT_TEMP <= SIGNAL_IN;
> > mycount := 0;
>
> > are repeated 5 times?
>
> > or this is fundamentally different than a while loop by the nature of
> > using IF instead of WHILE?
>
> The IF is not a while. The loop of a process is repeated on the same
> hardware (process) on each clock tick. Each time the process is run
> an explicit loop repeats N times. Very different.
>
>
>
> > In other words, if I re-write my repeat 10 loop as such:
>
> > looper10_proc: process (CLK,RESET)
> > variable icount : integer := 0;
> > begin
> > if (reset = SWITCH_ON) then
> > icount := 0;
> > elsif (CLK = '1' and CLK'event ) then --{1
> > if (icount <= 10 ) then --{2
> > icount := icount +1;
> > -- do that same something
> > end if; --2}
>
> > end if; --1}
>
> > end process looper_10_proc;
>
> > I think I'm back to keeping the hardware in mind at all times....
>
> Good boy!!!
>
> Remember that each process (that includes each line of concurrent
> code) is a description of a piece of hardware that runs when an input
> changes (implied in concurrent code or explicit in a process). Every
> line of code that is executed within a process is defining what the
> hardware will do on that one trigger event. If you want a process to
> do 10 things on 10 different clock cycles, you need to give it a way
> to know which clock cycle it is on (a counter perhaps) and then
> describe those different behaviors. That is what you have done in the
> above code. You use icount to tell what clock cycle you are on and
> you use the IF statement to tell the process what to do on the
> different clock cycles. If you want to do something multiple times on
> separate hardware (parallel operations) you can use an explicit loop
> to define that. Variables can be used in this case but will often
> result in multiple copies of hardware.
>
> HDL is complex and simple at the same time. I recommend that you
> think in terms of the hardware and then describe the hardware in the
> HDL because that tends to take away the complex parts of the HDL and
> you can use cookie cutters to create your code. I've been doing this
> for over 15 years and I am still using the cookie cutter method.
> Others have been doing this for less time, but spend a higher
> percentage of their time on HDL and so have learned more complex
> methods that reduce their effort. But they didn't learn those methods
> the first day on the job.
>
> Rick
Yay!!! I got something right.
Your very polite in calling it "cut and paste." I've always called in
"Plagiarize
it you can" and have been doing so for 25 years :)))
I see what your saying, and its gonna be a learning curve to get used
to watching
the hardware all the time as I program. Having done a bit of work on
compiler design
that while thing still bugs me though. To a compiler an IF and a
WHILE are just
variations of the same thing. The if becomes in assembly language:
<conditional jump> to else_part
-- then code goes here
<unconditional jump> to endif_xyz
label else_part:
--else code goes here
label endif_xyz:
and the while would be:
label topofwhile_xyz:
<conditional jump> to end_of_while_xyz
---stuff to do
<unconditional jump> to topofwhile_xyz
label end_of_while_xyz:
I was expecting the synth do work similarly.
Article: 137313
On Jan 6, 8:43=A0pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 5 Jan 2009 18:12:51 -0800 (PST), jleslie48
>
> <j...@jonathanleslie.com> wrote:
> >On Jan 5, 7:14 pm, rickman <gnu...@gmail.com> wrote:
> >> On Jan 5, 5:53 pm, jleslie48 <j...@jonathanleslie.com> wrote:
> >>"The synthesis could not "see" your intent and so it threw up its hands
> >>and cried "foul"!"
>
> >- here's my issue. =A0I don't see what my foul was. =A0I agree that
> >functionally what I wrote would never work; every
> >falling edge of the clock pulse would reset 'mycount' to 0. =A0but I
> >don't understand why just because it was stupid
> >it wouldn't synthesize. I'm guessing I ended up with two plugs instead
> >of a plug and a socket
>
> That's a pretty good analogy actually.
>
> Rickman makes the point that this code will simulate (and do something
> odd) but not synthesise. You really have to treat VHDL as, not exactly
> as two separate languages, but as having two separate modes of
> operation. In C, you would program somewhat differently for Visual
> Studio NET edition, and the Microchip PIC C compiler...
>
> In VHDL you (a) have to generate hardware, and (b) have to test it in
> simulation. In the latter case, you can use the full language to express
> your tests as simply and as comprehensively as you can.
>
> But synthesis is different. The synthesis tool has to translate what you
> write into the building blocks available. It actually doesn't try
> compiling arbitrary VHDL into raw silicon; it's more like a process of
> recognising specific design patterns and translating them into blocks it
> already has in hardware.
>
> For example, "Single Process State Machine", "Pure Combinatorial
> Process", "Single Clocked Process With Asynch Reset" and so on
> (don't look these up in the Gang of Four book; try the Xilinx
> "Synthesis and Simulation Design Guide:"http://toolbox.xilinx.com/docsan/=
xilinx6/books/docs/sim/sim.pdf
> instead!)
>
> As synth tools advance, the number of patterns correctly translated is
> increasing, so you'll see discrepancies between older books and recent
> practice. Multiplication is now translated well; division is not (the
> special case of division by 2^n may be recognised; but there are simpler
> alternatives instead!) Floating point is not recognised ... yet, but
> it's coming. And so on.
>
> >for example in c:
> >x =3D 0;
> >While (x < 10) {
> > =A0 x++;
> > =A0 // do something 10 times
> > =A0}//while loop 1
>
> This one in a VHDL process could translate successfully; however it
> will generate ten identical instances of "do something"; possibly with a
> very long combinatorial path through 10 strings of gates...
>
> >>"I'll point
> >> out that your sensitivity list is overly populated.
>
> >> P1: process (CLK, SIGNAL_IN, SIGNAL_OUT_TEMP)"
>
> >ahh, so the sensitivity list should only include elements that define
> >when my "rising edges" of
> >activity should occur, in my case CLK, and in many other cases a RESET
> >event.
>
> Yes; though not every process needs to be clocked.
>
> GATE: process (a,b)
> begin
> =A0 d <=3D a and b and c;
> end process GATE;
>
> is a perfectly legal description of a 3-input AND gate.
> It won't simulate quite as desired of course, and it might synthesise,
> but I would hope for a warning about the incomplete sensitivity list...
>
AND gate must respond to change to 'c' in the above description for it
to be a truly 3-input AND gate.
But 'c' not being in the sensitivity list, d is supposed to have the
same value until 'a' or 'b' changes regardless of any change in 'c'.
So if we follow the rules of sensitivity list, how can we say the
above code to be a legal description of a 3-input AND gate?
Now let's assume synthesis tool tries to exactly describe user's
intent in above code (intentional exclusion of c from sensitivity
list). I don't see this being possible without having some sort of
memory (flip-flop or latch) for c. But the process will not be
combinatorial then. So to keep this as a combinatorial logic,
synthesis tool must make an AND gate (this is what I think, I may me
wrong, I don't know!!!). And I believe AND here is just an example,
any combinatorial however complex might be synthesized in a similar
way, i.e. synthesized hardware not having any difference in its
working in either cases of including or excluding 'c' (or alike
inputs of other combinatorial block). So why should synthesis tool
generate warning messages for not including all the inputs of
combinatorial block in sensitivity list? ('c' in this case; It has to
get 3-input AND here).
Only one point I see for having this warning message useful is when,
say designer by mistake typed 'c' in the expression
d <=3D a and b and c; and he actually did not want to have 'c' as an
input the combinatorial process containing this assignment!!
> Combinatorial processes are legitimate, and synthesisable, but
> error-prone (as above!) - mixing clocked and combinatorial in the same
> process is definitely not recommended.
>
> One pattern you will often see in older books, that is definitely NOT
> recommended now, is "Two (or three) process state machine". It has one
> clocked process which simply registers the current state, and a separate
> (purely combinatorial) process which computes the next state from
> current state and input signals. (And a third process for outputs)
>
> In the real world, with deadlines looming, someone inevitably updates
> the combinatorial process and forgets to update the sensitivity list.
> Oops...
>
> - Brian
Article: 137314In ISE click help -> tutorials If you think ISE daunting, you've chosen the wrong career. ;-) It is irritating though! Good luck, Syms. "njwang" <neal.njwang@gmail.com> wrote in message news:CYOdnTAXTcl9vvvUnZ2dnUVZ_vOdnZ2d@giganews.com... > > Could I get some references to learn how to use the ISE program and help > with programming in Verilog? The ISE program is espeically intimidating. > Thanks for helping me cut down the learning curve. > > >Article: 137315
On Jan 8, 9:32=A0am, jleslie48 <j...@jonathanleslie.com> wrote:
> Well the synth only complained when I took SIGNAL_OUT_TEMP, SIGNAL_IN
> out of the sensitivity list, can you elaborate a little more on what
> you feel is
> not synthesizeable with the original code?
Well, it's kind of tricky to explain, but here goes.
Take this example:
process (clk) is
begin
if rising_edge(clk) then
count_temp <=3D count_temp + 1;
end if;
count_out <=3D count_temp;
end process;
On the rising edge of the clock, clock_out will have the un-
incremented value (because there is no process suspension between the
increment assignment and the subsequent reference of count_temp).
However, on the falling edge of the clock, the whole clocked if clause
does not execute, but the assignment to clock_out still does. Since
the process has suspended since count_temp was incremented, count_out
will be assigned with the incremented value. That requires the output
to change on the falling edge. I suppose it could be synthesized that
way, but I seriously doubt any tool is smart enough to realize it and
do it correctly.
Some synthesis tools are able to synthesize processes that operate on
both edges of a clock, but they cannot do it for the same signal on
both edges (that would be a Double Data Rate flop, which most target
platforms do not support, except some in the IO.
Now, if count_temp were a variable, then some synthesis tools figure
out that count_out updates on the rising edge of the clock, and
synthesize it accordingly.
This brings us to a somewhat popular means of implementing double data
rate (DDR) behavior using single data rate (normal) registers:
process (clk) is
variable qr, qf : std_logic;
begin
if rising_edge(clk) then
qr :=3D d xor qf; -- registered qf ref
elsif falling_edge(clk) then
qf :=3D d xor qr; -- registered qr ref
end if;
q <=3D qf xor qr; -- combinatorial xor of reg'd qr/qf
end process;
The above behaves (WRT q and d) exactly like this one:
process (clk) is
begin
if rising_edge(clk) or falling_edge(clk) then
q <=3D d;
end if;
end process;
The former is synthesizable (by some tools), but the latter is not
(perhaps it should be, and implemented in the form of the former).
The former description takes advantage of the nature of both variables
and signals in one clocked process to do what normally would require
three separate processes (one RE, one FE, and one combinatorial).
Hope this helps,
Andy
Article: 137316Brian Drummond wrote: > > I am using Mercurial too, and liking it; the distributed repository > approach makes more sense, since we have several sites and occasional > failures to the "central" host. > > One problem was encountered when our software guy tried to adopt > Mercurial: its script to import an entire project history from SVN > didn't work. > I often find that converting from CVS or SVN to git works better. Then one can import from git to hg if desired. -hpaArticle: 137317
"njwang": > Could I get some references to learn how to use the ISE program and help > with programming in Verilog? The ISE program is espeically intimidating. > Thanks for helping me cut down the learning curve. On the command line: xst -ifn compile.script ngdbuild prevresult´ map prevresult par prevresult newresult bitgen newresult impact The compile.script could look like run -ifn someverilog.v -top mainmodule -ifmt verilog -opt_mode SPEED -opt_level 1 -p xc3s1000 -ofn ürevresult.ngc Gruss Jan BrunsArticle: 137318
On Jan 8, 12:31=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > On Jan 7, 1:49=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > > > Svenn Are Bjerkem <svenn.bjer...@googlemail.com> writes: > > > > of the newer tools weren't available back then. We currently use > > > Subversion for anything and I find it kind of awkward to use for RTL. > > > Would you care to elaborate? > > It is probably the branching and merging that I find awkward, using > the trunk for everything works fine. Problem is when two branches > should be maintained simultaneously. Files supposed to be common in > two branches will differ as soon as somebody change that file in one > of the branches. In CVS branch could be done on a file so that changes > on that file would be the difference between two branches and not the > whole codebase as in svn. I have understood that it is possible to use > external properties, but this isn't reuse of files, it is common files > that is part of the design. If you are sharing code between FPGA designs, it's probably smart to keep the shared code in its own project within the repository, with the usual trunk/tags/branches structure. In general, you should always use a tagged (immutable by convention in the Subversion world) version of the shared code. This ensures that if your colleague needs to change that shared code, your design will not be affected by his changes. And, yes, the shared code should be brought into your design as an external. -aArticle: 137319
On Thu, 8 Jan 2009 08:47:58 -0800 (PST), bish <bisheshkh@gmail.com> wrote: >> Yes; though not every process needs to be clocked. >> >> GATE: process (a,b) >> begin >> d <= a and b and c; >> end process GATE; >> >> is a perfectly legal description of a 3-input AND gate. >> It won't simulate quite as desired of course, and it might synthesise, >> but I would hope for a warning about the incomplete sensitivity list... >> >AND gate must respond to change to 'c' in the above description for it >to be a truly 3-input AND gate. >But 'c' not being in the sensitivity list, d is supposed to have the >same value until 'a' or 'b' changes regardless of any change in 'c'. >So if we follow the rules of sensitivity list, how can we say the >above code to be a legal description of a 3-input AND gate? Legal is not necessarily the same as correct! (Anyone who has used C will be aware of this...) >Now let's assume synthesis tool tries to exactly describe user's >intent in above code (intentional exclusion of c from sensitivity >list). I don't see this being possible without having some sort of >memory (flip-flop or latch) for c. THAT's the point: the synthesis tool won't even try the exact description. It'll recognise the combinatorial pattern, implement it, and warn about the sensitivity list, as jleslie noticed. >So to keep this as a combinatorial logic, >synthesis tool must make an AND gate (this is what I think, I may me >wrong, I don't know!!!). True for all the synth tools I have used. >And I believe AND here is just an example, >any combinatorial however complex might be synthesized in a similar >way, Absolutely. > So why should synthesis tool >generate warning messages for not including all the inputs of >combinatorial block in sensitivity list? >Only one point I see for having this warning message useful is when, >say designer by mistake typed 'c' in the expression >d <= a and b and c; and he actually did not want to have 'c' as an >input the combinatorial process containing this assignment!! That's one reason; a more likely scenario is that he added 'c' later, and omitted to correct the sensitivity list... Either way, the warning is *essential* to alert the designer to the fact that the implementation cannot meet the specification (description) and is therefore not what he tested in simulation. That is a serious problem, if ignored. - BrianArticle: 137320
On Jan 7, 2:39=A0am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2009-01-07, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > > > Hi, > > found a thread on revision control from 2001 here, but obviously some > > of the newer tools weren't available back then. We currently use > > Subversion for anything and I find it kind of awkward to use for RTL. > > Obvious alternatives are CVS and git. Have people found new favourite > > tools since then? > > I'm using SVN as well. I think the only real problem is when used in > conjunction with ISE (because ISE's config files are mostly binary > instead of text). To work around this (and to gain other advantages) > I'm using a Makefile based build system for larger projects and a > simple synthesis script for smaller projects (where it doesn't matter > if everything has to be resynthesized every time). At least for Xilinx ISE 10.1: take advantage of the "Project =3D> Source Control" feature. This exports the important stuff in the ISE project file out to a couple of tcl scripts. Then all you need in your repository are the tcl scripts, your constraints file and your sources. The rest of the cruft can be deleted. To use those scripts: a) Check out your project in the usual way. b) Open ISE. c) From the "Project" menu, choose "Source Control | Import" and mouse around to the myproject_import.tcl script. d) Tell the dialog where to store the "inflated" project. e) ISE will recreate the project, including the binary ISE file, from that script, and it should all work. I am told that 11.1i will have text-based project files. -aArticle: 137321
Hello there, I own the NIOS - stratix II development board ( http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html ). Does anybody know how to read a file from the onboard CF? I do not want to use an OS on the NIOS processor. Any reference design is more then welcome . . . Thanks, GuyArticle: 137322
On Thu, 8 Jan 2009 07:32:11 -0800 (PST), jleslie48 <jon@jonathanleslie.com> wrote: >On Jan 7, 2:11 pm, Andy <jonesa...@comcast.net> wrote: >> clock: if rising_edge(clk) then >> ... >> end if clock; >> >> The advantage of this over comments is that labels are checked and >> enforced by the compiler; comments are not. >> >> Andy > >Wow! about time a language allowed labels on ifs. I've been doing >it >for years with comments I don't even realize I'm doing it. Then I think you'll find a lot more "about time"s in VHDL, where it allows the compiler to statically check lots of things (or better, allow algorithms to be expressed in intrinsically safe manner) for clearer and more reliable code. And thanks to Andy for pointing this example out; it's one I don't use enough myself. >> * The OP's final signal assignment outside the clocked if-statement is >> not synthesizeable (at least not correctly) because it it is from >> another signal (signal_out_temp). If however, signal_out_temp were a >> variable, then it would be synthesizeable, at least by some tools. >Well the synth only complained when I took SIGNAL_OUT_TEMP, SIGNAL_IN >out of the sensitivity list, can you elaborate a little more on what >you feel is not synthesizeable with the original code? Again it's synthesisable; just not correctly, i.e. not in a way that matches simulation. SIGNAL_OUT_TEMP is assigned after the clocked process. It is not copied to SIGNAL_OUT until the clocked process wakes up again ... with only CLK in the sensitivity list, that is half a cycle later. The synthesis tool will implement something, but probably not that... Restoring SIGNAL_OUT_TEMP to the sensitivity list wakes the process up immediately (i.e. in the next delta cycle). Now, a really good synthesis tool should correctly implement the final signal assignment. But it's enough of a deviation from the normal pattern that it may not be recognised by all synth tools. So why take the risk? - BrianArticle: 137323
On Wed, 7 Jan 2009 09:36:05 -0800 (PST), jleslie48
<jon@jonathanleslie.com> wrote:
>On Jan 6, 8:21 pm, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:
>> -- this is inside a process of course!
>> for i in x_type loop
>> if i < x then
>> do_something;
>> end if;
>> end loop;
>>
end if; --1}
>You still have me scratching my head on this. Lets look at my example:
>
>
> if (mycount >= DEBOUNCE_COUNT) then --{3
> SIGNAL_OUT_TEMP <= SIGNAL_IN;
> mycount := 0;
> end if; --3}
>
>in this code, DEBOUNCE_COUNT is a constant 5, so are you saying
>that the lines:
> SIGNAL_OUT_TEMP <= SIGNAL_IN;
> mycount := 0;
>
>are repeated 5 times?
Absolutely not...
>or this is fundamentally different than a while loop by the nature of
>using IF instead of WHILE?
Yes. Because semantically, IF and WHILE are very different.
(even if, in some languages, they may look similar). In VHDL you cannot
even write a while loop without using the word "loop" somewhere, which
may help to make the distinction clear.
>In other words, if I re-write my repeat 10 loop as such:
>
>looper10_proc: process (CLK,RESET)
>variable icount : integer := 0;
>begin
> if (reset = SWITCH_ON) then
> icount := 0;
> elsif (CLK = '1' and CLK'event ) then --{1
> if (icount <= 10 ) then --{2
> icount := icount +1;
> -- do that same something
> end if; --2}
>
> end if; --1}
>
>end process looper_10_proc;
As Rick says, good!
That is a good example of a pattern to iterate ten times with one
"do_something".
- Brian
Article: 137324
On Jan 8, 2:52 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
>
> >In other words, if I re-write my repeat 10 loop as such:
>
> >looper10_proc: process (CLK,RESET)
> >variable icount : integer := 0;
> >begin
> > if (reset = SWITCH_ON) then
> > icount := 0;
> > elsif (CLK = '1' and CLK'event ) then --{1
> > if (icount <= 10 ) then --{2
> > icount := icount +1;
> > -- do that same something
> > end if; --2}
>
> > end if; --1}
>
> >end process looper_10_proc;
>
> As Rick says, good!
> That is a good example of a pattern to iterate ten times with one
> "do_something".
>
> - Brian
My turing machine, language processing, LL(1) grammar, and compiler
design Professors are turning over in their graves,
but it seems to be a consensus that this is the way it works.
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