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Threads Starting Jun 2007

120086: 07/06/01: Sandip: After PAR simulation, should I assume that it will work on FPGA board?
    120087: 07/06/01: Mark McDougall: Re: After PAR simulation, should I assume that it will work on FPGA
    120088: 07/05/31: Thomas Stanka: Re: After PAR simulation, should I assume that it will work on FPGA board?
        120134: 07/06/01: Mike Lewis: Re: After PAR simulation, should I assume that it will work on FPGA board?
    120103: 07/06/01: Sandip: Re: After PAR simulation, should I assume that it will work on FPGA board?
120102: 07/06/01: Andreas Ehliar: Re: Can anyone explain the details of the FPGA design flow in ISE
120106: 07/06/01: subint: Can anyone explain the details of the FPGA design flow in ISE
120107: 07/06/01: subint: Can anyone explain the details of the FPGA design flow in ISE
    120229: 07/06/03: svenand: Re: Can anyone explain the details of the FPGA design flow in ISE
120109: 07/06/01: subint: Some doubts in the FPGA design flow in the ISE
    120225: 07/06/03: vssumesh: Re: Some doubts in the FPGA design flow in the ISE
120111: 07/06/01: Simon Heinzle: Xilinx MIG and verifying UCF files
    120116: 07/06/01: subint: Re: Xilinx MIG and verifying UCF files
120112: 07/06/01: =?utf-8?B?R2FMYUt0SWtVc+KEog==?=: Virtex-4 troubles after configuration
120113: 07/06/01: Adnan: Regarding multiple write problem in opencores pci bridge
    120219: 07/06/04: Mark McDougall: Re: Regarding multiple write problem in opencores pci bridge
120117: 07/06/01: fabien.goy@gmail.com: using ICAP with the ML310
    120152: 07/06/01: Neil Steiner: Re: using ICAP with the ML310
    120236: 07/06/04: fabien.goy@gmail.com: Re: using ICAP with the ML310
    120262: 07/06/04: fabien.goy@gmail.com: Re: using ICAP with the ML310
120118: 07/06/01: Tim Morlion: ise9.1 : partitions with edif flow
    120252: 07/06/04: Patrick Dubois: Re: ise9.1 : partitions with edif flow
        120253: 07/06/04: Tim: Re: ise9.1 : partitions with edif flow
            120293: 07/06/05: Tim: Re: ise9.1 : partitions with edif flow
    120258: 07/06/04: Patrick Dubois: Re: ise9.1 : partitions with edif flow
120119: 07/06/01: Linas Petras: CoreGen Issues ??
    120247: 07/06/04: Gabor: Re: CoreGen Issues ??
120123: 07/06/01: Philipp Klaus Krause: Cyclone 3 Starter Board connector?
120124: 07/06/01: Pablo: Bootloader in BRAM to run a program loaded in the DDR
    120127: 07/06/01: Antti: Re: Bootloader in BRAM to run a program loaded in the DDR
    120130: 07/06/01: Pablo: Re: Bootloader in BRAM to run a program loaded in the DDR
    120131: 07/06/01: Antti: Re: Bootloader in BRAM to run a program loaded in the DDR
120135: 07/06/01: Tomas Davidovic: ML402 development board
    120140: 07/06/01: Ed McGettigan: Re: ML402 development board
        120146: 07/06/01: Tomas Davidovic: Re: ML402 development board
120145: 07/06/01: jack lee: How to guarantee the same relative placement and routing in ISE?
120148: 07/06/01: <javaguy11111@gmail.com>: Modular Design Example
    120154: 07/06/01: <javaguy11111@gmail.com>: Re: Modular Design Example
120153: 07/06/01: lgs23: xilinx parallel cable troubles
    120163: 07/06/01: Antti: Re: xilinx parallel cable troubles
    120188: 07/06/02: Sylvain Munaut: Re: xilinx parallel cable troubles
    120228: 07/06/03: svenand: Re: xilinx parallel cable troubles
    120264: 07/06/04: lgs23: Re: xilinx parallel cable troubles
        120267: 07/06/04: Uwe Bonnes: Re: xilinx parallel cable troubles
            120336: 07/06/05: lgs23: Re: xilinx parallel cable troubles
120155: 07/06/01: Nicholas Kubiak: Tristate ipcore problem with XPS
120156: 07/06/01: Marlboro: Weekend pop quiz
    120162: 07/06/01: Tommy Thorn: Re: Weekend pop quiz
        120201: 07/06/03: Symon: Re: Weekend pop quiz
    120167: 07/06/02: Marlboro: Re: Weekend pop quiz
    120186: 07/06/02: Tommy Thorn: Re: Weekend pop quiz
    120194: 07/06/02: Marlboro: Re: Weekend pop quiz
    120217: 07/06/03: Eric Smith: Re: Weekend pop quiz
120164: 07/06/02: Totally_Lost: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120180: 07/06/02: Thomas Womack: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120285: 07/06/04: Ray Andraka: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer
        120333: 07/06/05: Thomas Womack: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer
    120351: 07/06/05: Totally_Lost: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120361: 07/06/05: Totally_Lost: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120369: 07/06/05: Totally_Lost: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120457: 07/06/07: comp.arch.fpga: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120507: 07/06/08: Totally_Lost: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120510: 07/06/08: Ben Jones: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
    120525: 07/06/08: Totally_Lost: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
120165: 07/06/02: Yao Sics: How to execute application code out of external memory using EDK?
    120170: 07/06/02: morphiend: Re: How to execute application code out of external memory using EDK?
120171: 07/06/02: morphiend: LocalLink TEMAC Data Corruption
    120182: 07/06/02: MM: Re: LocalLink TEMAC Data Corruption
    120193: 07/06/02: MM: Re: LocalLink TEMAC Data Corruption
    120196: 07/06/03: morphiend: Re: LocalLink TEMAC Data Corruption
    120385: 07/06/06: Greg Crocker: Re: LocalLink TEMAC Data Corruption
120172: 07/06/02: morphiend: Xilinx OPB External Memory Controller
    120174: 07/06/02: Jan Pech: Re: Xilinx OPB External Memory Controller
    120183: 07/06/02: morphiend: Re: Xilinx OPB External Memory Controller
    120199: 07/06/03: Jan Pech: Re: Xilinx OPB External Memory Controller
    120266: 07/06/04: morphiend: Re: Xilinx OPB External Memory Controller
120173: 07/06/02: Pasacco: FIFO : Synchronous WRITE, Asynchronous READ ?
    120178: 07/06/02: John_H: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120184: 07/06/02: Pasacco: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120185: 07/06/02: Duane Clark: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
        120260: 07/06/04: Barry Brown: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
            120268: 07/06/04: John_H: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
                120280: 07/06/04: Duane Clark: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120190: 07/06/02: Peter Alfke: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120202: 07/06/03: Symon: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
        120208: 07/06/03: Duane Clark: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120204: 07/06/03: Marlboro: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
    120499: 07/06/07: Frank: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120176: 07/06/02: comp.arch.fpga: Re: 180 differential inputs each 800Mbps using V5
120197: 07/06/02: mahalingamv@gmail.com: ngdbuild error : multiple drivers and driving non buffer primitives
    120213: 07/06/03: motty: Re: ngdbuild error : multiple drivers and driving non buffer primitives
        120302: 07/06/05: Brian Drummond: Re: ngdbuild error : multiple drivers and driving non buffer primitives
    120248: 07/06/04: mahalingamv@gmail.com: Re: ngdbuild error : multiple drivers and driving non buffer primitives
    120271: 07/06/04: Sean Durkin: Re: ngdbuild error : multiple drivers and driving non buffer primitives
    120282: 07/06/04: motty: Re: ngdbuild error : multiple drivers and driving non buffer primitives
    120318: 07/06/05: mahalingamv@gmail.com: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120200: 07/06/03: John Adair: Raggedstone1 Brackets
120205: 07/06/03: <jidan1@hotmail.com>: Microcontrollers have a better predictable time behaviour than FPGAs
    120206: 07/06/03: Symon: Re: Microcontrollers have a better predictable time behaviour than FPGAs
    120207: 07/06/04: Jim Granville: Re: Microcontrollers have a better predictable time behaviour than
        120210: 07/06/03: mk: Re: Microcontrollers have a better predictable time behaviour than FPGAs
        120211: 07/06/03: Colin Paul Gloster: Re: Microcontrollers have a better predictable time behaviour than FPGAs
    120212: 07/06/03: Ralf Hildebrandt: Re: Microcontrollers have a better predictable time behaviour than
    120216: 07/06/03: Jonathan Bromley: Re: Microcontrollers have a better predictable time behaviour than FPGAs
        120263: 07/06/04: Sean Durkin: Re: Microcontrollers have a better predictable time behaviour than
    120251: 07/06/04: <jidan1@hotmail.com>: Re: Microcontrollers have a better predictable time behaviour than FPGAs
120214: 07/06/03: Ben Jackson: Altera Serial Flash Loader (SFL) question
    120220: 07/06/04: Mark McDougall: Re: Altera Serial Flash Loader (SFL) question
        120221: 07/06/04: Mark McDougall: Re: Altera Serial Flash Loader (SFL) question
            120226: 07/06/03: Ben Jackson: Re: Altera Serial Flash Loader (SFL) question
                120227: 07/06/04: Mark McDougall: Re: Altera Serial Flash Loader (SFL) question
120215: 07/06/03: rajiv: Synchronization of instruction with clock
120218: 07/06/03: Koustav: Create and Import Peripheral in EDK
    120233: 07/06/04: Pablo: Re: Create and Import Peripheral in EDK
120222: 07/06/04: Philipp Hachtmann: Problem with System ACE
    120245: 07/06/04: Philipp Hachtmann: Re: Problem with System ACE -> Solved!
120223: 07/06/03: <javaguy11111@gmail.com>: TBUF and modular design flow on spartan
    120243: 07/06/04: Gabor: Re: TBUF and modular design flow on spartan
        120272: 07/06/04: Sean Durkin: Re: TBUF and modular design flow on spartan
    120250: 07/06/04: <javaguy11111@gmail.com>: Re: TBUF and modular design flow on spartan
    120276: 07/06/04: <javaguy11111@gmail.com>: Re: TBUF and modular design flow on spartan
120232: 07/06/04: L. Schreiber: any experiences concerning xup and digilent inc.?
    120246: 07/06/04: Eli Hughes: Re: any experiences concerning xup and digilent inc.?
    120249: 07/06/04: mahalingamv@gmail.com: Re: any experiences concerning xup and digilent inc.?
120234: 07/06/04: Antti: Lattice XP2 finally announced
    120237: 07/06/04: Sean Durkin: Re: Lattice XP2 finally announced
        120239: 07/06/04: Uwe Bonnes: Re: Lattice XP2 finally announced
            120254: 07/06/04: <lb.edc@telenet.be>: Re: Lattice XP2 finally announced
            120257: 07/06/04: Uwe Bonnes: Re: Lattice XP2 finally announced
        120275: 07/06/04: Tim: Re: Lattice XP2 finally announced
            120278: 07/06/04: austin: Re: Lattice XP2 finally announced
                120281: 07/06/04: austin: Re: Lattice XP2 finally announced
                    120283: 07/06/05: Jim Granville: Re: Lattice XP2 finally announced
                        120284: 07/06/04: austin: Power on Spartan 90nm process node
                            120286: 07/06/05: Jim Granville: Re: Power on Spartan 90nm process node
                                120288: 07/06/04: austin: Re: Power on Spartan 90nm process node
                                    120289: 07/06/05: Jim Granville: Re: Power on Spartan 90nm process node
                                        120305: 07/06/05: austin: Re: Power on Spartan 90nm process node
                120297: 07/06/05: Tim (one of many): Re: Lattice XP2 finally announced
                    120307: 07/06/05: austin: Re: Lattice XP2 finally announced
                        120317: 07/06/05: mk: Re: Lattice XP2 finally announced
                        120319: 07/06/05: austin: ARM in FPGA's?
                            120324: 07/06/05: austin: Re: ARM in FPGA's?
                            120331: 07/06/05: Tim (one of many): Re: ARM in FPGA's?
                        120352: 07/06/06: Jim Granville: Re: Lattice XP2 finally announced
                            120356: 07/06/06: Jim Granville: Re: Lattice XP2 finally announced
                    120329: 07/06/05: Tim (one of many): Re: Lattice XP2 finally announced
                120298: 07/06/05: Uwe Bonnes: Re: Lattice XP2 finally announced
                120306: 07/06/05: austin: V4 FX Apologia: (again)
    120238: 07/06/04: Antti: Re: Lattice XP2 finally announced
    120241: 07/06/04: John Adair: Re: Lattice XP2 finally announced
    120294: 07/06/05: Jon Beniston: Re: Lattice XP2 finally announced
    120300: 07/06/05: Antti: Re: Lattice XP2 finally announced
    120310: 07/06/05: Antti: Re: Lattice XP2 finally announced
    120321: 07/06/05: Sandro: Re: ARM in FPGA's?
    120323: 07/06/05: Antti: Re: ARM in FPGA's?
    120327: 07/06/05: Sandro: Re: ARM in FPGA's?
    120332: 07/06/05: Antti: Re: ARM in FPGA's?
120235: 07/06/04: Simon Heinzle: ISE and total equivalent gate count
    120265: 07/06/04: austin: Re: ISE and total equivalent gate count
        120303: 07/06/05: Brian Drummond: Re: ISE and total equivalent gate count
            120311: 07/06/05: austin: Re: ISE and total equivalent gate count
120244: 07/06/04: sjulhes: Power PC heap initialisation on Reset
    120391: 07/06/06: sjulhes: Re: Power PC heap initialisation on Reset
    120427: 07/06/06: Peter Ryser: Re: Power PC heap initialisation on Reset
        120505: 07/06/08: sjulhes: Re: Power PC heap initialisation on Reset
120255: 07/06/04: maxascent: MGT Clock
    120259: 07/06/04: MM: Re: MGT Clock
120261: 07/06/04: jacky: modelsim
    120291: 07/06/05: Jonathan Bromley: Re: modelsim
        120292: 07/06/05: jacky: Re: modelsim
120273: 07/06/04: Patrick Dubois: XST sythesizes fifos instead of creating black boxes
    120337: 07/06/05: Patrick Dubois: Re: XST sythesizes fifos instead of creating black boxes
        120345: 07/06/05: Mike Treseler: Re: XST sythesizes fifos instead of creating black boxes
    120339: 07/06/05: Patrick Dubois: Re: XST sythesizes fifos instead of creating black boxes
120274: 07/06/04: LC: FFT and etc on a cycloneII or III help/sugestions.
120279: 07/06/04: Manny: System Generator installation
120287: 07/06/04: Biancu: Mesa 5i21 Xilinx
    120344: 07/06/05: Mike Treseler: Re: Mesa 5i21 Xilinx
120295: 07/06/05: <haghdoost@gmail.com>: Topics and Ideas for BS Project
    120299: 07/06/05: Symon: Re: Topics and Ideas for BS Project
    120314: 07/06/05: austin: Re: Topics and Ideas for BS Project
        120342: 07/06/05: Mike Treseler: Re: Topics and Ideas for BS Project
        120347: 07/06/05: HT-Lab: Re: Topics and Ideas for BS Project
            120375: 07/06/06: Colin Paul Gloster: Re: Topics and Ideas for BS Project
                120444: 07/06/07: Colin Paul Gloster: Re: Topics and Ideas for BS Project
                    120461: 07/06/07: Evan Lavelle: Re: Topics and Ideas for BS Project
                        120512: 07/06/08: Colin Paul Gloster: Re: Topics and Ideas for BS Project
                            120618: 07/06/12: Evan Lavelle: Re: Topics and Ideas for BS Project
                                120679: 07/06/13: Colin Paul Gloster: Re: Topics and Ideas for BS Project
                                    120688: 07/06/13: Evan Lavelle: Re: Topics and Ideas for BS Project
                                    120703: 07/06/14: Colin Paul Gloster: Re: Topics and Ideas for BS Project
            120443: 07/06/07: HT-Lab: Re: Topics and Ideas for BS Project
        120359: 07/06/05: glen herrmannsfeldt: Re: Topics and Ideas for BS Project
            120404: 07/06/06: Terje Mathisen: Re: Topics and Ideas for BS Project
                121327: 07/07/02: glen herrmannsfeldt: Re: Topics and Ideas for BS Project
    120335: 07/06/05: ARH: Re: Topics and Ideas for BS Project
    120353: 07/06/05: ARH: Re: Topics and Ideas for BS Project
    120376: 07/06/06: <hans64@ht-lab.com>: Re: Topics and Ideas for BS Project
    120389: 07/06/06: <hans64@ht-lab.com>: Re: Topics and Ideas for BS Project
    120397: 07/06/06: ARH: Re: Topics and Ideas for BS Project
120296: 07/06/05: pk: OPB IPIF Master Attachment
120301: 07/06/05: maxascent: Choosing a clock
    120315: 07/06/05: austin: Re: Choosing a clock
120304: 07/06/05: Yao Sics: How to Access CompactFlash by using SystemACE?
    120308: 07/06/05: Jon Beniston: Re: How to Access CompactFlash by using SystemACE?
    120363: 07/06/06: Yao Sics: Re: How to Access CompactFlash by using SystemACE?
120309: 07/06/05: <rponsard@gmail.com>: mig 1.7 for SDRAM DDR 1 or 2 controller : watch your ISE properties
    120328: 07/06/05: Patrick Dubois: Re: mig 1.7 for SDRAM DDR 1 or 2 controller : watch your ISE properties
120312: 07/06/05: Shant: Build error for multiprocessor sytem.
    120354: 07/06/06: John Williams: Re: Build error for multiprocessor sytem.
    120433: 07/06/07: Shant: Re: Build error for multiprocessor sytem.
    120731: 07/06/15: Jason Agron: Re: Build error for multiprocessor sytem.
    121606: 07/07/09: JD Newcomb: Re: Build error for multiprocessor sytem.
120316: 07/06/05: Andrew: System Generator vs Synplify DSP vs Simulink HDL Coder
    120330: 07/06/05: Kevin Neilson: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
        120346: 07/06/05: Kevin Neilson: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
    120334: 07/06/05: Andrew: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
    120592: 07/06/11: Jon: Re: System Generator vs Synplify DSP vs Simulink HDL Coder
120320: 07/06/05: Amal: Portable TCP/IP socket library
    120322: 07/06/05: <cs_posting@hotmail.com>: Re: Portable TCP/IP socket library
        120338: 07/06/05: HT-Lab: Re: Portable TCP/IP socket library
    120387: 07/06/06: EdA: Re: Portable TCP/IP socket library
    120415: 07/06/06: <cs_posting@hotmail.com>: Re: Portable TCP/IP socket library
    120463: 07/06/07: Amal: Re: Portable TCP/IP socket library
120325: 07/06/05: Pablo: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
    120343: 07/06/05: Patrick Dubois: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
    120348: 07/06/05: MM: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
        120392: 07/06/06: Ben Jones: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
            120450: 07/06/07: Ben Jones: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
    120394: 07/06/06: Pablo: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
    120428: 07/06/06: Peter Ryser: Re: Unable to connect to PowerPC target. Invalid Processor Version
    120435: 07/06/07: Pablo: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120340: 07/06/05: MikeJ: Virtex4 CLKX2 DCM Jitter
    120349: 07/06/05: austin: Re: Virtex4 CLKX2 DCM Jitter
        120355: 07/06/05: austin: Re: Virtex4 CLKX2 DCM Jitter
            120357: 07/06/05: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
            120358: 07/06/06: John Retta: Re: Virtex4 CLKX2 DCM Jitter
                120377: 07/06/06: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
            120371: 07/06/06: mk: Re: Virtex4 CLKX2 DCM Jitter
                120393: 07/06/06: austin: Re: Virtex4 CLKX2 DCM Jitter
                    120396: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter
                        120401: 07/06/06: austin: Re: Virtex4 CLKX2 DCM Jitter, comments on DAC
                            120419: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter, comments on DAC
                                120459: 07/06/07: austin: Re: Virtex4 CLKX2 DCM Jitter, comments on DAC
                        120413: 07/06/07: Jim Granville: Re: Virtex4 CLKX2 DCM Jitter
                            120416: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter
                                120418: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter
                    120411: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter
                    120424: 07/06/07: Gerhard Hoffmann: Re: Virtex4 CLKX2 DCM Jitter
                        120425: 07/06/06: John_H: Re: Virtex4 CLKX2 DCM Jitter
                        120437: 07/06/07: Symon: Re: Virtex4 CLKX2 DCM Jitter
                            120439: 07/06/07: Gerhard Hoffmann: Re: Virtex4 CLKX2 DCM Jitter
                                120440: 07/06/07: Symon: Re: Virtex4 CLKX2 DCM Jitter
                            120464: 07/06/07: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
                                120473: 07/06/07: austin: Re: Virtex4 CLKX2 DCM Jitter
                                    120477: 07/06/07: John_H: Re: Virtex4 CLKX2 DCM Jitter
    120360: 07/06/05: Brian Davis: Re: Virtex4 CLKX2 DCM Jitter
        120380: 07/06/06: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
            120597: 07/06/11: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
    120379: 07/06/06: Symon: Re: Virtex4 CLKX2 DCM Jitter
        120381: 07/06/06: MikeJ: Re: Virtex4 CLKX2 DCM Jitter
            120438: 07/06/07: Symon: Re: Virtex4 CLKX2 DCM Jitter
    120574: 07/06/10: Brian Davis: Re: Virtex4 CLKX2 DCM Jitter
120341: 07/06/05: Test01: svf file programming issue
120350: 07/06/05: Ahmed: Difference between DCM and PMCD
120362: 07/06/06: Yao Sics: Weird! sysace_fwrite() cannot be found!!!???
    120364: 07/06/05: Yao Sics: Re: Weird! sysace_fwrite() cannot be found!!!???
    120365: 07/06/05: Siva Velusamy: Re: Weird! sysace_fwrite() cannot be found!!!???
120366: 07/06/06: VIPS: How to Find false path in a design
    120367: 07/06/05: Jonathan Bromley: Re: How to Find false path in a design
        120434: 07/06/06: Jonathan Bromley: Re: How to Find false path in a design
    120373: 07/06/06: <hans64@ht-lab.com>: Re: How to Find false path in a design
    120398: 07/06/06: Mike Treseler: Re: How to Find false path in a design
120368: 07/06/05: Ace: XILINX IPCore
    120370: 07/06/05: John Adair: Re: XILINX IPCore
    120372: 07/06/06: Ben Jackson: Re: XILINX IPCore
    120414: 07/06/06: <ghelbig@lycos.com>: Re: XILINX IPCore
120374: 07/06/06: Pablo: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
    120378: 07/06/06: Zara: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
    120384: 07/06/06: Symon: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
        120465: 07/06/07: MikeJ: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
    120386: 07/06/06: Patrick Dubois: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
    120388: 07/06/06: Pablo: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
120382: 07/06/06: sanju: asynchronous circuit design
    120399: 07/06/06: Mike Treseler: Re: asynchronous circuit design
    120402: 07/06/06: Jonathan Bromley: Re: asynchronous circuit design
    120403: 07/06/06: austin: Re: asynchronous circuit design
        120417: 07/06/07: Frank Buss: Re: asynchronous circuit design
        120426: 07/06/07: Jim Granville: Re: asynchronous circuit design
    120405: 07/06/06: Newman: Re: asynchronous circuit design
    120446: 07/06/07: Christopher: Re: asynchronous circuit design
120383: 07/06/06: naran: Reg:Clock to pad Delay of the System Clock.
120395: 07/06/06: jjlindula@hotmail.com: Quartus Advisors
    120400: 07/06/06: Mike Treseler: Re: Quartus Advisors
120406: 07/06/06: jasonL: What should be taken care of when two FPGA broad connected together?
    120407: 07/06/06: Andy: Re: What should be taken care of when two FPGA broad connected together?
    120408: 07/06/06: austin: Re: What should be taken care of when two FPGA broad connected together?
    120412: 07/06/06: John_H: Re: What should be taken care of when two FPGA broad connected together?
    120423: 07/06/06: jasonL: Re: What should be taken care of when two FPGA broad connected together?
120410: 07/06/06: Andy Peters: Re: Virtex4 CLKX2 DCM Jitter
120420: 07/06/06: Test01: How many OSERDES per bufio
    120432: 07/06/06: Jim Wu: Re: How many OSERDES per bufio
    120453: 07/06/07: Mavrick: Re: How many OSERDES per bufio
120421: 07/06/06: <antoine.vernay@gmail.com>: FPGA / Virtex II Pro / LWIP
    120431: 07/06/07: Ken Ryan: Re: FPGA / Virtex II Pro / LWIP
        120489: 07/06/08: Ken Ryan: Re: FPGA / Virtex II Pro / LWIP
    120478: 07/06/07: <antoine.vernay@gmail.com>: Re: FPGA / Virtex II Pro / LWIP
    120513: 07/06/08: Patrick Dubois: Re: FPGA / Virtex II Pro / LWIP
120422: 07/06/06: <gseegmiller@gmail.com>: No output while booting ML403 board
    120429: 07/06/06: Peter Ryser: Re: No output while booting ML403 board
    120462: 07/06/07: <gseegmiller@gmail.com>: Re: No output while booting ML403 board
120436: 07/06/07: Grant Stockly: A first FPGA project
    120486: 07/06/08: Mark McDougall: Re: A first FPGA project
    120497: 07/06/07: <cs_posting@hotmail.com>: Re: A first FPGA project
        120503: 07/06/08: Mark McDougall: Re: A first FPGA project
            120540: 07/06/08: Eric Smith: Re: A first FPGA project
                120560: 07/06/10: Mark McDougall: Re: A first FPGA project
                    120598: 07/06/11: Eric Smith: Re: A first FPGA project
120441: 07/06/07: nasif4003@gmail.com: verilog HDL problem
    120445: 07/06/07: Jon Beniston: Re: verilog HDL problem
    120456: 07/06/07: ARH: Re: verilog HDL problem
120442: 07/06/07: Pablo: JTAG as UART for PowerPC in XMD.
    120447: 07/06/07: Pablo: Re: JTAG as UART for PowerPC in XMD.
    120449: 07/06/07: Patrick Dubois: Re: JTAG as UART for PowerPC in XMD.
    120455: 07/06/07: Pablo: Re: JTAG as UART for PowerPC in XMD.
    120460: 07/06/07: Patrick Dubois: Re: JTAG as UART for PowerPC in XMD.
120452: 07/06/07: Mavrick: Lattce SC Purspeed I/O
    120454: 07/06/07: Symon: Re: Lattce SC Purspeed I/O
        120458: 07/06/07: austin: Re: Lattce SC Purspeed I/O
            120469: 07/06/07: <lb.edc@telenet.be>: Re: Lattce SC Purspeed I/O
                120472: 07/06/07: John_H: Re: Lattce SC Purspeed I/O
                    120526: 07/06/08: <lb.edc@telenet.be>: Re: Lattce SC Purspeed I/O
                120475: 07/06/07: austin: Re: Lattce SC Purspeed I/O
            120480: 07/06/08: Jim Granville: Re: Lattce SC Purspeed I/O
    120573: 07/06/10: Brian Davis: Re: Lattce SC Purspeed I/O
120466: 07/06/07: Marlboro: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
    120467: 07/06/07: John_H: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
        120471: 07/06/07: John_H: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
            120476: 07/06/07: John_H: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
    120470: 07/06/07: Marlboro: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
    120474: 07/06/07: Marlboro: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120468: 07/06/07: Wojciech Zabolotny: Symbolic names for pll derived clocks in SDC file? (quartus)
    120494: 07/06/07: <dkarchmer@gmail.com>: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
    120495: 07/06/07: <dkarchmer@gmail.com>: Re: Symbolic names for pll derived clocks in SDC file? (quartus)
    120509: 07/06/08: wzab: SOLVED!!! Symbolic names for pll derived clocks in SDC file? (quartus)
120479: 07/06/07: <deleted@googlemail.com>: How can i convert char* / string to sc_lv<16> ?
120481: 07/06/07: Mavrick: LVPECL output skew
    120483: 07/06/07: austin: Re: LVPECL output skew
        120487: 07/06/07: Mavrick: Re: LVPECL output skew
            120490: 07/06/07: austin: Re: LVPECL output skew
        120492: 07/06/07: Bob: Re: LVPECL output skew
            120493: 07/06/07: Mavrick: Re: LVPECL output skew
                120496: 07/06/08: John_H: Re: LVPECL output skew
                    120514: 07/06/08: Mavrick: Re: LVPECL output skew
                120498: 07/06/08: Jim Granville: Re: LVPECL output skew
                120501: 07/06/07: Bob: Re: LVPECL output skew
            120517: 07/06/08: austin: Re: LVPECL output skew
    120536: 07/06/08: Maverick: Re: LVPECL output skew
        120537: 07/06/08: austin: Re: LVPECL output skew
    120570: 07/06/10: Brian Davis: Re: LVPECL output skew
        120622: 07/06/12: Mavrick: Re: LVPECL output skew
    120651: 07/06/12: Brian Davis: Re: LVPECL output skew
120482: 07/06/08: Frank Buss: another Forth CPU design
    120738: 07/06/15: jrh: Re: another Forth CPU design
    120918: 07/06/20: Petter Gustad: Re: another Forth CPU design
        121173: 07/06/27: Frank Buss: Re: another Forth CPU design
            121193: 07/06/28: Jim Granville: Re: another Forth CPU design
                121200: 07/06/28: Frank Buss: Re: another Forth CPU design
                    121203: 07/06/28: Jim Granville: Re: another Forth CPU design
120484: 07/06/08: <willwestward@gmail.com>: Re: Arbiter
    120504: 07/06/08: jtw: Re: Arbiter
        120535: 07/06/08: Walter Roberson: Re: Arbiter
120485: 07/06/07: Jim Wu: Re: How many OSERDES per bufio
120491: 07/06/07: motty: EDK Simulation Problem
    120523: 07/06/08: Mike Treseler: Re: EDK Simulation Problem
        120624: 07/06/12: sjulhes: Re: EDK Simulation Problem
    120538: 07/06/08: motty: Re: EDK Simulation Problem
    120631: 07/06/12: motty: Re: EDK Simulation Problem
    122401: 07/07/26: Daniel Finchelstein: Re: EDK Simulation Problem
120500: 07/06/07: Frank: HELP with Asynch RAM
    120502: 07/06/07: ARH: Re: HELP with Asynch RAM
    120518: 07/06/08: Duth: Re: HELP with Asynch RAM
120506: 07/06/08: cutemonster: adaptive filter FPGA
    120542: 07/06/09: MM: Re: adaptive filter FPGA
        120561: 07/06/10: cutemonster: Re: adaptive filter FPGA
            120564: 07/06/10: cutemonster: Re: adaptive filter FPGA
                120606: 07/06/11: Spiros Lakkos: Re: adaptive filter FPGA
                    120637: 07/06/12: cutemonster: Re: adaptive filter FPGA
                120689: 07/06/13: cutemonster: Re: adaptive filter FPGA
                    120713: 07/06/14: cutemonster: Re: adaptive filter FPGA
                        120725: 07/06/14: cutemonster: Re: adaptive filter FPGA
    120563: 07/06/10: Marlboro: Re: adaptive filter FPGA
    120647: 07/06/12: Marlboro: Re: adaptive filter FPGA
    120690: 07/06/13: Marlboro: Re: adaptive filter FPGA
    120719: 07/06/14: Marlboro: Re: adaptive filter FPGA
120508: 07/06/08: <fpga.vhdl.designer@gmail.com>: Pin Capacitance Quartus 6.0
    120628: 07/06/12: Paul Leventis: Re: Pin Capacitance Quartus 6.0
120511: 07/06/08: wzab: TimeQuest - clocks related by default?
    120541: 07/06/08: <dkarchmer@gmail.com>: Re: TimeQuest - clocks related by default?
120516: 07/06/08: David Tweed: XST net splitting blocks placement
    120546: 07/06/09: Brian Drummond: Re: XST net splitting blocks placement
        120567: 07/06/10: MikeJ: Re: XST net splitting blocks placement
            120579: 07/06/11: David Tweed: Re: XST net splitting blocks placement
                120596: 07/06/11: MikeJ: Re: XST net splitting blocks placement
                    120822: 07/06/18: David Tweed: Re: XST net splitting blocks placement
    120572: 07/06/10: Brian Davis: Re: XST net splitting blocks placement
120519: 07/06/08: Antti: FPGA with ARM+CAN+USB+ethernet+ADC
    120520: 07/06/08: Sean Durkin: Re: FPGA with ARM+CAN+USB+ethernet+ADC
    120524: 07/06/08: Ed McGettigan: Re: FPGA with ARM+CAN+USB+ethernet+ADC
    120528: 07/06/08: Antti: Re: FPGA with ARM+CAN+USB+ethernet+ADC
    120550: 07/06/09: fpgabuilder: Re: FPGA with ARM+CAN+USB+ethernet+ADC
120521: 07/06/08: Pasacco: Module LOCK possible in VHDL?
120522: 07/06/08: Daveb: PBGA FPGA in hi-rel application
    120577: 07/06/11: dalai lamah: Re: PBGA FPGA in hi-rel application
120527: 07/06/08: bart: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120529: 07/06/08: Antti: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
        120545: 07/06/09: Sean Durkin: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
            120555: 07/06/10: Jim Granville: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
        120686: 07/06/13: Joerg: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
            120717: 07/06/14: rickman: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
                120727: 07/06/14: Joerg: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
            120718: 07/06/14: Didi: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
            120728: 07/06/14: Didi: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120548: 07/06/09: Antti: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120559: 07/06/10: Antti: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120626: 07/06/12: bart: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120632: 07/06/12: Antti: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120644: 07/06/12: bart: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
    120664: 07/06/13: rickman: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
120530: 07/06/08: <freeagent.20.oracle@xoxy.net>: Newbie Question: Using Includes in Verilog
    120531: 07/06/08: John_H: Re: Newbie Question: Using Includes in Verilog
    120532: 07/06/08: tersono: Re: Newbie Question: Using Includes in Verilog
    120533: 07/06/08: <freeagent.20.oracle@xoxy.net>: Re: Newbie Question: Using Includes in Verilog
120534: 07/06/08: <willwestward@gmail.com>: Re: Arbiter
120539: 07/06/08: motty: Another EDK Sim question...
120543: 07/06/09: Olaf: linux and USB JTAG at Spartan 3e starter
    120552: 07/06/09: Olaf: Re: linux and USB JTAG at Spartan 3e starter
        120553: 07/06/09: Olaf: Re: linux and USB JTAG at Spartan 3e starter
    120554: 07/06/09: Michael Gernoth: Re: linux and USB JTAG at Spartan 3e starter
        120558: 07/06/10: Olaf: Re: linux and USB JTAG at Spartan 3e starter
120544: 07/06/09: Alex Gibson: Affordable pcie card ?
    120547: 07/06/09: Brian Drummond: Re: Affordable pcie card ?
    120549: 07/06/09: John_H: Re: Affordable pcie card ?
    120566: 07/06/10: Nico Coesel: Re: Affordable pcie card ?
    120571: 07/06/10: Colin Hankins: Re: Affordable pcie card ?
    120585: 07/06/11: Charles Steinkuehler: Re: Affordable pcie card ?
    120619: 07/06/12: Manfred Kraus: Re: Affordable pcie card ?
120551: 07/06/09: Olaf: xilinx windrv install on linux
    120557: 07/06/10: Ken Ryan: Re: xilinx windrv install on linux
120556: 07/06/09: <willwestward@gmail.com>: Re: Arbiter
120562: 07/06/10: John Adair: Spartan3A-DSP Development Board
120568: 07/06/11: Tom: ANNOUNCE: Atom 2007.06
120569: 07/06/11: lyra: Re: Altera FPGA programming problem.
120575: 07/06/10: Brian Davis: DVI-D Tx directly from FPGA?
    120595: 07/06/11: MikeJ: Re: DVI-D Tx directly from FPGA?
        120669: 07/06/13: MikeJ: Re: DVI-D Tx directly from FPGA?
    120599: 07/06/11: Eric Smith: Re: DVI-D Tx directly from FPGA?
        120658: 07/06/13: MikeJ: Re: DVI-D Tx directly from FPGA?
    120649: 07/06/12: Brian Davis: Re: DVI-D Tx directly from FPGA?
    120661: 07/06/13: Erik Widding: Re: DVI-D Tx directly from FPGA?
    120667: 07/06/13: ZR1TECH: Re: DVI-D Tx directly from FPGA?
120576: 07/06/11: Yao Sics: How to put part of program data into local ram, the rest into external memroy?
    120605: 07/06/11: Vasanth Asokan: Re: How to put part of program data into local ram, the rest into external memroy?
    120609: 07/06/11: Yao Sics: Re: How to put part of program data into local ram, the rest into external memroy?
120578: 07/06/11: Wei Wang: synthesis - design compiler or synplify pro?
    120580: 07/06/11: Jon Beniston: Re: synthesis - design compiler or synplify pro?
    120582: 07/06/11: Andy: Re: synthesis - design compiler or synplify pro?
    120593: 07/06/11: Wei Wang: Re: synthesis - design compiler or synplify pro?
    120607: 07/06/11: Andy: Re: synthesis - design compiler or synplify pro?
        120687: 07/06/13: Wei Wang: Re: synthesis - design compiler or synplify pro?
        120702: 07/06/14: Jon Beniston: Re: synthesis - design compiler or synplify pro?
120583: 07/06/11: Jorge: EDK 9.1 + Virtex 5 Hard MAC
    120600: 07/06/11: Eric Smith: Re: EDK 9.1 + Virtex 5 Hard MAC
120584: 07/06/11: <cs_posting@hotmail.com>: Re: Altera FPGA programming problem.
120586: 07/06/11: Pablo: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120611: 07/06/12: sjulhes: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
        120623: 07/06/12: sjulhes: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120612: 07/06/12: Pablo: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120613: 07/06/12: Pablo: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
    120625: 07/06/12: Pablo: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
120587: 07/06/11: Nial Stewart: Unused clock pins tied inactive?
    120591: 07/06/11: John_H: Re: Unused clock pins tied inactive?
        120659: 07/06/13: Symon: Re: Unused clock pins tied inactive?
        120671: 07/06/13: Nial Stewart: Re: Unused clock pins tied inactive?
    120627: 07/06/12: Paul Leventis: Re: Unused clock pins tied inactive?
    120660: 07/06/13: KJ: Re: Unused clock pins tied inactive?
120588: 07/06/11: <eryksson@gmail.com>: Unexpected resources utilization
    120589: 07/06/11: mk: Re: Unexpected resources utilization
    120601: 07/06/11: <eryksson@gmail.com>: Re: Unexpected resources utilization
120594: 07/06/11: motty: EDK Sim: BRAM won't init
    120602: 07/06/11: motty: Re: EDK Sim: BRAM won't init
120603: 07/06/11: Ji Soon Kim: Help with T-VPACK
120604: 07/06/11: Roger: Optical RocketIO
    120608: 07/06/11: johnp: Re: Optical RocketIO
    120706: 07/06/14: tullio: Re: Optical RocketIO
120610: 07/06/11: <Amine.Miled@gmail.com>: Power consumption problem
    120614: 07/06/12: Jim Granville: Re: Power consumption problem
        120646: 07/06/13: Jim Granville: Re: Power consumption problem
    120638: 07/06/12: <Amine.Miled@gmail.com>: Re: Power consumption problem
    120793: 07/06/16: <Amine.Miled@gmail.com>: Re: Power consumption problem
120615: 07/06/12: NickNitro: UK shop - FPGA boards + chips.
    120616: 07/06/12: Sylvain Munaut: Re: UK shop - FPGA boards + chips.
        120621: 07/06/12: John Adair: Re: UK shop - FPGA boards + chips.
    120654: 07/06/12: NickNitro: Re: UK shop - FPGA boards + chips.
120617: 07/06/12: Pablo: Apart from IEEE, is there some another journals for publishing an FPGA article?
    120620: 07/06/12: Colin Paul Gloster: Re: Apart from IEEE, is there some another journals for publishing an FPGA article?
        120629: 07/06/12: Kevin Neilson: Re: Apart from IEEE, is there some another journals for publishing
120630: 07/06/12: emu: xilinx spartan3e kit ddr sdram
    120643: 07/06/12: Kishore: Re: xilinx spartan3e kit ddr sdram
    120650: 07/06/12: Eric Smith: Re: xilinx spartan3e kit ddr sdram
120633: 07/06/12: jai.dhar@gmail.com: TDM stream multiplex/demultiplex
120634: 07/06/12: Rohan: Programming Question
    120636: 07/06/12: John_H: Re: Programming Question
    120778: 07/06/16: Sachin: Re: Programming Question
120635: 07/06/12: Rohan: Programming Question
120639: 07/06/12: johnp: XIlinx tools question - how to quickly identify unconstrained paths
    120640: 07/06/12: Mike Treseler: Re: XIlinx tools question - how to quickly identify unconstrained
    120641: 07/06/12: johnp: Re: XIlinx tools question - how to quickly identify unconstrained paths
    120645: 07/06/12: Nico Coesel: Re: XIlinx tools question - how to quickly identify unconstrained paths
    120648: 07/06/12: johnp: Re: XIlinx tools question - how to quickly identify unconstrained paths
120642: 07/06/12: Nobody Here: Virtex-4 pre-configuration pull-ups
    120776: 07/06/16: Sachin: Re: Virtex-4 pre-configuration pull-ups
    120777: 07/06/16: Sachin: Re: Virtex-4 pre-configuration pull-ups
        120780: 07/06/16: Nobody Here: Re: Virtex-4 pre-configuration pull-ups
            120785: 07/06/16: austin: Re: Virtex-4 pre-configuration pull-ups
                120790: 07/06/16: Nobody Here: Re: Virtex-4 pre-configuration pull-ups
120652: 07/06/13: Tommy Thorn: Stolen Spartan 3E-1600 Development Board
    120653: 07/06/12: Bob: Re: Stolen Spartan 3E-1600 Development Board
        120663: 07/06/13: John Adair: Re: Stolen Spartan 3E-1600 Development Board
    120754: 07/06/15: radarman: Re: Stolen Spartan 3E-1600 Development Board
    120760: 07/06/15: Marlboro: Re: Stolen Spartan 3E-1600 Development Board
120655: 07/06/13: vasile: Virtex 5 static and dynamic (re)configuration
    120656: 07/06/12: mh: Re: Virtex 5 static and dynamic (re)configuration
120657: 07/06/12: Pablo Bleyer Kocik: KCAsm beta
120662: 07/06/13: J.Ram: programming virtex2 FPGA
    120665: 07/06/13: Symon: Re: programming virtex2 FPGA
    120678: 07/06/13: davide: Re: programming virtex2 FPGA
        120721: 07/06/14: davide: Re: programming virtex2 FPGA
    120701: 07/06/13: J.Ram: Re: programming virtex2 FPGA
120666: 07/06/13: MikeJ: Frogger and Scramble released
    120674: 07/06/14: Mark McDougall: Re: Frogger and Scramble released
        120683: 07/06/13: MikeJ: Re: Frogger and Scramble released
120668: 07/06/13: ZR1TECH: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
    120672: 07/06/13: Jonathan Bromley: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
        120681: 07/06/13: Symon: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
        120682: 07/06/13: Mike Treseler: Re: Newbie questions: Can I do this PLL all digitally in a FPGA?
    120675: 07/06/13: ZR1TECH: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
    120677: 07/06/13: ZR1TECH: Re: Newbie questions: Can I do this PLL all digitally in a FPGA? 8Khz clock locked on a 100hz pulse
120670: 07/06/13: maxascent: Virtex 4 Config
    120680: 07/06/13: davide: Re: Virtex 4 Config
        120740: 07/06/15: maxascent: Re: Virtex 4 Config
            120765: 07/06/15: davide: Re: Virtex 4 Config
                120779: 07/06/16: maxascent: Re: Virtex 4 Config
120673: 07/06/13: <tlenomade@googlemail.com>: how to speed up the write to the off chip ram
120676: 07/06/13: Amontec, Larry: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120707: 07/06/14: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120711: 07/06/14: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120821: 07/06/18: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
        120968: 07/06/21: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
            120977: 07/06/21: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
            120981: 07/06/21: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
                121055: 07/06/24: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
            120987: 07/06/21: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
                121053: 07/06/24: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120866: 07/06/19: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120867: 07/06/19: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120870: 07/06/19: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120871: 07/06/19: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120872: 07/06/19: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120873: 07/06/19: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120874: 07/06/19: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120973: 07/06/21: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
        121431: 07/07/04: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
            122367: 07/07/26: Amontec, Larry: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120974: 07/06/21: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120976: 07/06/21: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120982: 07/06/21: <cs_posting@hotmail.com>: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120985: 07/06/21: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120989: 07/06/21: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    120990: 07/06/21: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    121074: 07/06/25: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
    121075: 07/06/25: Antti: Re: ANN: Amontec JTAGkey programs XC4VLX25 at 2.8s
120684: 07/06/13: Pablo: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
    120685: 07/06/13: MM: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
        120720: 07/06/14: MM: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
            120744: 07/06/15: MM: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
    120712: 07/06/14: Pablo: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
    120739: 07/06/15: Pablo: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
    120750: 07/06/15: Pablo: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
    120843: 07/06/18: emu: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120691: 07/06/13: jjlindula@hotmail.com: Incremental Compilation in Altera Quartus II version 7.1
    120693: 07/06/13: Mike Treseler: Re: Incremental Compilation in Altera Quartus II version 7.1
    120715: 07/06/14: jjlindula@hotmail.com: Re: Incremental Compilation in Altera Quartus II version 7.1
120692: 07/06/13: Andrea05: custom peripheral registers
    120697: 07/06/13: <cs_posting@hotmail.com>: Re: custom peripheral registers
    120698: 07/06/13: motty: Re: custom peripheral registers
    120699: 07/06/13: motty: Re: custom peripheral registers
    120700: 07/06/13: radarman: Re: custom peripheral registers
    120837: 07/06/18: Andrea05: Re: custom peripheral registers
120694: 07/06/13: Pete Fraser: ISE write permissions?
    120695: 07/06/13: davide: Re: ISE write permissions?
        120696: 07/06/13: Pete Fraser: Re: ISE write permissions?
            120722: 07/06/14: davide: Re: ISE write permissions?
120704: 07/06/14: Joe: LogicSim v3.0 Verilog Simulator is Here!
120705: 07/06/14: <rajivc53@gmail.com>: c code to initialize a peripheral
    120714: 07/06/14: <cs_posting@hotmail.com>: Re: c code to initialize a peripheral
        120729: 07/06/15: John Williams: Re: c code to initialize a peripheral
    120730: 07/06/14: <cs_posting@hotmail.com>: Re: c code to initialize a peripheral
    120737: 07/06/15: Uncle Noah: Re: c code to initialize a peripheral
    120742: 07/06/15: <cs_posting@hotmail.com>: Re: c code to initialize a peripheral
120708: 07/06/14: FPGA Guy: problems with FSL and Microblaze
    120709: 07/06/14: <sunwei1688@gmail.com>: Re: problems with FSL and Microblaze
    120710: 07/06/14: motty: Re: problems with FSL and Microblaze
    120724: 07/06/14: morphiend: Re: problems with FSL and Microblaze
    120819: 07/06/18: FPGA Guy: Re: problems with FSL and Microblaze
120716: 07/06/14: jjlindula@hotmail.com: Using LogicLock in Altera Quartus II
    120783: 07/06/16: Ben Twijnstra: Re: Using LogicLock in Altera Quartus II
    120789: 07/06/16: fpgabuilder: Re: Using LogicLock in Altera Quartus II
120723: 07/06/14: Zorjak: Quartus Timing Analyzer question
    120756: 07/06/15: <dkarchmer@gmail.com>: Re: Quartus Timing Analyzer question
    120773: 07/06/15: Zorjak: Re: Quartus Timing Analyzer question
    120794: 07/06/16: Zorjak: Re: Quartus Timing Analyzer question
    120828: 07/06/18: <dkarchmer@gmail.com>: Re: Quartus Timing Analyzer question
    120907: 07/06/20: Zorjak: Re: Quartus Timing Analyzer question
120726: 07/06/14: Netoko Young: What is LatticeSC implementation of Virtex-4 ISERDES and OSERDES
120732: 07/06/15: mahalingamv@gmail.com: edk clock problem
    120834: 07/06/18: mahalingamv@gmail.com: Re: edk clock problem
120733: 07/06/15: Jeff Cunningham: booting a large V4 PPC program with a minimum of on chip bram
    120735: 07/06/15: Ben Jackson: Re: booting a large V4 PPC program with a minimum of on chip bram
        120743: 07/06/15: Jeff Cunningham: Re: booting a large V4 PPC program with a minimum of on chip bram
            120767: 07/06/15: leevv: Re: booting a large V4 PPC program with a minimum of on chip
                120774: 07/06/15: Jeff Cunningham: Re: booting a large V4 PPC program with a minimum of on chip bram
                    120786: 07/06/16: leevv: Re: booting a large V4 PPC program with a minimum of on chip
                        120813: 07/06/18: Jeff Cunningham: Re: booting a large V4 PPC program with a minimum of on chip bram
            120771: 07/06/15: Jeff Cunningham: Re: booting a large V4 PPC program with a minimum of on chip bram
    120749: 07/06/15: <jetmarc@hotmail.com>: Re: booting a large V4 PPC program with a minimum of on chip bram
120734: 07/06/15: Jeff Cunningham: How to make a small (<4Kbyte) program for V4 PPC
    120736: 07/06/15: Andreas Hofmann: Re: How to make a small (<4Kbyte) program for V4 PPC
        120741: 07/06/15: Jeff Cunningham: Re: How to make a small (<4Kbyte) program for V4 PPC
            120746: 07/06/15: Sylvain Munaut: Re: How to make a small (<4Kbyte) program for V4 PPC
                120768: 07/06/15: Jeff Cunningham: Re: How to make a small (<4Kbyte) program for V4 PPC
120745: 07/06/15: Chris@Austin: help on clock fowarding between 2 FPGAs
    120751: 07/06/15: Nico Coesel: Re: help on clock fowarding between 2 FPGAs
        120761: 07/06/15: Kuo: Re: help on clock fowarding between 2 FPGAs
    120782: 07/06/16: Brian Drummond: Re: help on clock fowarding between 2 FPGAs
        120829: 07/06/18: Kuo: Re: help on clock fowarding between 2 FPGAs
            120831: 07/06/18: austin: Re: help on clock fowarding between 2 FPGAs
120747: 07/06/15: ChrisKuo@Austin: Need help on clock forwarding on Xilinx Virtex-5
120748: 07/06/15: Kuo: Help on clock forwarding with Virtex-5
120752: 07/06/15: rob.dimond@gmail.com: Xilinx FPGA Pinout spreadsheets
    120757: 07/06/15: Symon: Re: Xilinx FPGA Pinout spreadsheets
        120759: 07/06/15: Sean Durkin: Re: Xilinx FPGA Pinout spreadsheets
    120791: 07/06/16: Andrew Holme: Re: Xilinx FPGA Pinout spreadsheets
    120824: 07/06/18: Jim Wu: Re: Xilinx FPGA Pinout spreadsheets
    120826: 07/06/18: colin: Re: Xilinx FPGA Pinout spreadsheets
120753: 07/06/15: cutemonster: what is the correct way to capture ADC using fpga
    120755: 07/06/15: John_H: Re: what is the correct way to capture ADC using fpga
        120764: 07/06/15: cutemonster: Re: what is the correct way to capture ADC using fpga
            120769: 07/06/15: John_H: Re: what is the correct way to capture ADC using fpga
        120792: 07/06/16: John_H: Re: what is the correct way to capture ADC using fpga
            120804: 07/06/17: John_H: Re: what is the correct way to capture ADC using fpga
    120788: 07/06/16: fpgabuilder: Re: what is the correct way to capture ADC using fpga
    120802: 07/06/17: fpgabuilder: Re: what is the correct way to capture ADC using fpga
    120876: 07/06/19: fpgabuilder: Re: what is the correct way to capture ADC using fpga
120766: 07/06/15: morphiend: V4FX and Microblaze 5.00.c hard multiplier not working
120770: 07/06/15: morphiend: V4FX60, hard temac, MPMC2 and SoDIMM
    120827: 07/06/18: MM: Re: V4FX60, hard temac, MPMC2 and SoDIMM
120772: 07/06/16: Richard Klingler: ispLever 7.0
120775: 07/06/15: Manny: Simulating analogue signal using ISE simulator
    120787: 07/06/16: Mike Treseler: Re: Simulating analogue signal using ISE simulator
    120795: 07/06/16: Manny: Re: Simulating analogue signal using ISE simulator
120781: 07/06/16: Fred: EDK - Microblaze question
    120796: 07/06/16: Eric Smith: Re: EDK - Microblaze question
    120806: 07/06/17: Steve at fivetrees: Re: EDK - Microblaze question
    120901: 07/06/19: Vasanth Asokan: Re: EDK - Microblaze question
        120943: 07/06/20: Fred: Re: EDK - Microblaze question
            121060: 07/06/24: PFC: Re: EDK - Microblaze question
120784: 07/06/16: Pasacco: How to measure clock fequency
120797: 07/06/17: <jonyt@eng.tau.ac.il>: anyone know a FPGA designer?
    120799: 07/06/17: Totally_Lost: Re: anyone know a FPGA designer?
    120800: 07/06/17: Symon: Re: anyone know a FPGA designer?
    120801: 07/06/17: Frank Buss: Re: anyone know a FPGA designer?
    120814: 07/06/17: John Adair: Re: anyone know a FPGA designer?
    120815: 07/06/18: Jim Granville: Re: anyone know a FPGA designer?
    120818: 07/06/18: comp.arch.fpga: Re: anyone know a FPGA designer?
120798: 07/06/17: Al: fitting problem on A54SX72A
    120803: 07/06/17: Mike Treseler: Re: fitting problem on A54SX72A
        120817: 07/06/18: Al: Re: fitting problem on A54SX72A
            120820: 07/06/18: Al: Re: fitting problem on A54SX72A
    120838: 07/06/18: Alvin Andries: Re: fitting problem on A54SX72A
        120857: 07/06/19: Al: Re: fitting problem on A54SX72A
            120897: 07/06/19: Alvin Andries: Re: fitting problem on A54SX72A
120805: 07/06/17: Islam Ossama: Help configuring XUP PPC for Ethernet
    120882: 07/06/19: Siva Velusamy: Re: Help configuring XUP PPC for Ethernet
120807: 07/06/17: freeplatypus: Graduate/Junior FPGA Designer concerns
    120810: 07/06/17: austin: Re: Graduate/Junior FPGA Designer concerns
    120860: 07/06/19: fabbl: Re: Graduate/Junior FPGA Designer concerns
    120903: 07/06/19: Totally_Lost: Re: Graduate/Junior FPGA Designer concerns
        121121: 07/06/26: Michael Jørgensen: Re: Graduate/Junior FPGA Designer concerns
        121122: 07/06/26: Michael Jørgensen: Re: Graduate/Junior FPGA Designer concerns
    120919: 07/06/20: freeplatypus: Re: Graduate/Junior FPGA Designer concerns
    120922: 07/06/20: Christian Kirschenlohr: Re: Graduate/Junior FPGA Designer concerns
120808: 07/06/17: Ankit: How to simulate testbenches using the ISE simulator in linux
    120832: 07/06/18: Mike Treseler: Re: How to simulate testbenches using the ISE simulator in linux
        120880: 07/06/19: HT-Lab: Re: How to simulate testbenches using the ISE simulator in linux
    120835: 07/06/18: Duth: Re: How to simulate testbenches using the ISE simulator in linux
    120840: 07/06/18: Duth: Re: How to simulate testbenches using the ISE simulator in linux
    120853: 07/06/19: <rponsard@gmail.com>: Re: How to simulate testbenches using the ISE simulator in linux
    120858: 07/06/19: Ankit: Re: How to simulate testbenches using the ISE simulator in linux
    120868: 07/06/19: Guenter: Re: How to simulate testbenches using the ISE simulator in linux
    120875: 07/06/19: Duth: Re: How to simulate testbenches using the ISE simulator in linux
    120883: 07/06/19: Ankit: Re: How to simulate testbenches using the ISE simulator in linux
    120928: 07/06/20: Duth: Re: How to simulate testbenches using the ISE simulator in linux
    120931: 07/06/20: Ankit: Re: How to simulate testbenches using the ISE simulator in linux
    120983: 07/06/21: Ankit: Re: How to simulate testbenches using the ISE simulator in linux
    121018: 07/06/22: Ankit: Re: How to simulate testbenches using the ISE simulator in linux
120809: 07/06/17: Gabor: Xpower complains about Vccint for Spartan 3A
    120811: 07/06/17: austin: Re: Xpower complains about Vccint for Spartan 3A
        120830: 07/06/18: austin: Re: Xpower complains about Vccint for Spartan 3A
    120812: 07/06/17: Gabor: Re: Xpower complains about Vccint for Spartan 3A
120816: 07/06/18: cutemonster: how to assert PSEN for DCM
    120825: 07/06/18: motty: Re: how to assert PSEN for DCM
120823: 07/06/18: Laurent Pinchart: Enumerated type simulation issue (ISE simulator, 9.1.03i)
    120833: 07/06/18: Duth: Re: Enumerated type simulation issue (ISE simulator, 9.1.03i)
    120839: 07/06/18: Duth: Re: Enumerated type simulation issue (ISE simulator, 9.1.03i)
120836: 07/06/18: <gseegmiller@gmail.com>: No serial output while booting a Xilinx ML403 board
    120852: 07/06/18: Lasse Eriksson: Re: No serial output while booting a Xilinx ML403 board
    120885: 07/06/19: <gseegmiller@gmail.com>: Re: No serial output while booting a Xilinx ML403 board
120841: 07/06/18: <karthiknatrajan@gmail.com>: Help needed regarding addition of Custom IP core to EDK
    120847: 07/06/18: motty: Re: Help needed regarding addition of Custom IP core to EDK
    120851: 07/06/19: <karthiknatrajan@gmail.com>: Re: Help needed regarding addition of Custom IP core to EDK
    120899: 07/06/19: motty: Re: Help needed regarding addition of Custom IP core to EDK
120842: 07/06/18: cutemonster: want to pay for DCM active phase shift controller.
    120844: 07/06/18: johnp: Re: want to pay for DCM active phase shift controller.
    120848: 07/06/18: motty: Re: want to pay for DCM active phase shift controller.
    120863: 07/06/19: <pontus.stenstrom@gmail.com>: Re: want to pay for DCM active phase shift controller.
        120877: 07/06/19: cutemonster: Re: want to pay for DCM active phase shift controller.
    120894: 07/06/19: motty: Re: want to pay for DCM active phase shift controller.
120845: 07/06/18: Maverick: .xco file and vcs verilog compiler
    120864: 07/06/19: Gabor: Re: .xco file and vcs verilog compiler
    120892: 07/06/19: Jim Wu: Re: .xco file and vcs verilog compiler
120846: 07/06/18: motty: V5 GTP Sim Problem
    120849: 07/06/18: muruganandam.m@gmail.com: Re: V5 GTP Sim Problem
    120893: 07/06/19: motty: Re: V5 GTP Sim Problem
120850: 07/06/18: Saumil Merchant: XPower: Can't change activity rates
120854: 07/06/19: <rponsard@gmail.com>: spartan 3A : DDR2 controller
    120859: 07/06/19: Antti: Re: spartan 3A : DDR2 controller
120855: 07/06/19: <rbmm756@gmail.com>: How do i add my IP to EDK?
    120856: 07/06/19: <rponsard@gmail.com>: Re: How do i add my IP to EDK?
    120887: 07/06/19: <HurleyBP@gmail.com>: Re: How do i add my IP to EDK?
120861: 07/06/19: Pablo: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
    120862: 07/06/19: Antti: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
    120878: 07/06/19: Pablo: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
    120890: 07/06/19: <HurleyBP@gmail.com>: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
120865: 07/06/19: Jeremie: Rocketio connection Virtex2pro-Virtex4
    121403: 07/07/03: Patrick Dubois: Re: Rocketio connection Virtex2pro-Virtex4
    121480: 07/07/05: beeraka@gmail.com: Re: Rocketio connection Virtex2pro-Virtex4
    121552: 07/07/08: Ken Ryan: Re: Rocketio connection Virtex2pro-Virtex4
120869: 07/06/19: Vince: SystemC - Libero IDE
    120879: 07/06/19: HT-Lab: Re: SystemC - Libero IDE
    120884: 07/06/19: Vince: Re: SystemC - Libero IDE
120881: 07/06/19: Kuo: synthesis translate_off
    120900: 07/06/19: Tim (one of many): Re: synthesis translate_off
120886: 07/06/19: kislo: Weird behavior in debuggin using XMD
    120905: 07/06/20: Zara: Re: Weird behavior in debuggin using XMD
120888: 07/06/19: Patrick Dubois: MIG for Virtex-4 DDR dimm, only 165 Hz?
    120920: 07/06/20: subint: Re: MIG for Virtex-4 DDR dimm, only 165 Hz?
    120933: 07/06/20: Patrick Dubois: Re: MIG for Virtex-4 DDR dimm, only 165 Hz?
120889: 07/06/19: cpope: V4 PPC to sleep?
120891: 07/06/19: Pasacco: [ISE] how to synthesize XilinxProcessorIP/pcore
120895: 07/06/19: <csisterna@hotmail.com>: noisy rising edge clock - non-monotonic clock
    120896: 07/06/19: Symon: Re: noisy rising edge clock - non-monotonic clock
    120898: 07/06/19: austin: Re: noisy rising edge clock - non-monotonic clock
120902: 07/06/20: John Williams: [Announce] Linux 2.6.20 on MicroBlaze now available
    120917: 07/06/20: Guru: Re: Linux 2.6.20 on MicroBlaze now available
        120921: 07/06/20: Ben Jones: Re: Linux 2.6.20 on MicroBlaze now available
            120946: 07/06/21: John Williams: Re: Linux 2.6.20 on MicroBlaze now available
    120923: 07/06/20: stephen.craven@gmail.com: Re: Linux 2.6.20 on MicroBlaze now available
    120927: 07/06/20: <rponsard@gmail.com>: Re: Linux 2.6.20 on MicroBlaze now available
120904: 07/06/19: hitsx@hit.edu.cn: Interesting problems about high performance computing
    120906: 07/06/19: Totally_Lost: Re: Interesting problems about high performance computing
        121010: 07/06/21: Marc Battyani: Re: Interesting problems about high performance computing
            121017: 07/06/22: Colin Paul Gloster: Re: Interesting problems about high performance computing
        121610: 07/07/09: glen herrmannsfeldt: Re: Interesting problems about high performance computing
            121615: 07/07/10: PFC: Re: Interesting problems about high performance computing
            122636: 07/08/01: glen herrmannsfeldt: Re: Interesting problems about high performance computing
    120913: 07/06/20: Christian Kirschenlohr: Re: Interesting problems about high performance computing
    120924: 07/06/20: <evansamuel@charter.net>: Re: Interesting problems about high performance computing
    120932: 07/06/20: John Adair: Re: Interesting problems about high performance computing
    120942: 07/06/20: glen herrmannsfeldt: Re: Interesting problems about high performance computing
    120952: 07/06/21: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    120953: 07/06/21: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    121015: 07/06/21: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    121016: 07/06/21: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    121029: 07/06/22: Totally_Lost: Re: Interesting problems about high performance computing
    121031: 07/06/22: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    121069: 07/06/24: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
    121910: 07/07/15: hitsx@hit.edu.cn: Re: Interesting problems about high performance computing
120908: 07/06/20: Jay: How to use UART on Spartan 3E Starter Kit
    120909: 07/06/20: Antti: Re: How to use UART on Spartan 3E Starter Kit
    120911: 07/06/20: Jay: Re: How to use UART on Spartan 3E Starter Kit
    120926: 07/06/20: <rponsard@gmail.com>: Re: How to use UART on Spartan 3E Starter Kit
    121290: 07/06/30: <mitch.hayenga@gmail.com>: Re: How to use UART on Spartan 3E Starter Kit
120912: 07/06/20: Uwe Bonnes: DFS to generate Frequencies slightly apart
    120915: 07/06/20: Symon: Re: DFS to generate Frequencies slightly apart
        120916: 07/06/20: Symon: Re: DFS to generate Frequencies slightly apart
    120930: 07/06/20: John Adair: Re: DFS to generate Frequencies slightly apart
120914: 07/06/20: Marek Kraft: Suggestions for Xilinx based evaluation board for image processing
    120925: 07/06/20: Pete Fraser: Re: Suggestions for Xilinx based evaluation board for image processing
    120929: 07/06/20: John Adair: Re: Suggestions for Xilinx based evaluation board for image processing
    120939: 07/06/20: Andy Peters: Re: Suggestions for Xilinx based evaluation board for image processing
    120940: 07/06/20: austin: Re: Suggestions for Xilinx based evaluation board for image processing
    120951: 07/06/21: mh: Re: Suggestions for Xilinx based evaluation board for image processing
120934: 07/06/20: hammouda: ML402 card (video starter kit) : Read/write on the ddr
    120937: 07/06/20: hammouda: Re: ML402 card (video starter kit) : Read/write on the ddr
120935: 07/06/20: Paul Urbanus: MIG 7.12 DDR2 bank availibility
120936: 07/06/20: RR: Can anyone identify the manufacturer of this Chip ?
    120941: 07/06/20: John_H: Re: Can anyone identify the manufacturer of this Chip ?
    120944: 07/06/20: Winfield Hill: Re: Can anyone identify the manufacturer of this Chip ?
    120945: 07/06/21: larwe: Re: Can anyone identify the manufacturer of this Chip ?
    120947: 07/06/21: Mark McDougall: Re: Can anyone identify the manufacturer of this Chip ?
        120949: 07/06/21: Gene S. Berkowitz: Re: Can anyone identify the manufacturer of this Chip ?
            120950: 07/06/21: Mark McDougall: Re: Can anyone identify the manufacturer of this Chip ?
                120958: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                    120961: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                        120971: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                        120972: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                        120980: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                        120986: 07/06/21: Jan Panteltje: Re: Can anyone identify the manufacturer of this Chip ?
                121012: 07/06/22: Mark McDougall: Re: Can anyone identify the manufacturer of this Chip ?
                121068: 07/06/25: Mark McDougall: Re: Can anyone identify the manufacturer of this Chip ?
    120955: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120959: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120963: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120965: 07/06/21: <cs_posting@hotmail.com>: Re: Can anyone identify the manufacturer of this Chip ?
    120966: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120967: 07/06/21: <cs_posting@hotmail.com>: Re: Can anyone identify the manufacturer of this Chip ?
    120969: 07/06/21: <panteltje@yahoo.com>: Re: Can anyone identify the manufacturer of this Chip ?
    120970: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120975: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120984: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120988: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120991: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    120997: 07/06/21: <cs_posting@hotmail.com>: Re: Can anyone identify the manufacturer of this Chip ?
    120999: 07/06/21: Antti: Re: Can anyone identify the manufacturer of this Chip ?
    121003: 07/06/21: Andy Peters: Re: Can anyone identify the manufacturer of this Chip ?
    121004: 07/06/21: Andy Peters: Re: Can anyone identify the manufacturer of this Chip ?
    121005: 07/06/21: Andy Peters: Re: Can anyone identify the manufacturer of this Chip ?
    121007: 07/06/21: <cs_posting@hotmail.com>: Re: Can anyone identify the manufacturer of this Chip ?
    121019: 07/06/22: <cs_posting@hotmail.com>: Re: Can anyone identify the manufacturer of this Chip ?
    121110: 07/06/25: Imti: Re: Can anyone identify the manufacturer of this Chip ?
120938: 07/06/20: Peter Alfke: Want to become part of Xilinx Applications Engineering ?
120948: 07/06/21: Jim Granville: Achronix Async FPGA Silicon available when ?
120954: 07/06/21: Pablo: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
    120956: 07/06/21: Antti: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
    120957: 07/06/21: Pablo: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
    120960: 07/06/21: Antti: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
    120962: 07/06/21: Pablo: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
    120964: 07/06/21: Antti: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120978: 07/06/21: <fastgreen2000@yahoo.com>: Modelsim simulation Q
    120979: 07/06/21: rob.dimond@gmail.com: Re: Modelsim simulation Q
    121038: 07/06/23: Wei Wang: Re: Modelsim simulation Q
    121086: 07/06/25: <fastgreen2000@yahoo.com>: Re: Modelsim simulation Q
120992: 07/06/21: Frank Buss: Nios II problem
    120993: 07/06/21: Tommy Thorn: Re: Nios II problem
        120994: 07/06/21: Frank Buss: Re: Nios II problem
            120995: 07/06/21: Frank Buss: Re: Nios II problem
    121008: 07/06/21: Marc Battyani: Re: Nios II problem
    121009: 07/06/21: <cs_posting@hotmail.com>: Re: Nios II problem
120996: 07/06/21: <pcplanet@gmx.de>: Virtex 5 Rocketio
    121001: 07/06/21: austin: Re: Virtex 5 Rocketio
        121006: 07/06/21: austin: Re: Virtex 5 Rocketio
    121002: 07/06/21: pc: Re: Virtex 5 Rocketio
    121013: 07/06/21: motty: Re: Virtex 5 Rocketio
120998: 07/06/21: Pete Fraser: Agilent Dynamic Probe?
121014: 07/06/21: Jeff Cunningham: is Ultracontroller-2 supposed to work under XPS/ISE 9.1?
121020: 07/06/22: <cxu_dl@yahoo.com>: How to deal with unavoidable setup time violation in CoolRunner II cpld?
    121021: 07/06/22: <cxu_dl@yahoo.com>: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
        121026: 07/06/22: Mike Treseler: Re: How to deal with unavoidable setup time violation in CoolRunner
    121025: 07/06/22: motty: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
    121027: 07/06/22: Peter Alfke: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
    121033: 07/06/22: <cxu_dl@yahoo.com>: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
    121034: 07/06/22: <cxu_dl@yahoo.com>: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121022: 07/06/22: Amal: Cadence TestBuilder
    121023: 07/06/22: Evan Lavelle: Re: Cadence TestBuilder
        121100: 07/06/25: Evan Lavelle: Re: Cadence TestBuilder
    121024: 07/06/22: Amal: Re: Cadence TestBuilder
    121050: 07/06/24: <ghelbig@lycos.com>: Re: Cadence TestBuilder
121028: 07/06/22: MM: Has anyone seen a vxWorks driver for the Xilinx LL_TEMAC?
121030: 07/06/22: Uwe Bonnes: Xilinx DFS woes
    121037: 07/06/23: Symon: Re: Xilinx DFS woes
        121039: 07/06/23: Uwe Bonnes: Re: Xilinx DFS woes
            121041: 07/06/23: Symon: Re: Xilinx DFS woes
                121043: 07/06/23: Uwe Bonnes: Re: Xilinx DFS woes
                    121044: 07/06/23: Symon: Re: Xilinx DFS woes
                        121046: 07/06/23: Uwe Bonnes: Re: Xilinx DFS woes
121032: 07/06/22: <randomdude@gmail.com>: Reshipping spartan3 PCIE board to England
    121036: 07/06/23: John Adair: Re: Reshipping spartan3 PCIE board to England
    121064: 07/06/24: <randomdude@gmail.com>: Re: Reshipping spartan3 PCIE board to England
121035: 07/06/23: Mohammad Abbas: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the
    121040: 07/06/23: <cs_posting@hotmail.com>: Re: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
    121148: 07/06/26: <i_s_uzun@yahoo.com>: Re: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the FPGA!!!|!!|!|!|!|!|!|!|!
121042: 07/06/23: <xtr>: How to create simple design?
    121058: 07/06/24: <evansamuel@charter.net>: Re: How to create simple design?
        121078: 07/06/25: <xtr>: Re: How to create simple design?
            121157: 07/06/27: <evansamuel@charter.net>: Re: How to create simple design?
                121208: 07/06/28: <xtr>: Re: How to create simple design?
                    121224: 07/06/28: <evansamuel@charter.net>: Re: How to create simple design?
121045: 07/06/23: cpope: corgen cic = terrible efficiency?
    121082: 07/06/25: Jon Beniston: Re: corgen cic = terrible efficiency?
        121093: 07/06/25: cpope: Re: corgen cic = terrible efficiency?
            121178: 07/06/27: Ray Andraka: Re: corgen cic = terrible efficiency?
                121182: 07/06/27: cpope: Re: corgen cic = terrible efficiency?
                    121184: 07/06/27: Ray Andraka: Re: corgen cic = terrible efficiency?
                        121188: 07/06/27: cpope: Re: corgen cic = terrible efficiency?
                            121191: 07/06/27: Ray Andraka: Re: corgen cic = terrible efficiency?
    121088: 07/06/25: comp.arch.fpga: Re: corgen cic = terrible efficiency?
        121091: 07/06/25: cpope: Re: corgen cic = terrible efficiency?
    121176: 07/06/27: Ray Andraka: Re: corgen cic = terrible efficiency?
        121183: 07/06/27: cpope: Re: corgen cic = terrible efficiency?
121047: 07/06/23: eromlignod: Substitute for FORK / JOIN?
    121048: 07/06/23: Jonathan Bromley: Re: Substitute for FORK / JOIN?
    121052: 07/06/24: vssumesh: Re: Substitute for FORK / JOIN?
121049: 07/06/23: Vimal: IBIS Model V5 GTP output
    121051: 07/06/24: Sean Durkin: Re: IBIS Model V5 GTP output
        121056: 07/06/24: Vimal: Re: IBIS Model V5 GTP output
            121061: 07/06/24: Sean Durkin: Re: IBIS Model V5 GTP output
                121067: 07/06/24: Vimal: Re: IBIS Model V5 GTP output
                    121073: 07/06/25: Sean Durkin: Re: IBIS Model V5 GTP output
121054: 07/06/24: Perry: What wrong with the DCM of Virtex4 in my project?
    121059: 07/06/24: Marc Randolph: Re: What wrong with the DCM of Virtex4 in my project?
    121083: 07/06/25: Perry: Re: What wrong with the DCM of Virtex4 in my project?
121057: 07/06/24: Uwe Bonnes: Multidimensional Register in Modul Port List
    121063: 07/06/24: Jonathan Bromley: Re: Multidimensional Register in Modul Port List
    121065: 07/06/24: Mike Treseler: Re: Multidimensional Register in Modul Port List
        121076: 07/06/25: Jonathan Bromley: Re: Multidimensional Register in Modul Port List
            121084: 07/06/25: Symon: Re: Multidimensional Register in Modul Port List
            121087: 07/06/25: Mike Treseler: Re: Multidimensional Register in Modul Port List
                121090: 07/06/25: Jonathan Bromley: Re: Multidimensional Register in Modul Port List
                    121132: 07/06/26: Symon: Re: Multidimensional Register in Modul Port List
121062: 07/06/24: PFC: Desperate to find the right FPGA board
    121079: 07/06/25: John Adair: Re: Desperate to find the right FPGA board
        121133: 07/06/26: PFC: Re: Desperate to find the right FPGA board
            121151: 07/06/26: Ben Jackson: Re: Desperate to find the right FPGA board
121066: 07/06/24: mitshek: Control Panel application for Altera Cyclone II Starter Kit, help?
    121080: 07/06/25: RedskullDC: Re: Control Panel application for Altera Cyclone II Starter Kit, help?
        121154: 07/06/27: mitshek: Re: Control Panel application for Altera Cyclone II Starter Kit, help?
121070: 07/06/24: hitsx@hit.edu.cn: How to choose FPGA for a huge computation?
    121071: 07/06/25: Frank Buss: Re: How to choose FPGA for a huge computation?
    121081: 07/06/25: Michael J?rgensen: Re: How to choose FPGA for a huge computation?
    121089: 07/06/25: Nico Coesel: Re: How to choose FPGA for a huge computation?
    121106: 07/06/26: John Williams: Re: How to choose FPGA for a huge computation?
        121124: 07/06/26: Uwe Bonnes: Re: How to choose FPGA for a huge computation?
            121134: 07/06/26: PFC: Re: How to choose FPGA for a huge computation?
    121108: 07/06/25: hitsx@hit.edu.cn: Re: How to choose FPGA for a huge computation?
        121531: 07/07/06: <evansamuel@charter.net>: Re: How to choose FPGA for a huge computation?
    121130: 07/06/26: hitsx@hit.edu.cn: Re: How to choose FPGA for a huge computation?
    121138: 07/06/26: ajjc: Re: How to choose FPGA for a huge computation?
    121300: 07/07/01: Totally_Lost: Re: How to choose FPGA for a huge computation?
    121325: 07/07/02: wallge: Re: How to choose FPGA for a huge computation?
    121332: 07/07/02: Totally_Lost: Re: How to choose FPGA for a huge computation?
        121337: 07/07/03: Matthew Hicks: Re: How to choose FPGA for a huge computation?
            122702: 07/08/03: Ray Andraka: Re: How to choose FPGA for a huge computation?
        121339: 07/07/02: Totally_Lost: Re: How to choose FPGA for a huge computation?
        121387: 07/07/03: Totally_Lost: Re: How to choose FPGA for a huge computation?
            121424: 07/07/03: Matthew Hicks: Re: How to choose FPGA for a huge computation?
                121430: 07/07/04: John_H: Re: How to choose FPGA for a huge computation?
            121429: 07/07/03: Totally_Lost: Re: How to choose FPGA for a huge computation?
            121639: 07/07/10: Totally_Lost: Re: How to choose FPGA for a huge computation?
        122712: 07/08/04: <fpga_toys@yahoo.com>: Re: How to choose FPGA for a huge computation?
    121578: 07/07/08: Totally_Lost: Re: How to choose FPGA for a huge computation?
121072: 07/06/25: bwilson79@gmail.com: Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM
    121077: 07/06/25: Symon: Re: Intermittent failures seen when bringing a clock into V4LX160 through IBUF to DCM
121085: 07/06/25: Sebastian Goller: Trouble using DCMs in EDK 8.2
    121107: 07/06/25: Perry: Re: Trouble using DCMs in EDK 8.2
        121118: 07/06/26: Sebastian Goller: Re: Trouble using DCMs in EDK 8.2
            121440: 07/07/04: Sebastian Goller: Re: Trouble using DCMs in EDK 8.2
    121129: 07/06/26: Perry: Re: Trouble using DCMs in EDK 8.2
121092: 07/06/25: Koustav: Interfacing expansion ports thru EDK
121094: 07/06/25: EEngineer: Xilinx FPGA: "after 10ns" constraint
    121095: 07/06/25: John_H: Re: Xilinx FPGA: "after 10ns" constraint
        121098: 07/06/25: Mike Treseler: Re: Xilinx FPGA: "after 10ns" constraint
            121102: 07/06/25: Georg Acher: Re: Xilinx FPGA: "after 10ns" constraint
            121103: 07/06/25: Mike Treseler: Re: Xilinx FPGA: "after 10ns" constraint
                121170: 07/06/27: jtw: Re: Xilinx FPGA: "after 10ns" constraint
    121097: 07/06/25: EEngineer: Re: Xilinx FPGA: "after 10ns" constraint
    121099: 07/06/25: EEngineer: Re: Xilinx FPGA: "after 10ns" constraint
        121101: 07/06/25: Matthew Hicks: Re: Xilinx FPGA: "after 10ns" constraint
    121104: 07/06/25: EEngineer: Re: Xilinx FPGA: "after 10ns" constraint
121105: 07/06/25: <wangtiffany313@gmail.com>: How to deal with RAM issue when generating blif
121109: 07/06/25: commone: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
    121111: 07/06/26: Mark McDougall: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
        121112: 07/06/26: Mark McDougall: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
            121125: 07/06/26: commone: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
                121152: 07/06/27: Mark McDougall: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
                    121160: 07/06/27: commone: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121113: 07/06/26: vasile: VGA 1080x1920 pixel chipset
    121128: 07/06/26: MH: Re: VGA 1080x1920 pixel chipset
    121155: 07/06/27: mitshek: Re: VGA 1080x1920 pixel chipset
121114: 07/06/26: Telenochek: Confused about FPGA devices recommended by Xilinx for my FFT project
    121116: 07/06/26: backhus: Re: Confused about FPGA devices recommended by Xilinx for my FFT
    121136: 07/06/26: Telenochek: Re: Confused about FPGA devices recommended by Xilinx for my FFT project
121115: 07/06/25: Allen: Coding style of verilog for FPGA synthesis
    121127: 07/06/26: Mir: Re: Coding style of verilog for FPGA synthesis
    121131: 07/06/26: Mike Treseler: Re: Coding style of verilog for FPGA synthesis
    121201: 07/06/27: <ghelbig@lycos.com>: Re: Coding style of verilog for FPGA synthesis
    121257: 07/06/29: Allen: Re: Coding style of verilog for FPGA synthesis
    121412: 07/07/03: <ghelbig@lycos.com>: Re: Coding style of verilog for FPGA synthesis
121117: 07/06/26: Ravishankar S: Trace capturing
    121164: 07/06/27: Jonathan Bromley: Re: Trace capturing
        121166: 07/06/27: Ravishankar S: Re: Trace capturing
            121168: 07/06/27: Jonathan Bromley: Re: Trace capturing
                121261: 07/06/29: Ravishankar S: Re: Trace capturing
121119: 07/06/26: Ravishankar S: Amontec chameleon
    121126: 07/06/26: Antti: Re: Amontec chameleon
        121167: 07/06/27: Ravishankar S: Re: Amontec chameleon
121120: 07/06/26: selva kumar: what is speed grade in virtes1
121137: 07/06/26: Jeremy: Xilinx ISE 9.1 - Version Control - VSS
    121139: 07/06/26: Alex Colvin: Re: Xilinx ISE 9.1 - Version Control - VSS
        121140: 07/06/26: Alex Colvin: Re: Xilinx ISE 9.1 - Version Control - VSS
    121142: 07/06/26: Symon: Re: Xilinx ISE 9.1 - Version Control - VSS
    121143: 07/06/26: Matthew Hicks: Re: Xilinx ISE 9.1 - Version Control - VSS
    121159: 07/06/27: Martin Thompson: Re: Xilinx ISE 9.1 - Version Control - VSS
121141: 07/06/26: N.V. Chandramouli: regarding the montavista linux preview kit
    121171: 07/06/27: morphiend: Re: regarding the montavista linux preview kit
121144: 07/06/26: Marc Weber: Can FPGAs inputs detect low currents?
    121145: 07/06/26: Peter Alfke: Re: Can FPGAs inputs detect low currents?
    121146: 07/06/26: John_H: Re: Can FPGAs inputs detect low currents?
    121147: 07/06/26: austin: Re: Can FPGAs inputs detect low currents?
    121150: 07/06/27: Jim Granville: Re: Can FPGAs inputs detect low currents?
        121161: 07/06/27: Marc Weber: my project / FPGA as USB client ? (Re: Can FPGAs inputs detect low currents?)(
121149: 07/06/26: Rotem Gazit: CameraLink to Hotlink-II video converter
    121156: 07/06/27: mh: Re: CameraLink to Hotlink-II video converter
    121175: 07/06/27: Martin Thompson: Re: CameraLink to Hotlink-II video converter
121153: 07/06/26: Vimal: Virtex4 ISERDES question
121158: 07/06/27: Perry: A strange error during PAR process in EDK, could anyone in xilinx help me?
    121162: 07/06/27: Brian Drummond: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
        121243: 07/06/29: MM: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
    121196: 07/06/27: Perry: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
    121244: 07/06/29: MM: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
    121419: 07/07/03: morphiend: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
121163: 07/06/27: <dineshvc@gmail.com>: Adding opb AC97 Controler in Xilinx EDK 8.2
    121165: 07/06/27: Antti: Re: Adding opb AC97 Controler in Xilinx EDK 8.2
121169: 07/06/27: Specialist Verilog Engineers Roles: VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
121172: 07/06/27: <SWAmdata@gmail.com>: EDK Custom IP
    121233: 07/06/28: MM: Re: EDK Custom IP
121174: 07/06/27: Richard Henry: Bidirectional LVDS
    121177: 07/06/27: Andy: Re: Bidirectional LVDS
        121185: 07/06/27: Steve at fivetrees: Re: Bidirectional LVDS
            121190: 07/06/27: Uwe Bonnes: Re: Bidirectional LVDS
                121282: 07/06/30: Uwe Bonnes: Re: Bidirectional LVDS
        121187: 07/06/27: Steve at fivetrees: Re: Bidirectional LVDS
            121195: 07/06/28: Steve at fivetrees: Re: Bidirectional LVDS
        121289: 07/06/30: John Larkin: Re: Bidirectional LVDS
    121181: 07/06/27: Richard Henry: Re: Bidirectional LVDS
    121186: 07/06/27: Richard Henry: Re: Bidirectional LVDS
    121189: 07/06/27: Gabor: Re: Bidirectional LVDS
    121274: 07/06/29: Richard Henry: Re: Bidirectional LVDS
121179: 07/06/27: gamer: Bit error counter - how to make it faster
    121180: 07/06/27: Günther Jehle: Re: Bit error counter - how to make it faster
    121192: 07/06/27: Paul A. Clayton: Re: Bit error counter - how to make it faster
    121202: 07/06/28: Ben Jackson: Re: Bit error counter - how to make it faster
    121218: 07/06/28: Terje Mathisen: Re: Bit error counter - how to make it faster
        121603: 07/07/09: glen herrmannsfeldt: Re: Bit error counter - how to make it faster
    121220: 07/06/28: comp.arch.fpga: Re: Bit error counter - how to make it faster
    121229: 07/06/28: Petter Gustad: Re: Bit error counter - how to make it faster
    121232: 07/06/28: Andy Freeman: Re: Bit error counter - how to make it faster
    121280: 07/06/30: YUAN, Nan: Re: Bit error counter - how to make it faster
        121602: 07/07/09: glen herrmannsfeldt: Re: Bit error counter - how to make it faster
121194: 07/06/27: Xilinx User: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
    121205: 07/06/28: HT-Lab: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
        121214: 07/06/28: Xilinx User: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
            121240: 07/06/28: Alan: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
121197: 07/06/27: Albert Nguyen: Xilinx FPGA to interface to special I/O
    121198: 07/06/28: Jim Granville: Re: Xilinx FPGA to interface to special I/O
        121210: 07/06/28: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
            121213: 07/06/28: John_H: Re: Xilinx FPGA to interface to special I/O
                121217: 07/06/28: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
                    121222: 07/06/28: John_H: Re: Xilinx FPGA to interface to special I/O
                        121225: 07/06/28: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
                            121227: 07/06/28: John_H: Re: Xilinx FPGA to interface to special I/O
            121230: 07/06/29: Jim Granville: Re: Xilinx FPGA to interface to special I/O
    121199: 07/06/28: John_H: Re: Xilinx FPGA to interface to special I/O
        121212: 07/06/28: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
    121204: 07/06/28: Ben Jackson: Re: Xilinx FPGA to interface to special I/O
        121211: 07/06/28: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
            121236: 07/06/28: Ben Jackson: Re: Xilinx FPGA to interface to special I/O
                121259: 07/06/29: Albert Nguyen: Re: Xilinx FPGA to interface to special I/O
                    121265: 07/06/29: John_H: Re: Xilinx FPGA to interface to special I/O
    121278: 07/06/29: Peter Alfke: Re: Xilinx FPGA to interface to special I/O
121206: 07/06/28: Ulrich Bangert: Analogue like signal interaction within cpld possible ????
    121209: 07/06/28: Jim Granville: Re: Analogue like signal interaction within cpld possible ????
        121215: 07/06/28: Ulrich Bangert: Re: Analogue like signal interaction within cpld possible ????
            121228: 07/06/29: Jim Granville: Re: Analogue like signal interaction within cpld possible ????
    121281: 07/06/29: John Larkin: Re: Analogue like signal interaction within cpld possible ????
        121345: 07/07/03: Ulrich Bangert: Re: Analogue like signal interaction within cpld possible ????
            121346: 07/07/03: Jim Granville: Re: Analogue like signal interaction within cpld possible ????
                121433: 07/07/04: Ulrich Bangert: Re: Analogue like signal interaction within cpld possible ????
    121301: 07/07/01: comp.arch.fpga: Re: Analogue like signal interaction within cpld possible ????
121207: 07/06/28: maxascent: ISE 9.1 Problem
121216: 07/06/28: Uwe Bonnes: How to write constraints with a clock enable?
    121221: 07/06/28: Gabor: Re: How to write constraints with a clock enable?
121219: 07/06/28: <neilla@pipstechnology.co.uk>: USB JTAG Programming
    121223: 07/06/28: Teo: Re: USB JTAG Programming
    121231: 07/06/28: Teo: Re: USB JTAG Programming
    121245: 07/06/29: Amontec, Larry: Re: USB JTAG Programming
        121253: 07/06/29: Amontec, Larry: Re: USB JTAG Programming
    121248: 07/06/29: <neilla@pipstechnology.co.uk>: Re: USB JTAG Programming
    121249: 07/06/29: <neilla@pipstechnology.co.uk>: Re: USB JTAG Programming
121226: 07/06/28: christophe ALEXANDRE: vista 64 bits
    121255: 07/06/29: RedskullDC: Re: vista 64 bits
        121285: 07/06/30: Sylvain Munaut: Re: vista 64 bits
            121496: 07/07/05: H. Peter Anvin: Re: vista 64 bits
    121562: 07/07/08: christophe ALEXANDRE: Re: vista 64 bits
121234: 07/06/28: <len>: d-link router?
    121235: 07/06/28: John_H: Re: d-link router?
        121238: 07/06/29: Mark McDougall: Re: d-link router?
    121237: 07/06/29: Symon: Re: d-link router?
    121250: 07/06/29: <jetmarc@hotmail.com>: Re: d-link router?
    121263: 07/06/29: <mikeandmax@aol.com>: Re: d-link router?
121239: 07/06/28: cpope: modelsim search path
    121247: 07/06/29: HT-Lab: Re: modelsim search path
        121258: 07/06/29: cpope: Re: modelsim search path
            121260: 07/06/29: HT-Lab: Re: modelsim search path
                121264: 07/06/29: cpope: Re: modelsim search path
    121262: 07/06/29: <pontus.stenstrom@gmail.com>: Re: modelsim search path
121241: 07/06/29: Jim Granville: Execute from SPI flash
    121242: 07/06/29: Jim Granville: Re: Execute from SPI flash
        121252: 07/06/29: Martin Thompson: Re: Execute from SPI flash
            121254: 07/06/29: Jim Granville: Re: Execute from SPI flash
121246: 07/06/28: Perry: How to snoop an inout signal in EDK?
    121269: 07/06/29: motty: Re: How to snoop an inout signal in EDK?
121251: 07/06/29: comp.arch.fpga: Re: Analogue like signal interaction within cpld possible ????
    121256: 07/06/29: Ulrich Bangert: Re: Analogue like signal interaction within cpld possible ????
121266: 07/06/29: devices: Latches
    121267: 07/06/29: Jon Beniston: Re: Latches
        121276: 07/06/29: devices: Re: Latches
    121271: 07/06/29: John_H: Re: Latches
        121277: 07/06/29: devices: Re: Latches
    122052: 07/07/18: Ralf Hildebrandt: Re: Latches
        122060: 07/07/18: Mike Treseler: Re: Latches
        122075: 07/07/19: devices: Re: Latches
    122106: 07/07/19: Andy: Re: Latches
121268: 07/06/29: Kuo: Xilinx ngdbuild question
    121270: 07/06/29: davide: Re: Xilinx ngdbuild question
    121272: 07/06/29: Sean Durkin: Re: Xilinx ngdbuild question
        121273: 07/06/29: Kuo: Re: Xilinx ngdbuild question
121275: 07/06/29: Koustav: Interfacing a camera to a fpga
121279: 07/06/29: Eddie H: Virtex5 LXT Clock Distribution
121283: 07/06/30: <darrick>: Xilinx programmer, many unknown devices...
    121284: 07/06/30: Uwe Bonnes: Re: Xilinx programmer, many unknown devices...
        121286: 07/06/30: <darrick>: Re: Xilinx programmer, many unknown devices...
    121288: 07/06/30: doug: Re: Xilinx programmer, many unknown devices...
    121291: 07/06/30: Matthew Hicks: Re: Xilinx programmer, many unknown devices...
        121293: 07/06/30: <darrick>: Re: Xilinx programmer, many unknown devices...
            121294: 07/06/30: Matthew Hicks: Re: Xilinx programmer, many unknown devices...
            121295: 07/06/30: John_H: Re: Xilinx programmer, many unknown devices...
    121322: 07/07/02: davide: Re: Xilinx programmer, many unknown devices...
    121335: 07/07/02: Andy Peters: Re: Xilinx programmer, many unknown devices...
121287: 07/06/30: <zlatkopetrov@yahoo.com>: How to pass several commands inside xps from script?
    121304: 07/07/02: John Williams: Re: How to pass several commands inside xps from script?
    121320: 07/07/02: <zlatkopetrov@yahoo.com>: Re: How to pass several commands inside xps from script?
121292: 07/06/30: Eddie H: Why PLL and not DCM for V5?
    121389: 07/07/03: MM: Re: Why PLL and not DCM for V5?
        121393: 07/07/03: austin: Re: Why PLL and not DCM for V5?
121296: 07/06/30: ZHI: Multiplier in Xilinx
    121298: 07/07/01: John_H: Re: Multiplier in Xilinx
        121321: 07/07/02: John_H: Re: Multiplier in Xilinx
        121323: 07/07/02: Jeff Cunningham: Re: Multiplier in Xilinx
            121359: 07/07/03: Sylvain Munaut: Re: Multiplier in Xilinx
            121384: 07/07/03: RCIngham: Re: Multiplier in Xilinx
    121319: 07/07/02: ZHI: Re: Multiplier in Xilinx
    121358: 07/07/03: ZHI: Re: Multiplier in Xilinx
    121377: 07/07/03: Tom Dillon: Re: Multiplier in Xilinx
    121436: 07/07/04: ZHI: Re: Multiplier in Xilinx
    121528: 07/07/06: <evansamuel@charter.net>: Re: Multiplier in Xilinx
    121535: 07/07/06: ZHI: Re: Multiplier in Xilinx
121297: 07/06/30: cpope: intermitent boot in V4
    121299: 07/07/01: Marc Randolph: Re: intermitent boot in V4
    121306: 07/07/02: Greg Crocker: Re: intermitent boot in V4
        121307: 07/07/01: cpope: Re: intermitent boot in V4
    121312: 07/07/02: Brian Drummond: Re: intermitent boot in V4


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