Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 121000

Article: 121000
Subject: Re: OPB Master Peripheral
From: chakra <narashimanc@gmail.com>
Date: Thu, 21 Jun 2007 13:17:34 -0700
Links: << >>  << T >>  << A >>
On May 5, 2:39 pm, Guru <ales.gor...@email.si> wrote:
> On May 3, 1:37 am, chakra <narashim...@gmail.com> wrote:
>
>
>
>
>
> > Hello all, I am working on a project, in which am trying to make
> > OV7660 camera protoboard to talk to  ML300Xilinx FPGA board.I have a
> > general question regarding OPB bus.
>
> > Here is the set up:  I am building a OPB Master peripheral which
> > directly talks to camera (8 data, vsync, Href and Pixclk) via GPIO
> > pins on theML300board. The same master peripheral talks to OPB DDR
> > SDRAM which is a slave connected to the OPB Bus. the Master peripheral
> > acquires the data from the camera frame after frame and stores them in
> > the DDR(currently am overwriting the image over and over at the same
> > address stack in DDR)
>
> > Question:: is there a limitation in terms of "clock cycles" to hold
> > the M_Select/M_Buslock high when given OPB_Mgrant by the opb BUS. Like
> > for example "..on a particular time once the OPB gives M_Grant a
> > Master peripheral can hold the M_Select and M_Buslock high  only for
> > 16 clock cycles...". is there some limitation like the above?
>
> > i am holding the M_Buslock and M_Select high till the transfer is
> > complete. and it takes close to 640*480*2 pixclk to collect one frame
> > of data from the camera to DDR SDRAM. Once the transfer is complete I
> > do release those signals and pull M_Dbus to ground. I read through the
> > Buslock operation given in the OPB manual by IBM and they seem to be
> > vague on this issue.
>
> > algorithm might look like this
> > A. Master peripheral holds M_Request high
> > B. OPB gives OPB_Mgrant
> > C. Master peripheral pulls M_Request low and holds M_select high to
> > assert OPB bus and take control of the bus. and once transfer is done
> > D. Master peripheral pulls M_Select Low
>
> > If you can help me in this regard it will be very helpful for the
> > success of my project
>
> Dear Chakra,
>
> I build a peripheral like this about a year ago.
> The principle is about the same what you suggested, you just forgot
> some details:
> A. Master peripheral holds M_Request high
> B. OPB gives OPB_Mgrant
> C. Master peripheral pulls M_Request low and holds M_select,
> M_seqAddr, M_BE and M_busLock high to
> assert OPB bus and take control of the bus. You should increment
> address for every OPB_xferAck received.
> D. One cycle before the end of burst pull the  M_seqAddr and M_seqAddr
> low
> E. Master peripheral pulls M_Select and M_BE Low
>
> There is NO limitation for burst size in clock cycles. The only thing
> which limits the burst size is a OPB_retry signal which is asserted
> after OPB_xferAck going low. This is usually a consequence of RAM
> refresh. When the OPB_retry happens in the state C then cancel
> transfer and retry (state A).
> If you receive OPB_errAck or OPB_timeout then immediatelly cancel
> transfer.
>
> Don't hesitate to contact me for further questions.
>
> Good luck,
>
> Guru- Hide quoted text -
>
> - Show quoted text -

thanks guru. the DDR write is working.


Article: 121001
Subject: Re: Virtex 5 Rocketio
From: austin <austin@xilinx.com>
Date: Thu, 21 Jun 2007 13:22:48 -0700
Links: << >>  << T >>  << A >>
PC,

Do you send anything at all before your "first 5 words"?

Serial transceivers do require some data in order to synchronize
initially (if the link stops completely - no data - neither 1's nor 0's,
then the receiver requires some time with data to resynchronize).

Austin

pcplanet@gmx.de wrote:
> Hello folks,
> 
> I am using the V5 rocketio to implement a high speed serial IO. I have
> configured the GTP and it works , but the only problem is that the
> first 5 words ( comma and data)  are corrupted at the receiver. I also
> ran the example design and it also reflects the same problem. Hence I
> guess there should be some problem in configuring the GTP tile. I had
> read the userguide over and over but still no luck .
> 
> -- used TX buffer and RX buffer
> -- no clock correction used
> -- 8B/10B used
> -- no PRBS
> -- Line rate 2.5gbps
> 
> 
> request you help in finding my mistake.
> 
> Thanks
> PC
> 

Article: 121002
Subject: Re: Virtex 5 Rocketio
From: pc <pcplanet@gmx.de>
Date: Thu, 21 Jun 2007 13:47:20 -0700
Links: << >>  << T >>  << A >>
Hello Austin,

I first do a gtpreset and wait for the shared pll to lock .This inturn
starts the DCM to get txusrclk and txusrclk2.
Then  I start with my comma words. No  I donot send any data initially
for sync.

 How long before the recclk extracted from RXN/RXP. But why does it
not work with the example design ?

Thanks
PC



On Jun 21, 10:22 pm, austin <aus...@xilinx.com> wrote:
> PC,
>
> Do you send anything at all before your "first 5 words"?
>
> Serial transceivers do require some data in order to synchronize
> initially (if the link stops completely - no data - neither 1's nor 0's,
> then the receiver requires some time with data to resynchronize).
>
> Austin
>
>
>
> pcpla...@gmx.de wrote:
> > Hello folks,
>
> > I am using the V5 rocketio to implement a high speed serial IO. I have
> > configured the GTP and it works , but the only problem is that the
> > first 5 words ( comma and data)  are corrupted at the receiver. I also
> > ran the example design and it also reflects the same problem. Hence I
> > guess there should be some problem in configuring the GTP tile. I had
> > read the userguide over and over but still no luck .
>
> > -- used TX buffer and RX buffer
> > -- no clock correction used
> > -- 8B/10B used
> > -- no PRBS
> > -- Line rate 2.5gbps
>
> > request you help in finding my mistake.
>
> > Thanks
> > PC- Hide quoted text -
>
> - Show quoted text -



Article: 121003
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: Andy Peters <google@latke.net>
Date: Thu, 21 Jun 2007 13:48:15 -0700
Links: << >>  << T >>  << A >>
On Jun 21, 4:01 am, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote:
> On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall
> <m...@vl.com.au> wrote in
> <467a2875$0$22415$5a62a...@per-qv1-newsreader-01.iinet.net.au>:
>
> >Gene S. Berkowitz wrote:
>
> >> According to the manufacturer (Century Corp, Japan), it stripes the data
> >> across the multiple cards to speed up access (you must install cards in
> >> pairs).
>
> >My statement stands. You can do all that in a single CPLD...
>
> >Regards,
>
> Agreed, was my idea too.

I've done it ...

-a


Article: 121004
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: Andy Peters <google@latke.net>
Date: Thu, 21 Jun 2007 13:50:44 -0700
Links: << >>  << T >>  << A >>
On Jun 21, 1:48 pm, Andy Peters <goo...@latke.net> wrote:
> On Jun 21, 4:01 am, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote:
>
> > On a sunny day (Thu, 21 Jun 2007 17:27:08 +1000) it happened Mark McDougall
> > <m...@vl.com.au> wrote in
> > <467a2875$0$22415$5a62a...@per-qv1-newsreader-01.iinet.net.au>:
>
> > >Gene S. Berkowitz wrote:
>
> > >> According to the manufacturer (Century Corp, Japan), it stripes the data
> > >> across the multiple cards to speed up access (you must install cards in
> > >> pairs).
>
> > >My statement stands. You can do all that in a single CPLD...
>
> > >Regards,
>
> > Agreed, was my idea too.
>
> I've done it ...
>
> -a

(replying to myself ... sheesh) .. actually, not with SD cards ... but
with the NAND flash chips themselves.

-a


Article: 121005
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: Andy Peters <google@latke.net>
Date: Thu, 21 Jun 2007 13:52:20 -0700
Links: << >>  << T >>  << A >>
On Jun 21, 3:23 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On Jun 21, 9:27 am, Mark McDougall <m...@vl.com.au> wrote:
>
> > Gene S. Berkowitz wrote:
> > > According to the manufacturer (Century Corp, Japan), it stripes the data
> > > across the multiple cards to speed up access (you must install cards in
> > > pairs).
>
> > My statement stands. You can do all that in a single CPLD...
>
> Mark,
>
> it depends on your definition of CPLD, if you mean CPLD as Complex
> PLD, not FPGA then, well it may be still doable, but very unreasonable
> as the price of CPLDs increases very quickly above 64MC.

I think Mark means that he can do whatever's necessary in some kind of
programmable logic device.  Whether it's a CPLD or an FPGA is really
just a detail.

-a


Article: 121006
Subject: Re: Virtex 5 Rocketio
From: austin <austin@xilinx.com>
Date: Thu, 21 Jun 2007 13:57:09 -0700
Links: << >>  << T >>  << A >>
PC,

Page 116,

http://direct.xilinx.com/bvdocs/userguides/ug196.pdf

page 14,

http://direct.xilinx.com/bvdocs/userguides/ug196.pdf

200uS, max.

Austin

pc wrote:
> Hello Austin,
> 
> I first do a gtpreset and wait for the shared pll to lock .This inturn
> starts the DCM to get txusrclk and txusrclk2.
> Then  I start with my comma words. No  I donot send any data initially
> for sync.
> 
>  How long before the recclk extracted from RXN/RXP. But why does it
> not work with the example design ?
> 
> Thanks
> PC
> 
> 
> 
> On Jun 21, 10:22 pm, austin <aus...@xilinx.com> wrote:
>> PC,
>>
>> Do you send anything at all before your "first 5 words"?
>>
>> Serial transceivers do require some data in order to synchronize
>> initially (if the link stops completely - no data - neither 1's nor 0's,
>> then the receiver requires some time with data to resynchronize).
>>
>> Austin
>>
>>
>>
>> pcpla...@gmx.de wrote:
>>> Hello folks,
>>> I am using the V5 rocketio to implement a high speed serial IO. I have
>>> configured the GTP and it works , but the only problem is that the
>>> first 5 words ( comma and data)  are corrupted at the receiver. I also
>>> ran the example design and it also reflects the same problem. Hence I
>>> guess there should be some problem in configuring the GTP tile. I had
>>> read the userguide over and over but still no luck .
>>> -- used TX buffer and RX buffer
>>> -- no clock correction used
>>> -- 8B/10B used
>>> -- no PRBS
>>> -- Line rate 2.5gbps
>>> request you help in finding my mistake.
>>> Thanks
>>> PC- Hide quoted text -
>> - Show quoted text -
> 
> 

Article: 121007
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: cs_posting@hotmail.com
Date: Thu, 21 Jun 2007 21:23:59 -0000
Links: << >>  << T >>  << A >>
On Jun 21, 3:13 pm, Antti <Antti.Luk...@googlemail.com> wrote:

> there are 4 times IDE-SD ASIC's, from company called c-guys

So why didn't you just say that in your first post and save all this
running around in circles?


Article: 121008
Subject: Re: Nios II problem
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Thu, 21 Jun 2007 23:44:00 +0200
Links: << >>  << T >>  << A >>

"Frank Buss" <fb@frank-buss.de> wrote

> At work I'm using a Nios CPU with Quartus 7.1. I've configured it with 512
> bytes data and instruction cache, and it uses internal RAM. I have a 
> struct
> like this:
>
> struct Something {
>  alt_u16 foo;
>  alt_u16 bar;
> };
>
> When modifying "foo" in a loop in main and "bar" of the same object in an
> interrupt, it looks like sometimes it behaves like the interrupt overides
> both variables, e.g. main increments "foo", but after the interrupt has
> written "bar", the old value of "foo" is there, too. Maybe there is a bug
> with memory cache updates? When I'm using "int" (or alt_u32), the problem
> disappears.
>
> Is there anything like this already known? If not, I'll try to extract a
> simple test case.

Have you tried to bypass the cache? (you need to set the bit 31 of the 
address for that)

Marc 



Article: 121009
Subject: Re: Nios II problem
From: cs_posting@hotmail.com
Date: Thu, 21 Jun 2007 21:54:34 -0000
Links: << >>  << T >>  << A >>
On Jun 21, 2:09 pm, Frank Buss <f...@frank-buss.de> wrote:
>
> One more hint why it might be a CPU core problem: I have configured Nios to
> use 32 bit block RAM, so it has to do some clever internal thing, if it
> writes to the same memory location from the main function and from
> interrupt.

How many write enables does the block ram have?

Aren't they oftern seperate for each 8/9 bit lane?

In traditional external memory I'd expect this problem with sub-width
writes, but in an FPGA I would think that narrower write enables would
be available.


Article: 121010
Subject: Re: Interesting problems about high performance computing
From: "Marc Battyani" <Marc.Battyani@fractalconcept.com>
Date: Thu, 21 Jun 2007 23:58:06 +0200
Links: << >>  << T >>  << A >>

<hitsx@hit.edu.cn> wrote
>
> To be specific, my program is related to 3D image reconstruction. The
> input data is float point numbers in the form of 3D array. I represent
> it using symbol: g(x1,y1,z1), while the number of x1,y1,z1 are quite
> large. The output data is another 3D float point array. I represent it
> using symbol: F(x2,y2,z2), similarily the number of x2,y2,z2 are also
> quite large.
>
> The estimated memory usage is 2GB or so, while the calculations
> required is listed below:
>
> integer addition 2442 Giga operations per second
> float add 814  Giga operations per second
> float substrac 2424 Giga operations per second
> float muliply 1610 Giga operations per second
> float divide 809  Giga operations per second
>
> I want these calculations done in one minite, so we can divide the
> operations by 60.
> As a matter of fact, if the calculations could be done in 5 minites,
> it is OK for me. So for minimum requirment, divide the above numbers
> by 300(=60*5).

Is it single or double precision floats?

Divided by 300 the numbers are not very high:
10.7G fadd/fsub
5.3G fmul
2.7G fdiv

IMO your limiting factor will probably be the memory bandwidth. If you have 
enough memory bandwidth then it's not a problem for a large FPGA. You can 
even go faster than that.

Marc



Article: 121011
Subject: Re: Inverse of a matrix
From: Venkat <venkat.japan@gmail.com>
Date: Fri, 22 Jun 2007 00:46:46 -0000
Links: << >>  << T >>  << A >>
On Jun 1, 7:14 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Venkat wrote:
> > Can anyone suggest simple algorithms for implementation of finding the
> > inverse of a matrix (4 X 4)? Even information of IP Cores for such
> > functionality will be greatly appreciated.
>
> There might be a systolic array implementation that would
> make a convenient FPGA pipeline.
>
> How fast does it need to be?  How big can it be?
>
> You will also need the appropriate floating point logic
> blocks.
>
> -- glen

Thanks all for your valuable feedback. At present, I could only think
of the hard approach of doing the inverse, the traditional math way
consuming lot of multipliers. Since the solution has to be in FPGA
(Xilinx), I cannot think of any software approach. The Speed of
operation should be at max 80 Mhz. However pipelining is allowed and
latency is tolerant to a reasonable extent. I will be glad to get more
feedback on any algorithms conducive for FPGA implementation.

Thanks again,
Venkat.


Article: 121012
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: Mark McDougall <markm@vl.com.au>
Date: Fri, 22 Jun 2007 11:42:17 +1000
Links: << >>  << T >>  << A >>
cs_posting@hotmail.com wrote:

> You assume that the operation of the buffers is trivial.  I suspect it
> may not be.  Even the ATA  interface is non-trivial if you want to
> support the faster transfer modes.  There's probably a reason why it's
> an FPGA and not simply a CPLD.

Actually, if you're talking about UDMA, implementation _is_ trivial.

And for the record, I was probably a little flippant in my remark about
CPLDs... I'll defer to Antti's judgement on that one...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 121013
Subject: Re: Virtex 5 Rocketio
From: motty <mottoblatto@yahoo.com>
Date: Thu, 21 Jun 2007 19:13:58 -0700
Links: << >>  << T >>  << A >>
I am investigating the same thing.  My GTP is setup to use:

--line rate of 312.5 MHz
--No 8b/10b
--Oversampler is of course used
--RECCLK is NOT used
--dynamic sampling is used

Reading the user guide it seems that there is no way to set the
receiver to do both oversampling AND lock to ref (page 139 -
PMA_RX_CFG settings).  I need this functionality since I am using a
slow line rate AND my data can have LONG runs of no data transitions.
The RX signals can stay idle for an indeterminate amount of time
before any useful data comes across.  Therefore I don't want to use a
recovered clock - since there might not even be one!

I had a V4 MGT setup to do oversampling AND it locked to the reference
clock.  This worked fine for my protocol.  Unfortunately the line rate
is too low and not supported in the MGT's.  Even though it worked fine
for our eval board, it may or may not work on other FPGA's.  We got a
V5 eval board to test the GTP since they can run the line rate we
need.

Perhaps I am not understanding the GTP user guide (I admit I haven't
scrutinized it yet - I have just started this project) and there is no
way to do what I need.

I am currently using the wizard-created instantiation/attributes and I
am seeing the data recovered AFTER some number of bits (like the above
post).  This is analogous to losing frames of data.

I have a solution that uses 4X oversampling in the V4 fabric, but we
wanted to evaluate another fallback option.  Is it possible to use the
V5 GTP for this protocol?


Article: 121014
Subject: is Ultracontroller-2 supposed to work under XPS/ISE 9.1?
From: Jeff Cunningham <jcc@sover.net>
Date: Thu, 21 Jun 2007 22:36:31 -0400
Links: << >>  << T >>  << A >>
Has anyone had success making ultracontroller-2 work under XPS 9.1? When 
I tried opening uc2_1ppc_v4_vhdl/uc2.xmp project file under 9.1 XPS it 
says "we recommend that you exit XPS now. As a project managed by 
project navigator, any further use of XPS could cause corruption". If I 
go ahead and open it, and try to build it using the supplied linker 
script, it has fatal errors with sections overlapping, etc.

Is a project like uc-2 even possible under XPS? It seems like XPS 
requires you to select an OS and the libraries that come with it. Even 
selecting "standalone" results in library code with crt0.s, boot0.s, 
etc. The uc-2 examples all have their own custom versions of these files 
and I can't figure out how to use them without conflicts in XPS 9.1.

Ultimately what I am trying to do is create a bootloader that would get 
initialized using the extended bitstream cache loading method like that 
described in xapp719. This bootloader would then read some flash to get 
the real program into ddr space.

thanks,
Jeff

Article: 121015
Subject: Re: Interesting problems about high performance computing
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: Thu, 21 Jun 2007 19:48:20 -0700
Links: << >>  << T >>  << A >>
It is double precision. And can you please explain it for me why it
matters?
The another question is that as you mentioned memory bandwidth could
be an issue, can you evaluate the approximately required memory
bandwidth?


Article: 121016
Subject: Re: Interesting problems about high performance computing
From: "hitsx@hit.edu.cn" <hitsx@hit.edu.cn>
Date: Thu, 21 Jun 2007 20:05:20 -0700
Links: << >>  << T >>  << A >>
On 6 22 ,   5 58 , "Marc Battyani" <Marc.Batty...@fractalconcept.com>
wrote:
> <h...@hit.edu.cn> wrote
>
>
>
>
>
>
>
> > To be specific, my program is related to 3D image reconstruction. The
> > input data is float point numbers in the form of 3D array. I represent
> > it using symbol: g(x1,y1,z1), while the number of x1,y1,z1 are quite
> > large. The output data is another 3D float point array. I represent it
> > using symbol: F(x2,y2,z2), similarily the number of x2,y2,z2 are also
> > quite large.
>
> > The estimated memory usage is 2GB or so, while the calculations
> > required is listed below:
>
> > integer addition 2442 Giga operations per second
> > float add 814  Giga operations per second
> > float substrac 2424 Giga operations per second
> > float muliply 1610 Giga operations per second
> > float divide 809  Giga operations per second
>
> > I want these calculations done in one minite, so we can divide the
> > operations by 60.
> > As a matter of fact, if the calculations could be done in 5 minites,
> > it is OK for me. So for minimum requirment, divide the above numbers
> > by 300(=60*5).
>
> Is it single or double precision floats?
>
> Divided by 300 the numbers are not very high:
> 10.7G fadd/fsub
> 5.3G fmul
> 2.7G fdiv
>
> IMO your limiting factor will probably be the memory bandwidth. If you have
> enough memory bandwidth then it's not a problem for a large FPGA. You can
> even go faster than that.
>
> Marc-         -
>
> -         -

It is double precision. And can you please explain it for me why it
matters?
The another question is that as you mentioned memory bandwidth could
be an issue, can you evaluate the approximately required memory
bandwidth?


Article: 121017
Subject: Re: Interesting problems about high performance computing
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 22 Jun 2007 08:14:35 GMT
Links: << >>  << T >>  << A >>
In news:1182481520.530724.54480@i38g2000prf.googlegroups.com
timestamped Thu, 21 Jun 2007 20:05:20 -0700, "hitsx@hit.edu.cn"
<hitsx@hit.edu.cn> posted:
     "On 6 22 ,   5 58 , "Marc Battyani" <Marc.Batty...@fractalconcept.com>
     wrote:
     > <h...@hit.edu.cn> wrote
[..]
     >
     > > The estimated memory usage is 2GB or so, while the calculations
     > > required is listed below:
     >
     > > integer addition 2442 Giga operations per second
[                                              ^^^^^^^^^^
N.B. "per second".]
     > > float add 814  Giga operations per second
     > > float substrac 2424 Giga operations per second
     > > float muliply 1610 Giga operations per second
     > > float divide 809  Giga operations per second
     >
     > > I want these calculations done in one minite, so we can divide the
     > > operations by 60.
[                                          ^^^^^^^^^^
N.B. one minute.]
[                   ^^^^^                                        ^^^^^^
N.B. the person of Harbin Institute of Technology of China typed
"divide" but clearly conveyed and understood the concept of needing to
multiply in order to speed up an implementation to perform five
minutes' worth of calculations of the original implementation's in one
second and simply mixed up the English word "divide" with
"multiply". I am reminded of a language lesson in which I mixed up a
word for "close" with a word for "open" (or maybe it was the other way
round) so the teacher mocked me by trying to indicate that such
miscommunication could result in disaster if I was giving an order to
control a dam instead of a door or window.]
     > > As a matter of fact, if the calculations could be done in 5 minites,
     > > it is OK for me. So for minimum requirment, divide the above numbers
     > > by 300(=60*5).
     >
     > Is it single or double precision floats?
     >
     > Divided by 300 the numbers are not very high:
     > 10.7G fadd/fsub
     > 5.3G fmul
     > 2.7G fdiv"

Hello,

In case you missed them, please see my notes above in square brackets
(and to see what the ^ characters are being used to point at, view in
a monospace font such as Courier).

The numbers should be divided by the reciprocal of 300 (or, for
efficient calculations, multiplied by 300) so instead of 10.7Gflops;
5.3Gflops; and 2.7Gflops the results should be approximately...
244200 Gigafloating point operations per second for additions;
727200 Gigafloating point operations per second for subtractions;
483000 Gigafloating point operations per second for multiplications;
and
242700 Gigafloating point operations per second for divisions.


     "[..]
     
     It is double precision. And can you please explain it for me why it
     matters?"

Slower and more memory (but less inaccurate).

     "The another question is that as you mentioned memory bandwidth could
     be an issue, can you evaluate the approximately required memory
     bandwidth?"

The more bigger values which will be flowing through your gates, the
more bits per second you will want to be able to handle. I am
surprised that you did not notice the inappropriate calculation of
1610 Gflops / 300 = 5.3Gflops so if you plan on spending a lot of
money on your new implementation, please for your own sake,
double-check everything.

Regards,
Colin Paul Gloster

From laurent.pinchart@skynet.be Fri Jun 22 02:47:18 2007
Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!tudelft.nl!txtfeed1.tudelft.nl!feeder.news-service.com!news.astraweb.com!border1.a.newsrouter.astraweb.com!hwmnpeer01.ams!news.highwinds-media.com!kramikske.telenet-ops.be!nntp.telenet.be!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail
Message-Id: <467b9aa6$0$13864$ba620e4c@news.skynet.be>
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Subject: Re: How to simulate testbenches using the ISE simulator in linux
Newsgroups: comp.arch.fpga
Date: Fri, 22 Jun 2007 11:47:18 +0200
References: <1182116017.579060.135360@d30g2000prg.googlegroups.com> <4677c0e2$0$13852$ba620e4c@news.skynet.be> <1182273982.654732.238610@n15g2000prd.googlegroups.com> <4678fbc4$0$14235$ba620e4c@news.skynet.be> <1182352484.909159.317010@g4g2000hsf.googlegroups.com> <1182355965.993612.150100@z28g2000prd.googlegroups.com> <467a6dcc$0$13850$ba620e4c@news.skynet.be> <1182441326.693263.13800@n15g2000prd.googlegroups.com>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 25
Organization: -= Belgacom Usenet Service =-
NNTP-Posting-Host: 45ff1fe7.news.skynet.be
X-Trace: 1182505639 news.skynet.be 13864 194.78.198.49:63313
X-Complaints-To: usenet-abuse@skynet.be
Xref: prodigy.net comp.arch.fpga:132781
X-Received-Date: Fri, 22 Jun 2007 05:47:33 EDT (newsdbm02.news.prodigy.net)

Hi Ankit,

> I am ready to use it if you could provide me with a link
> from where i could download it i guess this is my last chance of
> running it..I am getting a little frustrated as i have not been able
> to run xilinx completely on linux..A little help can really help me
> out..Waiting for your reply..

There are several open-source projects out there. Which device are you
targetting, and what programming cable are you using ?

Parallel-port cables are widely supported. The Xilinx Platform Cable USB is
a bit of a problem, as Xilinx won't release any information regarding the
protocol. There have been a few reverse-engineering efforts to understand
how the cable works, and an open-source firmware replacement has been
developed. It currently runs slower than with the Xilinx firmware, but at
least it's usable.

Have a look at http://inisyn.org/src/xup/ for a S3E programmer working with
the USB cable.

Best regards,

Laurent Pinchart


Article: 121018
Subject: Re: How to simulate testbenches using the ISE simulator in linux
From: Ankit <ankitanand1986@gmail.com>
Date: Fri, 22 Jun 2007 03:05:56 -0700
Links: << >>  << T >>  << A >>
Hi Laurent,

                  Thanx a lot for providing the link i will definitely
give it a try..I am looking to program the CPLD board using the the
parallel port i will use JTAG..


Regards
Ankit



Article: 121019
Subject: Re: Can anyone identify the manufacturer of this Chip ?
From: cs_posting@hotmail.com
Date: Fri, 22 Jun 2007 13:35:21 -0000
Links: << >>  << T >>  << A >>
On Jun 21, 3:13 pm, Antti <Antti.Luk...@googlemail.com> wrote:

> there are 4 times IDE-SD ASIC's, from company called c-guys
> 1 per SD card. those chips include FULL IDE2SD interface,
> each of them has local onchip buffers for 2 sector
> FPGA does some management only, to combine the 4 IDE into one,
> the SD IP core is not inside the FPGA at all..

The SD core may not be in the FPGA, but if the device stripes data
across the cards, which thanks to these ASICS present IDE interfaces,
wouldn't it need to implement a fully IDE target to talk to the PC,
and then multiple IDE hosts to talk to the ASICs?   And quite possible
a small amount of buffering in between... beginning to make sense for
it to be an FPGA.  Though perhaps not an elegant design.

Curious what that wide package device (1x) is.  It looks like a flash
memory device...


Article: 121020
Subject: How to deal with unavoidable setup time violation in CoolRunner II cpld?
From: cxu_dl@yahoo.com
Date: Fri, 22 Jun 2007 07:28:24 -0700
Links: << >>  << T >>  << A >>
Hi,
I apologize if this question is too stupid... basically I want to
build a protocol analyzer with a CoolRunner II cpld. the CPLD will
watch the bus line and extract data. I have passed behaviorial
simulation and fitted the device. but post-fit timing simulation gives
me some setup time violations and the output goes to X afterwards. I
read document that says ASYNC_REG can be used but it is not  available
on coolrunner cpld. Then I'm very concerned about what happens in the
real circuit. The bus line will not switch in sync with the sampling
clock, due to different clock domains, jitters etc. what happens in
the real circuit when the setup time is violated? will the cpld go
into metastable state for ever? This must be an old problem that has
been long solved, but how? can anyone help? thanks a lot....

Hsu


Article: 121021
Subject: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
From: cxu_dl@yahoo.com
Date: Fri, 22 Jun 2007 07:37:39 -0700
Links: << >>  << T >>  << A >>
On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
> Hi,
> I apologize if this question is too stupid... basically I want to
> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
> watch the bus line and extract data. I have passed behaviorial
> simulation and fitted the device. but post-fit timing simulation gives
> me some setup time violations and the output goes to X afterwards. I
> read document that says ASYNC_REG can be used but it is not  available
> on coolrunner cpld. Then I'm very concerned about what happens in the
> real circuit. The bus line will not switch in sync with the sampling
> clock, due to different clock domains, jitters etc. what happens in
> the real circuit when the setup time is violated? will the cpld go
> into metastable state for ever? This must be an old problem that has
> been long solved, but how? can anyone help? thanks a lot....
>
> Hsu

Just want to add that I have a local oversampling clock, and the bus
could switch at anytime, say 0.1ns before the clock edge. and the cpld
requires setup time of 1.8ns.


Article: 121022
Subject: Cadence TestBuilder
From: Amal <akhailtash@gmail.com>
Date: Fri, 22 Jun 2007 15:22:52 -0000
Links: << >>  << T >>  << A >>
Does anyone have a copy of the last release of "Cadence TestBuilder"?
I would appreciate if you can give me a copy.

-- Amal


From Iwo.Mergler@soton.sc.philips.com Fri Jun 22 08:57:08 2007
Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!newsfeed.cw.net!cw.net!news-FFM2.ecrc.de!news-raspail.gip.net!news.gsl.net!gip.net!lon04-news-philips!53ab2750!not-for-mail
Message-Id: <k38tk4-58l.ln1@c2968.soton.sc.philips.com>
From: Iwo Mergler <Iwo.Mergler@soton.sc.philips.com>
Subject: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
Newsgroups: comp.arch.fpga
References: <1182522504.655936.24620@e9g2000prf.googlegroups.com> <1182523059.138125.241130@m37g2000prh.googlegroups.com>
Lines: 43
Organization: Not organised
User-Agent: KNode/0.9.2
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Date: Fri, 22 Jun 2007 16:57:08 +0100
NNTP-Posting-Host: 161.85.127.140
X-Complaints-To: newsmaster@rain.fr
X-Trace: lon04-news-philips 1182530887 161.85.127.140 (Fri, 22 Jun 2007 16:48:07 GMT)
NNTP-Posting-Date: Fri, 22 Jun 2007 16:48:07 GMT
Xref: prodigy.net comp.arch.fpga:132793
X-Received-Date: Fri, 22 Jun 2007 12:47:34 EDT (newsdbm02.news.prodigy.net)

 cxu_dl@yahoo.com wrote:

> On 6 22 ,   10 28 , cxu...@yahoo.com wrote:
>> Hi,
>> I apologize if this question is too stupid... basically I want to
>> build a protocol analyzer with a CoolRunner II cpld. the CPLD will
>> watch the bus line and extract data. I have passed behaviorial
>> simulation and fitted the device. but post-fit timing simulation gives
>> me some setup time violations and the output goes to X afterwards. I
>> read document that says ASYNC_REG can be used but it is not  available
>> on coolrunner cpld. Then I'm very concerned about what happens in the
>> real circuit. The bus line will not switch in sync with the sampling
>> clock, due to different clock domains, jitters etc. what happens in
>> the real circuit when the setup time is violated? will the cpld go
>> into metastable state for ever? This must be an old problem that has
>> been long solved, but how? can anyone help? thanks a lot....
>>
>> Hsu
> 
> Just want to add that I have a local oversampling clock, and the bus
> could switch at anytime, say 0.1ns before the clock edge. and the cpld
> requires setup time of 1.8ns.

You can't get rid of metastability, but you can reduce it to
spectacularly low likelihoods.

The classic way of doing this is to route the signals through
extra flip-flops. 1-2 are usually enough for most applications.

Violating the setup time on the first FF gives you a certain
chance of it entering a metastable state. It won't stay in it
forever - it just takes longer to switch. The metastable state
must last longer than the clock period to affect the second FF,
which is very unlikely.

The critical setup time windows which could cause a problem are in
the sub-femtosecond range - somewhere within your setup time window.
I think Xilinx have a appnote somewhere about the details.

Kind regards,

Iwo


Article: 121023
Subject: Re: Cadence TestBuilder
From: Evan Lavelle <nospam@nospam.com>
Date: Fri, 22 Jun 2007 17:19:07 +0100
Links: << >>  << T >>  << A >>
On Fri, 22 Jun 2007 15:22:52 -0000, Amal <akhailtash@gmail.com> wrote:

>Does anyone have a copy of the last release of "Cadence TestBuilder"?
>I would appreciate if you can give me a copy.

What was the last release? I've got TestBuilder-01_30-s004_tar.gz, if
that's of any use.

Evan

Article: 121024
Subject: Re: Cadence TestBuilder
From: Amal <akhailtash@gmail.com>
Date: Fri, 22 Jun 2007 16:22:44 -0000
Links: << >>  << T >>  << A >>
On Jun 22, 12:19 pm, Evan Lavelle <nos...@nospam.com> wrote:
> On Fri, 22 Jun 2007 15:22:52 -0000, Amal <akhailt...@gmail.com> wrote:
> >Does anyone have a copy of the last release of "Cadence TestBuilder"?
> >I would appreciate if you can give me a copy.
>
> What was the last release? I've got TestBuilder-01_30-s004_tar.gz, if
> that's of any use.
>
> Evan

I think 1.3 was the last one.  Would you please email it to me?

Thanks,
-- Amal




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search