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Threads Starting May 1999
16086: 99/05/01: Enrico Migliore: IrDA controller macro: is it easy to design?
16090: 99/05/02: Karim EMBAREK: Re: IrDA controller macro: is it easy to design?
16087: 99/05/01: Steven K. Knapp: Re: ISP,schematics and sim for free???
16088: 99/05/01: <david@home.com>: ISP,schematics and sim for free???
16089: 99/05/01: muzo: 10KE dual port RAM help ?
16093: 99/05/02: Eli Keren: Re: 10KE dual port RAM help ?
16098: 99/05/03: Ed Mcgettigan: Re: 10KE dual port RAM help ?
16120: 99/05/04: muzo: Re: 10KE dual port RAM help ?
16124: 99/05/05: Ray Andraka: Re: 10KE dual port RAM help ?
16131: 99/05/05: muzo: Re: 10KE dual port RAM help ?
16134: 99/05/05: Stuart Clubb: Re: 10KE dual port RAM help ?
16094: 99/05/02: Kirton Morris: Any Material on advances in FPGA Technology
16109: 99/05/04: zule: Re: Any Material on advances in FPGA Technology
16117: 99/05/04: Alun Morris: Re: Any Material on advances in FPGA Technology
16095: 99/05/03: Jacob Eluz: Virtex
16096: 99/05/03: Lars Fomsgaard: Xilinx netlister - Workaround needed
16136: 99/05/05: Todd Kline: Re: Xilinx netlister - Workaround needed
16141: 99/05/06: Ken Yasui: Re: Xilinx netlister - Workaround needed
16183: 99/05/07: Andreas Schmidt: Re: Xilinx netlister - Workaround needed
16097: 99/05/03: <mlmtkv@hotmail.com>: I want your support 8565
16100: 99/05/03: <rajesh52@hotmail.com>: Verilog FAQ
16101: 99/05/03: HDL Conference: Fall VIUF Workshop Call For Papers
16106: 99/05/03: Gary Desrosiers: Anyone use 27256 for config?
16108: 99/05/03: Ray Andraka: Re: Anyone use 27256 for config?
16110: 99/05/04: M.Simon: Re: Anyone use 27256 for config?
16114: 99/05/04: Andy Peters: Re: Anyone use 27256 for config?
16128: 99/05/05: Brian Boorman: Re: Anyone use 27256 for config?
16133: 99/05/05: Andy Peters: Re: Anyone use 27256 for config?
16135: 99/05/05: Ray Andraka: Re: Anyone use 27256 for config?
16137: 99/05/05: Todd Kline: Re: Anyone use 27256 for config?
16107: 99/05/04: D. Polo: AHDL books
16175: 99/05/07: Steven K. Knapp: Re: AHDL books
16185: 99/05/07: bob elkind: Re: AHDL books
16111: 99/05/04: Rolf Aengenendt: Configuring Xilinx FPGAs
16112: 99/05/04: Brian Boorman: Re: Configuring Xilinx FPGAs
16126: 99/05/05: Rolf Aengenendt: RE: Configuring Xilinx FPGAs
16155: 99/05/06: Philip Freidin: Re: Configuring Xilinx FPGAs
16125: 99/05/05: Le mer Michel: Re: Configuring Xilinx FPGAs
16199: 99/05/09: Sandeep Mukthavaram: Re: Configuring Xilinx FPGAs
16113: 99/05/04: P.C.R. Beukelman: web synthesis
16115: 99/05/04: <igorft@my-dejanews.com>: StateCad, Renoir, EASE feedback
16116: 99/05/04: <igorft@my-dejanews.com>: Multi-cycle path analysis in MaxPlus II
16119: 99/05/04: Johnnyick: PLD & FPGA Conference & Exhibition 12/05/99
16121: 99/05/05: APP01: Looking for Vhdl/verilog functions
16127: 99/05/05: <satish_me@hotmail.com>: Reciprocator in VHDL
16129: 99/05/05: Ray Andraka: Re: Reciprocator in VHDL
16230: 99/05/11: <satish_me@hotmail.com>: Re: Reciprocator in VHDL
16279: 99/05/13: Ray Andraka: Re: Reciprocator in VHDL
16130: 99/05/05: John Cooley: Re: One Sheep Farmer's Impressions of SNUG'99
16143: 99/05/06: Lars Rzymianowicz: Re: One Sheep Farmer's Impressions of SNUG'99
16218: 99/05/10: John Cooley: Re: One Sheep Farmer's Impressions of SNUG'99
16138: 99/05/05: Pascal Buseyne: connecting an PS/2-mouse with an Altera FLEX10K20
16139: 99/05/05: jok: Bugs in place and route s/w....XLINX???
16151: 99/05/06: Ed Mcgettigan: Re: Bugs in place and route s/w....XLINX???
16153: 99/05/06: Tom Burgess: Re: Bugs in place and route s/w....XLINX???
16140: 99/05/06: ymlee: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
16142: 99/05/06: Emil Blaschek: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
16145: 99/05/06: Stuart Clubb: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
16150: 99/05/06: Ray Andraka: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for Altera FPGA?
16184: 99/05/07: Jim Kipps: Re: [Q]Do you recommend Altera MAXPLUS II9.01 as a VHDL compiler for
16144: 99/05/06: roman pollak: BGA Prototyping ?
16146: 99/05/06: Stephen Maudsley: Re: BGA Prototyping ?
16149: 99/05/06: Pascal Dornier: Re: BGA Prototyping ?
16165: 99/05/07: Edgar Conzen: Re: BGA Prototyping ?
16207: 99/05/10: roman pollak: Re: BGA Prototyping ?
16168: 99/05/07: roman pollak: Re: BGA Prototyping ?
16169: 99/05/07: rk: Re: BGA Prototyping ?
16193: 99/05/08: Rick Filipkiewicz: Re: BGA Prototyping ?
16171: 99/05/07: Ray Andraka: Re: BGA Prototyping ?
16172: 99/05/07: Stephen Maudsley: Re: BGA Prototyping ?
16177: 99/05/07: Bill Pringlemeir: Re: BGA Prototyping ?
16182: 99/05/07: <sw>: Re: BGA Prototyping ?
16147: 99/05/06: <craig_jacobs@asl-tk.com>: Re: BGA Prototyping ?
16148: 99/05/06: roman pollak: Re: BGA Prototyping ?
16174: 99/05/07: Helmut Juchems: Re: BGA Prototyping ?
16187: 99/05/07: Todd Kline: Re: BGA Prototyping ?
16190: 99/05/08: Also-Antal Csaba: Re: BGA Prototyping ?
16173: 99/05/07: Don Husby: Re: BGA Prototyping ?
16181: 99/05/07: Martin Whitaker: Re: BGA Prototyping ?
16232: 99/05/11: Brian Boorman: Re: BGA Prototyping ?
16189: 99/05/08: Chris Tate: Re: BGA Prototyping ?
16196: 99/05/08: Nicholas C. Weaver: Re: BGA Prototyping ?
16224: 99/05/10: <REMOVEldavis@spacey.net>: Re: BGA Prototyping ?
16152: 99/05/06: hhk: Fpga gates, PLD gates ASIC gates: Help us please.
16161: 99/05/06: Edward L. Hepler: Re: Fpga gates, PLD gates ASIC gates: Help us please.
16178: 99/05/07: Brian Drummond: Re: Fpga gates, PLD gates ASIC gates: Help us please.
16374: 99/05/19: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Fpga gates, PLD gates ASIC gates: Help us please.
16154: 99/05/06: Cemal Coemert (TIP): DSP in FPGA
16163: 99/05/07: Brian Pedersen: Re: DSP in FPGA
16170: 99/05/07: Ray Andraka: Re: DSP in FPGA
16375: 99/05/19: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: DSP in FPGA
16157: 99/05/06: Pete Zaitcev: PCI slave in FPGA?
16164: 99/05/07: Le mer Michel: Re: PCI slave in FPGA?
16179: 99/05/07: Rene Becker: Re: PCI slave in FPGA?
16180: 99/05/07: Rene Becker: Re: PCI slave in FPGA?
16192: 99/05/08: Juergen Otterbach: Re: PCI slave in FPGA?
16222: 99/05/10: Steven Casselman: Re: PCI slave in FPGA?
16223: 99/05/11: Willy_Tsai: We need engineer
16158: 99/05/06: John Janusson: Re: How do I design this ?
16160: 99/05/06: Zeki Basbuyuk: Re: How do I design this ?(synchronous interface)
16315: 99/05/15: Hal Murray: Re: How do I design this ?(synchronous interface)
16159: 99/05/07: Slavek Przepiorski: 68HC11+EPLD development system
16162: 99/05/07: <p_sin@my-dejanews.com>: "DACafe.com: The ultimate resource for the EDA customers"
16166: 99/05/07: Allan Herriman: Re: How do I design this ?
16167: 99/05/07: Allan Herriman: Re: How do I design this ?
16176: 99/05/07: <kamath@ecn.purdue.edu>: FPGA, PLD, EPLD, CPLD differences
16203: 99/05/10: J. Khatib: Re: FPGA, PLD, EPLD, CPLD differences
16212: 99/05/10: Francisco Barat Quesada: Re: FPGA, PLD, EPLD, CPLD differences
16376: 99/05/19: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: FPGA, PLD, EPLD, CPLD differences
16186: 99/05/07: Richard Chapman: problem with Prentice-Hall student edition Xilinx
16188: 99/05/07: Hobson Frater: Re: problem with Prentice-Hall student edition Xilinx
16191: 99/05/08: Mtootell: Anyone in the UK looking for FPGA/CPLD support ?
16194: 99/05/08: Hul Tytus: USB standard
16197: 99/05/09: Rune Baeverrud: Re: USB standard
16195: 99/05/08: J&P Lezcano: SE VENDE FINCA EN MADRID
16198: 99/05/09: Atif Zafar: Looking for Altera APEX board
16200: 99/05/10: zule: Re: Looking for Altera APEX board
16219: 99/05/10: <ems@riverside-machines.com.NOSPAM>: Re: Looking for Altera APEX board
16202: 99/05/10: J. Khatib: Bitstream size
16205: 99/05/10: Le mer Michel: Re: Bitstream size
16204: 99/05/10: Cheah Soo Lan: Downloading of Bitstream to program FPGA
16209: 99/05/10: Daniel Feldman: Divider core
16220: 99/05/10: Jonas Thor: Re: Divider core
16216: 99/05/10: asap: Synopsys DC & Modelsim
16235: 99/05/11: Todd Kline: Re: Synopsys DC & Modelsim
16248: 99/05/12: Kyungjin Jang: Re: Synopsys DC & Modelsim
16381: 99/05/19: <alex_schreiber@my-dejanews.com>: Re: Synopsys DC & Modelsim
16335: 99/05/17: Alan Fitch: Re: Synopsys DC & Modelsim
16337: 99/05/17: Laurens Drost: Re: Synopsys DC & Modelsim
16379: 99/05/19: <alex_schreiber@my-dejanews.com>: Re: Synopsys DC & Modelsim
16918: 99/06/16: jok: Re: Synopsys DC & Modelsim
16923: 99/06/17: Eric Venditti: Re: Synopsys DC & Modelsim
16217: 99/05/10: Carl Martin: Need Altera 10k Prototype bd
16233: 99/05/11: Steven K. Knapp: Re: Need Altera 10k Prototype bd
16240: 99/05/11: Michael Ayton: Re: Need Altera 10k Prototype bd
16302: 99/05/14: Edwin Grigorian: Re: Need Altera 10k Prototype bd
16225: 99/05/11: Jonas Thor: Synchronizer design?
16227: 99/05/11: Roland =?iso-8859-1?Q?Fr=F6hlich?=: Re: Synchronizer design?
16238: 99/05/11: Peter Alfke: Re: Synchronizer design?
16241: 99/05/11: Bob Sugar: Re: Synchronizer design?
16246: 99/05/11: Peter Alfke: Re: Synchronizer design?
16347: 99/05/17: Rickman: Re: Synchronizer design?
16249: 99/05/12: Roland =?iso-8859-1?Q?Fr=F6hlich?=: Re: Synchronizer design?
16260: 99/05/12: Ray Andraka: Re: Synchronizer design?
16273: 99/05/13: Mark Summerfield: Re: Synchronizer design?
16285: 99/05/13: Peter Alfke: Re: Synchronizer design?
16291: 99/05/14: Mark Summerfield: Re: Synchronizer design?
16292: 99/05/14: Bob Perlman: Re: Synchronizer design?
16323: 99/05/16: Magnus Homann: Re: Synchronizer design?
16340: 99/05/17: Peter Alfke: Re: Synchronizer design?
16344: 99/05/17: Andy Peters: Re: Synchronizer design?
16348: 99/05/18: Andreas Doering: Re: Synchronizer design?
16330: 99/05/16: Alvin E. Toda: Re: Synchronizer design?
16228: 99/05/11: Markus Michel: Re: Synchronizer design?
16236: 99/05/11: Todd Kline: Re: Synchronizer design?
16237: 99/05/11: Jamie Sanderson: Re: Synchronizer design?
16242: 99/05/11: Peter Alfke: Re: Synchronizer design?
16261: 99/05/12: Ray Andraka: Re: Synchronizer design?
16265: 99/05/12: Jamie Sanderson: Re: Synchronizer design?
16317: 99/05/15: Hal Murray: Re: Synchronizer design?
16307: 99/05/14: Tim Davis: Re: Synchronizer design?
16256: 99/05/12: Andreas Doering: Re: Synchronizer design?
16316: 99/05/15: Hal Murray: Re: Synchronizer design?
16226: 99/05/11: wannarat: USB core design
16231: 99/05/11: <frouatbi@my-dejanews.com>: Virtual fabs ...
16239: 99/05/11: Mike Walsh: Free FPGA Design Workshop
16243: 99/05/11: Tom Jackson: Formal Solutions for Static Verification: An ASIC and IC Design
16244: 99/05/11: Dan Oomkes: UART Design
16245: 99/05/11: Steven Casselman: Re: UART Design
16255: 99/05/12: Tippawan Aranwattananon: Re: UART Design
16992: 99/06/22: APS: Re: UART Design
16251: 99/05/12: roman pollak: Fancy Dram problem
16257: 99/05/12: Chip Brown: Re: Fancy Dram problem
16263: 99/05/12: Georg Acher: Re: Fancy Dram problem
16300: 99/05/14: roman pollak: Re: Fancy Dram problem
16333: 99/05/16: bunnyboy: Re: Fancy Dram problem
16336: 99/05/17: Matthias Monhart: Re: Fancy Dram problem
16264: 99/05/12: Mike Treseler: Re: Fancy Dram problem
16278: 99/05/13: DmitrySn: Re: Fancy Dram problem
16281: 99/05/13: DmitrySn: Re: Fancy Dram problem
16299: 99/05/14: Olaf Birkeland: Re: Fancy Dram problem
16311: 99/05/14: Andy Peters: Re: Fancy Dram problem
16312: 99/05/15: Phil Short: Re: Fancy Dram problem
16321: 99/05/15: Steve Rencontre: Re: Fancy Dram problem
16354: 99/05/18: Rickman: Re: Fancy Dram problem
16343: 99/05/17: Andy Peters: Re: Fancy Dram problem
16352: 99/05/18: roman pollak: Re: Fancy Dram problem
16290: 99/05/13: Phil Short: Re: Fancy Dram problem
16360: 99/05/18: <woodyj@pptvision.com>: Re: Fancy Dram problem
16253: 99/05/12: Daryl Bradley: Virtex development boards
16259: 99/05/12: Christof Teuscher: Re: Virtex development boards
16268: 99/05/12: Jonathan Feifarek: Re: Virtex development boards
16254: 99/05/12: Tippawan Aranwattananon: How synthesize tools concern with size of the design?
16262: 99/05/12: Ray Andraka: Re: How synthesize tools concern with size of the design?
16275: 99/05/12: Phil Hays: Re: How synthesize tools concern with size of the design?
16286: 99/05/13: Jim Kipps: Re: How synthesize tools concern with size of the design?
16293: 99/05/13: Ray Andraka: Re: How synthesize tools concern with size of the design?
16313: 99/05/14: Jim Kipps: Re: How synthesize tools concern with size of the design?
16314: 99/05/15: Hal Murray: Re: How synthesize tools concern with size of the design?
16318: 99/05/15: Ray Andraka: Re: How synthesize tools concern with size of the design?
16413: 99/05/20: <ems@riverside-machines.com.NOSPAM>: Re: How synthesize tools concern with size of the design?
16427: 99/05/21: Magnus Homann: Re: How synthesize tools concern with size of the design?
16445: 99/05/22: Stuart Clubb: Re: How synthesize tools concern with size of the design?
16478: 99/05/25: Stuart Clubb: Re: How synthesize tools concern with size of the design?
16431: 99/05/21: Andy Peters: Re: How synthesize tools concern with size of the design?
16464: 99/05/24: <ems@riverside-machines.com.NOSPAM>: Re: How synthesize tools concern with size of the design?
16467: 99/05/24: Jim Kipps: Re: How synthesize tools concern with size of the design?
16476: 99/05/25: Magnus Homann: Re: How synthesize tools concern with size of the design?
16322: 99/05/15: Jan Gray: Re: How synthesize tools concern with size of the design?
16331: 99/05/17: Austin Franklin: Re: How synthesize tools concern with size of the design?
16423: 99/05/21: David Pashley: Re: How synthesize tools concern with size of the design?
16428: 99/05/21: David Pashley: Re: How synthesize tools concern with size of the design?
16475: 99/05/25: David Pashley: Re: How synthesize tools concern with size of the design?
16269: 99/05/13: basaro: Can use pullup in XC9500XL?
16276: 99/05/12: Mamoon Hamid: Re: Can use pullup in XC9500XL?
16270: 99/05/13: Jean-Francois Richard: floating points to fixed points on a FPGA
16272: 99/05/12: Steven Casselman: Re: floating points to fixed points on a FPGA
16288: 99/05/13: Bhaskar Thiagarajan: Re: floating points to fixed points on a FPGA
16488: 99/05/25: Peter Sels: Re: floating points to fixed points on a FPGA
16536: 99/05/26: Martin Filteau: Re: floating points to fixed points on a FPGA
16492: 99/05/25: Peter Sels: Re: floating points to fixed points on a FPGA
16271: 99/05/13: Jean-Francois Richard: Reference on word lenght quantization
16282: 99/05/13: info: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16289: 99/05/13: Jonathan Bromley: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16297: 99/05/14: Duncan Crowther: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16327: 99/05/16: <Steve@s-deweynospam.demon.co.uk>: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
16283: 99/05/13: Davide Falchieri: Xilinx demo board
16332: 99/05/17: Ken Yasui: Re: Xilinx demo board
16678: 99/06/02: <sparky_chan@ibm.net>: Xilinx XC9500 series product term 3-state (tPTTS) time delays
16284: 99/05/13: Timothy Miller: Verilog example for Xilinx?
16287: 99/05/13: Brian Philofsky: Re: Verilog example for Xilinx?
16306: 99/05/14: Stuart Clubb: Re: Verilog example for Xilinx?
16296: 99/05/14: Andreas Doering: On-chip intercinnection system survey?
16298: 99/05/14: <username@dso.org.sg>: How to physically implement the fuse map of a PLA
16301: 99/05/14: Rickman: Bitstream Compression
16310: 99/05/14: Armin Mueller: Re: Bitstream Compression
16304: 99/05/14: Yoo: Who do you know? Motorola FPGA
16305: 99/05/14: Philip Freidin: Re: Who do you know? Motorola FPGA
16308: 99/05/14: Peter Alfke: Re: Who do you know? Motorola FPGA
16309: 99/05/14: Peter Alfke: Re: Who do you know? Motorola FPGA
16320: 99/05/15: NO-SPAM damiano: Re: Who do you know? Motorola FPGA
16319: 99/05/15: lijun2611: How can I get a ISA/PCI BUS model?
16493: 99/05/25: Pavel Zivny: Re: How can I get a ISA/PCI BUS model?
16324: 99/05/16: Italian Cowboy: Re: High Speed Reconfigurability
16325: 99/05/16: Italian Cowboy: High Speed Reconfigurability, Re:
16380: 99/05/19: Michael Barr: Re: High Speed Reconfigurability, Re:
16385: 99/05/19: Steven Casselman: Re: High Speed Reconfigurability
16414: 99/05/20: Jonathan Feifarek: Re: High Speed Reconfigurability
16416: 99/05/20: Steven Casselman: Re: High Speed Reconfigurability
16429: 99/05/21: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16420: 99/05/21: Roland Paterson-Jones: Re: High Speed Reconfigurability
16422: 99/05/21: Roland Paterson-Jones: Re: High Speed Reconfigurability
16436: 99/05/21: Michael Schuerig: Re: High Speed Reconfigurability
16442: 99/05/22: Roland PJ Pipex Account: Re: High Speed Reconfigurability
16469: 99/05/24: Jonathan Feifarek: Re: High Speed Reconfigurability
16481: 99/05/25: Rickman: Re: High Speed Reconfigurability
16482: 99/05/25: Stuart D. Gathman: Re: High Speed Reconfigurability
16483: 99/05/25: Jonathan Feifarek: Re: High Speed Reconfigurability
16509: 99/05/26: Roland Paterson-Jones: Re: High Speed Reconfigurability
16470: 99/05/24: Jonathan Feifarek: Re: High Speed Reconfigurability
16430: 99/05/21: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16452: 99/05/23: Tim Tyler: Re: High Speed Reconfigurability
16511: 99/05/26: Roland Paterson-Jones: Re: High Speed Reconfigurability
16521: 99/05/26: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16525: 99/05/26: Tim Tyler: Re: High Speed Reconfigurability
16529: 99/05/26: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16530: 99/05/26: Ray Andraka: Re: High Speed Reconfigurability
16534: 99/05/26: Jonathan Feifarek: Re: High Speed Reconfigurability
16549: 99/05/27: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16551: 99/05/27: Ray Andraka: Re: High Speed Reconfigurability
16564: 99/05/28: Rickman: Re: High Speed Reconfigurability
16578: 99/05/28: Ray Andraka: Re: High Speed Reconfigurability
16548: 99/05/27: Tim Tyler: Re: High Speed Reconfigurability
16552: 99/05/27: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16560: 99/05/28: Roland Paterson-Jones: Re: High Speed Reconfigurability
16561: 99/05/28: Tim Tyler: Re: High Speed Reconfigurability
16433: 99/05/21: Tim Tyler: Re: High Speed Reconfigurability
16444: 99/05/22: Roland PJ Pipex Account: Re: High Speed Reconfigurability
16453: 99/05/23: Tim Tyler: Re: High Speed Reconfigurability
16474: 99/05/25: Roland PJ Pipex Account: Re: High Speed Reconfigurability
16468: 99/05/24: Jonathan Feifarek: Re: High Speed Reconfigurability
16479: 99/05/25: Tim Tyler: Re: High Speed Reconfigurability
16490: 99/05/25: Jonathan Feifarek: Re: High Speed Reconfigurability
16484: 99/05/25: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16434: 99/05/21: Steven Casselman: Re: High Speed Reconfigurability
16449: 99/05/23: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16438: 99/05/21: Italian Cowboy: R: High Speed Reconfigurability
16486: 99/05/25: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16510: 99/05/26: Roland Paterson-Jones: Re: High Speed Reconfigurability
16522: 99/05/26: <brian_n_miller@yahoo.com>: Re: High Speed Reconfigurability
16542: 99/05/27: Roland Paterson-Jones: Re: High Speed Reconfigurability
16556: 99/05/27: Steven Casselman: Re: High Speed Reconfigurability
16386: 99/05/19: Italian Cowboy: R: High Speed Reconfigurability, Re:
16328: 99/05/16: Swapnajit Mittra: Verilog PLI website
16649: 99/06/01: <andi_carmon@my-deja.com>: Re: Verilog PLI website
16691: 99/06/03: Swapnajit Mittra: Re: Verilog PLI website
16753: 99/06/07: <andi_carmon@my-deja.com>: Re: Verilog PLI website
16712: 99/06/03: Bob Beckwith: Re: Verilog PLI website
16329: 99/05/16: Keyvan Irani: Altera to Clear Logic Conversion
16334: 99/05/17: wannarat: Glue logic
16339: 99/05/17: Peter Schulz: Re: Glue logic
16358: 99/05/18: Elder V Costa: Re: Glue logic
16338: 99/05/17: J. Khatib: Dual Port mem
16369: 99/05/19: Eduardo Augusto Bezerra: Re: Dual Port mem
16371: 99/05/19: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Dual Port mem
16539: 99/05/26: Scott Winick: Re: Dual Port mem
16341: 99/05/17: Bill Kury: 4062XL problems and solutions
16350: 99/05/18: Le mer Michel: Re: 4062XL problems and solutions
16351: 99/05/18: Hal Murray: Re: 4062XL problems and solutions
16454: 99/05/23: Ray Andraka: Re: 4062XL problems and solutions
16353: 99/05/18: Rickman: Re: 4062XL problems and solutions
16359: 99/05/18: Brian Philofsky: Re: 4062XL problems and solutions
16364: 99/05/18: Cant Tell You: Re: 4062XL problems and solutions
16342: 99/05/17: <micheal_thompson@my-dejanews.com>: Post route simulation: EDIF or VHDL?
16349: 99/05/18: Yves Tchapda: Re: Post route simulation: EDIF or VHDL?
16355: 99/05/18: William White: Re: Post route simulation: EDIF or VHDL?
16345: 99/05/17: mta: Looking for VHDL Phase Locked Loop design
16356: 99/05/18: Jim Kipps: Case study: Viewlogic's IntelliFlow
16405: 99/05/20: Bill Kury: Re: Case study: Viewlogic's IntelliFlow
16410: 99/05/20: Jim Kipps: Re: Case study: Viewlogic's IntelliFlow
16455: 99/05/23: Ray Andraka: Re: Case study: Viewlogic's IntelliFlow
16357: 99/05/18: Alain Cloet: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16400: 99/05/20: Klaus Falser: Re: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16412: 99/05/20: Alain Cloet: Re: Onboard JTAG-programming Xilinx CPLD with Found.Series?
16361: 99/05/18: John Cooley: Yikes! Only 2 Days Left For The Boston SNUG Call-For-Papers !
16362: 99/05/18: Rich McNeil: JTAG program Altera and Xilinx same chain?
16370: 99/05/19: Steve Rencontre: Re: JTAG program Altera and Xilinx same chain?
16363: 99/05/19: Tibor Szolnoki: Need crack
16365: 99/05/18: Andy Peters: Re: Need crack
16366: 99/05/18: rk: Re: Need crack
16367: 99/05/19: Uday Godbole: Is schmitt trigger possible with Xilinx 9536?
16377: 99/05/19: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Is schmitt trigger possible with Xilinx 9536?
16383: 99/05/19: Peter Alfke: Re: Is schmitt trigger possible with Xilinx 9536?
16397: 99/05/20: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Is schmitt trigger possible with Xilinx 9536?
16382: 99/05/19: Leon Heller: Re: Is schmitt trigger possible with Xilinx 9536?
16396: 99/05/20: Peter =?iso-8859-1?Q?S=F8rensen?=: Re: Is schmitt trigger possible with Xilinx 9536?
16401: 99/05/20: Leon Heller: Re: Is schmitt trigger possible with Xilinx 9536?
16406: 99/05/20: Michael Ayton: Re: Is schmitt trigger possible with Xilinx 9536?
16456: 99/05/23: Ray Andraka: Re: Is schmitt trigger possible with Xilinx 9536?
16495: 99/05/25: Pavel Zivny: Re: Is schmitt trigger possible with Xilinx 9536?
16368: 99/05/19: Peter Sels: Aries Ballnet sockets?
16378: 99/05/19: Dominic Reitman: Foundation FPGA Express
16399: 99/05/20: Le mer Michel: Re: Foundation FPGA Express
16409: 99/05/20: Jim Kipps: Re: Foundation FPGA Express
16384: 99/05/19: Elder V Costa: Xilinx Foundation Archiving
16388: 99/05/19: Tom McLaughlin: Assigning pad type in Xilinx Virtex FPGA
16446: 99/05/22: Stuart Clubb: Re: Assigning pad type in Xilinx Virtex FPGA
16504: 99/05/26: Simon Goble: Re: Assigning pad type in Xilinx Virtex FPGA
16389: 99/05/19: Peekay Chan: Internal visibility and EDIF/VHDL
16390: 99/05/19: Adam J. Elbirt: Xilinx M1.5 Crash
16391: 99/05/20: david langmann: Re: Xilinx M1.5 Crash
16392: 99/05/19: Andy Peters: Re: Xilinx M1.5 Crash
16393: 99/05/19: Adam J. Elbirt: Re: Xilinx M1.5 Crash
16394: 99/05/20: Bob Sefton: Re: Xilinx M1.5 Crash
16395: 99/05/20: Adam J. Elbirt: Re: Xilinx M1.5 Crash
16451: 99/05/23: Zoltan Kocsi: Re: Xilinx M1.5 Crash
16461: 99/05/24: Bob Sefton: Re: Xilinx M1.5 Crash
16472: 99/05/25: Zoltan Kocsi: Re: Xilinx M1.5 Crash
16477: 99/05/25: Peter: Re: Xilinx M1.5 Crash
16480: 99/05/25: Rickman: Re: Xilinx M1.5 Crash
16500: 99/05/26: Zoltan Kocsi: Re: Xilinx M1.5 Crash
16532: 99/05/26: Rickman: Re: Xilinx M1.5 Crash
16540: 99/05/27: Zoltan Kocsi: Re: Xilinx M1.5 Crash
16543: 99/05/27: Daniel K. Elftmann: Re: Xilinx M1.5 Crash
16555: 99/05/28: Zoltan Kocsi: Re: Xilinx M1.5 Crash
16566: 99/05/28: Rickman: Re: Xilinx M1.5 Crash
16589: 99/05/29: Jamie Lokier: Re: Xilinx M1.5 Crash
16408: 99/05/20: Andy Peters: Re: Xilinx M1.5 Crash
16411: 99/05/20: Adam J. Elbirt: Re: Xilinx M1.5 Crash
16421: 99/05/21: Kim Hofmans: Re: Xilinx M1.5 Crash
16417: 99/05/21: zule: Re: Xilinx M1.5 Crash
16418: 99/05/20: Adam J. Elbirt: Re: Xilinx M1.5 Crash
16432: 99/05/21: Bret Wade: Re: Xilinx M1.5 Crash
16502: 99/05/26: Simon Goble: Re: Xilinx M1.5 Crash
16402: 99/05/20: Klaus Falser: Makefile for Xilinx Foundation 1.4
16404: 99/05/20: Rickman: DSP Board for PC/104 Bus
16407: 99/05/20: Mike Treseler: Re: DSP Board for PC/104 Bus
16415: 99/05/20: Rickman: Re: DSP Board for PC/104 Bus
16520: 99/05/26: <rrohatgi@kendra.com>: Re: DSP Board for PC/104 Bus
16526: 99/05/26: Rickman: Re: DSP Board for PC/104 Bus
16547: 99/05/27: <rrohatgi@kendra.com>: Re: DSP Board for PC/104 Bus
16497: 99/05/25: APS: Re: DSP Board for PC/104 Bus
16419: 99/05/21: Oliver Diessel: Call for Papers: RAW 2000 (Reconfigurable Architectures Workshop)
16425: 99/05/21: Rob Putala: Request FAQ
16458: 99/05/23: Ray Andraka: Re: Request FAQ
16426: 99/05/21: Herman Schmit: CFP: FPGA 2000
16435: 99/05/21: Steven Casselman: Re: High Speed Reconfigurability
16437: 99/05/21: Joao Manuel Paiva Cardoso: Re: High Speed Reconfigurability
16439: 99/05/21: Steven Casselman: [Fwd: High Speed Reconfigurability]
16440: 99/05/21: Jan Gray: The Economist article: "Hardware goes soft"
16679: 99/06/02: <sparky_chan@no_spam_ibm.net>: speed optimisation for Xilinx XC9500
16441: 99/05/22: Ivan: Xilinx device readback through parallel port
16443: 99/05/22: Vasant Ram: JTAG: Altera & Xilinx
16448: 99/05/22: Dave D'Aurelio: Re: JTAG: Altera & Xilinx
16450: 99/05/23: Rich McNeil: Re: JTAG: Altera & Xilinx
16541: 99/05/27: zule: Re: JTAG: Altera & Xilinx
16447: 99/05/22: Edward Moore: IOB tristate register in Xilinx XLA devices
16460: 99/05/24: David Hawke: Re: IOB tristate register in Xilinx XLA devices
16459: 99/05/24: Chris: For Sale: Altera Max+Plus II
16471: 99/05/24: muzo: virtex vs apex20k family comparison for DSP ?
16565: 99/05/28: Ray Andraka: Re: virtex vs apex20k family comparison for DSP ?
16642: 99/06/01: Brent A. Hayhoe: Re: virtex vs apex20k family comparison for DSP ?
16700: 99/06/03: Magnus Homann: Re: virtex vs apex20k family comparison for DSP ?
16718: 99/06/04: Don Husby: Re: virtex vs apex20k family comparison for DSP ?
16473: 99/05/25: <username@dso.org.sg>: LUT implementation in XC3000
16485: 99/05/25: Philip Freidin: Re: LUT implementation in XC3000
16487: 99/05/25: Tximo: Synthesis problem
16496: 99/05/25: Jason T. Wright: Re: Synthesis problem
16498: 99/05/25: Jason T. Wright: Re: Synthesis problem
16513: 99/05/26: Alan Fitch: Re: Synthesis problem
16514: 99/05/26: Tximo: Re: Synthesis problem Solved. Thanks to all
16528: 99/05/26: Elder V Costa: Re: Synthesis problem
16577: 99/05/28: Elder V Costa: Re: Synthesis problem
16489: 99/05/25: Frank Scherler: JOB WANTED
16491: 99/05/25: Frank Scherler: JOB WANTED
16499: 99/05/25: David Langmann: Beginner's Virtex pinout Question
16501: 99/05/26: zule: Re: Beginner's Virtex pinout Question
16503: 99/05/26: <lalitm@my-dejanews.com>: Reconfiguarble chips.
16607: 99/05/30: =?iso-8859-1?Q?Jos=E9?= Antonio Moreno Zamora: Re: Reconfiguarble chips.
16505: 99/05/26: Gabriel Tello González: SUMESE A NUESTRO EXITO!!!!
16507: 99/05/26: Enrico Migliore: C to VHDL translator?
16512: 99/05/26: Eduardo Augusto Bezerra: Re: C to VHDL translator?
16517: 99/05/26: Herman Beke: Re: C to VHDL translator?
16523: 99/05/26: Michael Barr: Re: C to VHDL translator?
16559: 99/05/28: Baris Aksoy: Re: C to VHDL translator?
16515: 99/05/26: Tximo: Instantiate Clocks
16537: 99/05/27: zule: Re: Instantiate Clocks
16516: 99/05/26: <micheal_thompson@my-dejanews.com>: FPGA express : Schematic viewing options w/o Vista?
16518: 99/05/26: David Gesswein: Re: FPGA express : Schematic viewing options w/o Vista?
16533: 99/05/26: Phil Hays: Re: FPGA express : Schematic viewing options w/o Vista?
16538: 99/05/27: zule: Re: FPGA express : Schematic viewing options w/o Vista?
16519: 99/05/26: Ruediger Becker: Leakage Current
16531: 99/05/27: <prastogi@my-dejanews.com>: C to EDIF translator??Anyone?
16535: 99/05/27: Gene N: Re: C to EDIF translator??Anyone?
16557: 99/05/28: Tom Kean: Re: C to EDIF translator??Anyone?
16544: 99/05/27: <username@dso.org.sg>: CFI (CAD Framework Initiative) webpage - DR documentation
16546: 99/05/27: Heinrich Fonfara: High speed with VHDL
16562: 99/05/28: Jamie Sanderson: Re: High speed with VHDL
16563: 99/05/28: Ray Andraka: Re: High speed with VHDL
16550: 99/05/27: <micheal_thompson@my-deja.com>: FPGA express + VHDL: strange SR implementation?
16571: 99/05/28: Rickman: Re: FPGA express + VHDL: strange SR implementation?
16576: 99/05/28: <micheal_thompson@my-deja.com>: Re: FPGA express + VHDL: strange SR implementation?
16582: 99/05/28: Rickman: Re: FPGA express + VHDL: strange SR implementation?
16573: 99/05/28: Stephen J. Byrne: Re: FPGA express + VHDL: strange SR implementation?
16605: 99/05/29: Alvin E. Toda: Re: FPGA express + VHDL: strange SR implementation?
16588: 99/05/28: <ems@riverside-machines.com.NOSPAM>: Re: FPGA express + VHDL: strange SR implementation?
16595: 99/05/28: Rickman: Re: FPGA express + VHDL: strange SR implementation?
16597: 99/05/29: <ems@riverside-machines.com.NOSPAM>: Re: FPGA express + VHDL: strange SR implementation?
16602: 99/05/29: Rickman: Re: FPGA express + VHDL: strange SR implementation?
16617: 99/05/31: <micheal_thompson@my-deja.com>: Re: FPGA express + VHDL: strange SR implementation?
16619: 99/05/31: Rickman: Re: FPGA express + VHDL: strange SR implementation?
16622: 99/05/31: Alvin E. Toda: Re: FPGA express + VHDL: strange SR implementation?
16653: 99/06/01: Brian Boorman: Re: FPGA express + VHDL: strange SR implementation?
16646: 99/06/01: Steve Rencontre: Re: FPGA express + VHDL: strange SR implementation?
16663: 99/06/01: <ems@riverside-machines.com.NOSPAM>: Re: FPGA express + VHDL: strange SR implementation?
16553: 99/05/27: Mike Walsh: Free Hardware/Software Co-Verification Workshop - Raleigh, NC
16554: 99/05/27: Nestor C.: Pipeline/Delay Stages in a Feedback Loop
16558: 99/05/27: Garrick Kremesec: RAM for external/internal use
16572: 99/05/28: Rickman: Re: RAM for external/internal use
16574: 99/05/28: Garrick Kremesec: Re: RAM for external/internal use
16579: 99/05/28: Ray Andraka: Re: RAM for external/internal use
16584: 99/05/28: Garrick Kremesec: Re: RAM for external/internal use
16583: 99/05/28: Rickman: Re: RAM for external/internal use
16591: 99/05/28: Ray Andraka: Re: RAM for external/internal use
16630: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16631: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16632: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16633: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16634: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16635: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16636: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16637: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16638: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16639: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16640: 99/06/01: ron van smoorenburg: Re: RAM for external/internal use
16567: 99/05/28: ron van smoorenburg: Rom use, Renoir => leonardo => maxplus2
16581: 99/05/28: Stuart Clubb: Re: Rom use, Renoir => leonardo => maxplus2
16568: 99/05/28: ron van smoorenburg: Rom use, Renoir => leonardo => maxplus2
16569: 99/05/28: ron van smoorenburg: Rom use, Renoir => leonardo => maxplus2
16570: 99/05/28: ron van smoorenburg: Rom use, Renoir => leonardo => maxplus2
16575: 99/05/28: Bernd Schmidt: Dynamically reconfigurable devices
16580: 99/05/28: Ray Andraka: Re: Dynamically reconfigurable devices
16585: 99/05/28: Jonathan Feifarek: Re: Dynamically reconfigurable devices
16592: 99/05/28: Ray Andraka: Re: Dynamically reconfigurable devices
16593: 99/05/28: Rickman: Re: Dynamically reconfigurable devices
16586: 99/05/28: Jonathan Feifarek: Evolutionary computation
16594: 99/05/28: Rickman: Re: Evolutionary computation
16604: 99/05/29: Tim Tyler: Re: Evolutionary computation
16666: 99/06/01: Jonathan Feifarek: Re: Evolutionary computation
16685: 99/06/02: Tim Tyler: Re: Evolutionary computation
16686: 99/06/02: Jonathan Feifarek: Re: Evolutionary computation
16688: 99/06/02: John McCluskey: Re: Evolutionary computation
16706: 99/06/03: Tim Tyler: Re: Evolutionary computation
16705: 99/06/03: Tim Tyler: Re: Evolutionary computation
16690: 99/06/02: Ray Andraka: Re: Evolutionary computation
16771: 99/06/08: Philip Freidin: Re: Evolutionary computation
16790: 99/06/08: Tim Tyler: Re: Evolutionary computation
16794: 99/06/09: Hal Murray: Re: Evolutionary computation
16805: 99/06/09: Tim Tyler: Re: Evolutionary computation
16904: 99/06/16: Jack Greenbaum: Re: Evolutionary computation
16928: 99/06/17: Tim Tyler: Re: Evolutionary computation
16696: 99/06/03: Delon Levi: Re: Evolutionary computation
16587: 99/05/28: Craig Yarbrough: Generating GSR From Within Chip
16598: 99/05/29: <ems@riverside-machines.com.NOSPAM>: Re: Generating GSR From Within Chip
16603: 99/05/29: Rickman: Re: Generating GSR From Within Chip
16616: 99/05/31: Le mer Michel: Re: Generating GSR From Within Chip
16618: 99/05/31: Rickman: Re: Generating GSR From Within Chip
16662: 99/06/01: <ems@riverside-machines.com.NOSPAM>: Re: Generating GSR From Within Chip
16671: 99/06/01: Rickman: Re: Generating GSR From Within Chip
16590: 99/05/28: Steven Casselman: Transmogrifier C
16599: 99/05/29: Oniria: SE TI INTERESSA ARCHICAD 6.0,LIHTWAVE 5.6,PHOTOSHOP5.0,AUTOCAD 14ita,etc ,postami.
16600: 99/05/29: Jamil Khatib: Modelsim, VHDL & mem core
16601: 99/05/29: <mench@mench.com>: Re: Modelsim, VHDL & mem core
16680: 99/06/02: Stephen Fraleigh: Re: Modelsim, VHDL & mem core
16681: 99/06/02: Stephen Fraleigh: Re: Modelsim, VHDL & mem core
16606: 99/05/30: Carlos Stahr: Application Consulting Engineer (ACE)
16608: 99/05/30: David Heller: Call for Papers/Articles
16609: 99/05/30: <nbsfor@home.com>: @home & networks 6282
16610: 99/05/31: Jon Cummings: just a test - an ISP check
16611: 99/05/31: <lpjwll@sssdfdf.org>: YOURE NOT GOING TO BELIEVE THIS! 7449
16612: 99/05/30: bayowolf: Re: YOURE NOT GOING TO BELIEVE THIS! 7449
16645: 99/06/01: Steve Rencontre: Re: YOURE NOT GOING TO BELIEVE THIS! 7449
16614: 99/05/31: Duck Foot: sif_wildcard_eql?
16615: 99/05/31: <username@dso.org.sg>: ANy good recommendations for Books on FPGA
16654: 99/06/01: Steven K. Knapp: Re: ANy good recommendations for Books on FPGA
16683: 99/06/02: <prastogi@my-deja.com>: Re: ANy good recommendations for Books on FPGA
16620: 99/05/31: Rickman: Printing to picture files
16623: 99/05/31: Ray Andraka: Re: Printing to picture files
16624: 99/05/31: Ray Andraka: Re: Printing to picture files
16657: 99/06/01: Rickman: Re: Printing to picture files
16629: 99/06/01: Alan Fitch: Re: Printing to picture files
16644: 99/06/01: Jonas Thor: Re: Printing to picture files
16655: 99/06/01: Rickman: Re: Printing to picture files
16661: 99/06/01: Jonas Thor: Re: Printing to picture files
16672: 99/06/02: Thierry Garrel: Re: Printing to picture files : my experience with Viewlogic
16674: 99/06/02: Rickman: Re: Printing to picture files : my experience with Viewlogic
16675: 99/06/02: Philip Freidin: Re: Printing to picture files : my experience with Viewlogic
16647: 99/06/01: Steve Rencontre: Re: Printing to picture files
16670: 99/06/01: Rickman: Re: Printing to picture files
16676: 99/06/02: Emmanuel JOLLY: Re: Printing to picture files
16673: 99/06/02: Alex Sherstuk: Re: Printing to picture files
16682: 99/06/02: Don Husby: Re: Printing to picture files
16684: 99/06/02: Ray Andraka: Re: Printing to picture files
16621: 99/05/31: KPDURHAM: !US-NC-Chapel Hill-FPGA Design Engineer/HOT
16625: 99/05/31: bayowolf: Re: LOOK WHAT SOMEBODY PUT ON THEIR WEBSITE! 278
16741: 99/06/06: Brother David, FFCS: Modems ... & stuff
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