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lfcoug@sssdfdf.org wrote: > zhbrtrzltfcswkhvjjhonlsibkdffuwtrijchyspgtkmklgpesuzbiubcwxg I'll be sure not to go to that website, then, since you've already told us. Enough already with the poor typing. Practice these words: "BAD KITTY", "FLUFFY!! GET AWAY FROM THAT KEYBOARD NOW!!!" Get a life already! -Alan -- For a free weekly homeschooling newsletter, devotions, lesson plans, and more, visit http://www.THSresources.com. A member of the A+ Thematic Units Webring . Chat with me on ICQ #6913463 or AOL IM username flowoyab (bayowolf backwards) Remember: any excuse that starts with but(t) already has a crack in it. (Alan Hunter)Article: 16626
http://38.201.46.9/index.asp?rs=n52399 <a href="http://38.201.46.9/index.asp?rs=n52399">CLICK HERE</a> TO CHECK IT OUT omxdmjwefyxrvqlsgjufhzuwmrenorqysdbxqiqrfjshdmpudjvvxcjodriArticle: 16629
In article <37532488.C35A2D64@ids.net>, Ray Andraka <randraka@ids.net> writes >Rick, > >You can print to a PDF (which tells me you probably have Acrobat exchange). >Once you have the PDF file, open it with acrobat exchange, select the >graphic (set the select graphic option in the tools menu). Now zoom way in >before you copy it to the clipboard. You can then paste the image to your >word file without it getting fuzzy. > >Apparently when you copy an acrobat image to the clipboard, it converts the >image at the current zoom into a bit map. By zooming in, you get better >quality images. No, I didn't find this written anywhere. I discovered it >by accident when I was trying to do pretty much the same thing you are. > >Rickman wrote: > >> I am working on documentaion for my last design and I would like to >> include schematic pages in the document. I could just print them out and >> add the pages. But I was tring to add them electronically so that >> everything is in one file. >> >> I am writing this in Word 97 and using Xilinx Foundation 1.5i for the >> schematic capture. I was able to print to a PDF file, but Word won't >> accept that as a picture. I also tried printing Postscript to a file, >> but Word won't show that on the screen. It will only print it to a >> Postscript printer. >> >> Does anyone have an idea of how to do this? Are there any programs that >> will let me print the schematic to a picture file without a big loss of >> resolution? I found that I could cut and paste from Acrobat to Word. But >> the intermediate file format was a bit mapped file of some type and most >> of the text blurred a great deal. >> >> -- The other thing you can try is to change the dots per inch setting under the "settings" of the desktop. This makes all the buttons on the user interface big (and they will possibly drop off the screen!), but you can then capture the image off the screen using e.g. Paint Shop Pro, and it will have higher resolution. A bit of a bodge... kind regards Alan -- Alan Fitch DOULOS, Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK Tel: +44 (0)1425 471 223 Email: alan@doulos.com Fax: +44 (0)1425 471 573 ** Visit THE WINNING EDGE www.doulos.com **Article: 16630
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16631
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16632
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16633
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16634
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16635
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16636
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16637
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16638
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16639
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16640
hi, i was wondering whether time multiplexing an option is? When you have give a signal to indicate data available then you possibly can delay that one? ron. Garrick Kremesec wrote in message <374E0988.E1027D7A@ews.uiuc.edu>... >Hello, > > I am very new to FPGA vhdl programming, but I have done a lot of work >with PLD (yes, big diff. in use, style, difficult, etc.). Anyway, >starting from scratch, I am using Max Plus 9.23 and working with an >EPF10K10 FPGA. > >I have most of my microcontroller control lines, several address lines, >and my 16 bit data bus connected to the FPGA. I would like a memory >block (64 words of data) that I can read or write to using the >microcontroller, but I can also work with internally. > >For instance, I have an ADC connected to the FPGA which will be flipping >through a mux and reading values and I want them stored in these memory >locations. > >Also, I have to generate 8 PWM signals. I want the microcontroller to >be able to send configuation bytes with information on duty cycle. > >I can't figure out how to do this. The ram/rom packages I could find >all appear to not allow other internal access simulateneously of this >memory: > >I thought I would have to set up dual port memory, but the only dual >port ram component Altera has places the input and output of BOTH ports >on seperate lines! Thats 64 data lines for a 16 bit, dual port ram. >Perhaps I'm not looking in the right places. And perhaps there is a way >to combine the data lines into one I/O/tristate internally and >externally. Any help will be greatly appreciated. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16641
I am a beginner in VHDL coding and I would like to place
a fixed delay in my (synchronous) finite state machine,
but I do not want to use "external" counter or to implement
a certain number of "idle" states in FSM.
Is it possible (and reasonable) to use a kind of iteration
scheme ("for" loop) within FSM state(s)?
Jarek
Article: 16642Good assessment Ray. In article <374EA3CA.DD3B6870@ids.net>, Ray Andraka <randraka@ids.net> writes: >First a quick overview of the pertinent 20K improvements: >1. EABs have an added capability for product terms, sort of a PAL like structure. >Each supports up to 32 product terms. These are useful for wide input functions, but >frankly, I don't see much application to DSP data-flow architectures. Agreed, and also, you can only use the product term function if you don't use the RAM (on a megaLAB by megaLAB basis) >2. The EAB in the 20KE has a content addressable memory mode. This is very useful >for sorting and searching. If your DSP application would benefit from this >capability, this may tip the scales in favor of the 20KE Agreed again, althoug Xilinx have inferred that they have a CAM solution, but I don't know anything more than that. >The biggest shortcomings of the 20K that I can see without actually doing a design in >the part are: >1. The LE's cannot become small RAM elements. This is significant in signal >processing in a few areas. Yep, Xilinx always seems to win out with this feature. >So, in summary, it comes down to what is needed by your application. For general DSP, >the lack of the CLB RAM capability and the multi-levels needed for arithmetic >functions are significant demerits in most of the cases I deal with. Most of my designs have not been DSP intensive and so I've had the luxury of being able to use either. However, the CAM support may swing it Altera's way for me. The main problem is softare support. Xilinx new tools look good. Maxplus2 has reached the end of the road for the new large FPGA designs and so I await to see how good Quartus will be. One other area is price. Most of the die I have seen, based on a like for like basis, has generally shown Altera to be 2-4 times smaller in area. Altera also have inbuilt redundancy in their row (or maybe column) structures, I'm not sure about Xilinx. Given these factors, I would expect Altera to win out in wafer die yields and hence price (my opinion). Just my 2 pence worth! -- Regards, Brent Hayhoe. Nortel Networks plc, Tel: +44 (0)1279-402937 Harlow Laboratories, London Road, Fax: +44 (0)1279-403930 Harlow, Essex, CM17 9NA, U.K. Email: hayhoe@nortelnetworks.comArticle: 16643
Hej, There's an even better approach if you have Acrobat Exchange. But you have to install a plugin. Goto http://www.adobe.com/supportservice/custsupport/LIBRARY/acewin.htm and download the "Export PS 1.2d Plug-in". Now you can crop the PDF sheet you are interested in exporting and then eport to EPS. Then you have a EPS (vector graphics) file than you can import in word / Jonas Thor On Mon, 31 May 1999 20:08:40 -0400, Ray Andraka <randraka@ids.net> wrote: >Apparently when you copy an acrobat image to the clipboard, it converts the >image at the current zoom into a bit map. By zooming in, you get better >quality images. No, I didn't find this written anywhere. I discovered it >by accident when I was trying to do pretty much the same thing you are.Article: 16645
Somebody's testing their spam software. Pay no attention. The only thing
worth doing is emailing abuse@{whoever}, and then only if you can be
bothered (and know how) to read the headers properly.
In article <3751F677.D555C67B@flnet.com>, bayowolf@flnet.com said...
> lpjwll@sssdfdf.org wrote:
>
> > bmbhsvhumsddkmqqxcvdhwukloqovzpbrzlghssgzqdwxryxgndqrkyqexwssergvclqtfsfhlsyrjbfwkhrypiqwopsilofzl
>
> How about "You're not going to understand this!" ?
> That makes a whole lotta sense. Exactly what was this person trying to communicate? That his cat can
> reach the keyboard? Mine can too!! (and types better)
>
> -Alan
>
> --
> For a free weekly homeschooling newsletter, devotions, lesson plans, and more, visit
> http://www.THSresources.com. A member of the A+ Thematic Units Webring .
>
> Chat with me on ICQ #6913463 or AOL IM username flowoyab (bayowolf backwards)
>
> Remember: any excuse that starts with but(t) already has a crack in it. (Alan Hunter)
>
>
>
--
Steve Rencontre - Design Consultant
http://www.rsn-tech.demon.co.uk/
Article: 16646I've not used VHDL with Actel chips, only schematics, and not all that recently either, so ignore me if I'm talking nonsense, but can't you /instantiate/ a DFF rather than infer one? In article <7itipu$50k$1@nnrp1.deja.com>, micheal_thompson@my-deja.com said... > In article <37502151.CFCEA000@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > > > > But at this point we seem to be splitting hairs. The bottom line is, > he > > code produces something he doesn't like while it correctly matches the > > simulation (at a logic level). > > > > So change the code. > > > >> > Precisely. So, any suggestions on the code that will will give me a > desirable implementation, namely a DFF whose (asynch) set and reset > inputs are connected to my set and clear signals, whilst its clock and > D inputs are effectively unused? > regds > Mike > > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > -- Steve Rencontre - Design Consultant http://www.rsn-tech.demon.co.uk/Article: 16647
In article <3752C959.B6A78501@yahoo.com>, spamgoeshere4@yahoo.com said... > I am working on documentaion for my last design and I would like to > include schematic pages in the document. I could just print them out and > add the pages. But I was tring to add them electronically so that > everything is in one file. > > I am writing this in Word 97 and using Xilinx Foundation 1.5i for the > schematic capture. I was able to print to a PDF file, but Word won't > accept that as a picture. I also tried printing Postscript to a file, > but Word won't show that on the screen. It will only print it to a > Postscript printer. > > Does anyone have an idea of how to do this? Are there any programs that > will let me print the schematic to a picture file without a big loss of > resolution? I found that I could cut and paste from Acrobat to Word. But > the intermediate file format was a bit mapped file of some type and most > of the text blurred a great deal. Have you tried copying your schematic to the clipboard in Foundation and then pasting into Word? I was pleasantly surprised to find that this technique worked with Rational Rose diagrams, even though I could find no way of generating a useful graphic file format. -- Steve Rencontre - Design Consultant http://www.rsn-tech.demon.co.uk/Article: 16648
In article <7hmvgk$vtf$1@nnrp1.deja.com>,
Swapnajit Mittra <mittra@my-dejanews.com> wrote:
> =-=-=-=-=-= 100% pure Verilog PLI - go, get it ! =-=-=-=-=-=
> Principles of Verilog PLI -By- Swapnajit Mittra
> Kluwer Academic Publishers. ISBN: 0-7923-8477-6
> http://www.angelfire.com/ca/verilog/
>
> --== Sent via Deja.com http://www.deja.com/ ==--
> ---Share what you know. Learn what you don't.---
>
Swapnajit,
I finally got the book above. Congratulations.
The section about inter-process communications was very helpful.
Regarding this issue, I need an advice on the following :
The 'accept' call of the server is blocking by default. It will not
return until a connection is available. I know that it is possible to
define the socket as non-blocking. Can you advise me how? Actually I
want to achieve the effect of the server 'visiting' the socket and if
there is no connection of the client to let it continue.
Thank you,
Andi Carmon
andi@orckit.com
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
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