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Your "for" loop requires a (external) counter to track the iterations,
no? It's the way I'd do it.
Jarek Patrzalek wrote:
> I am a beginner in VHDL coding and I would like to place
> a fixed delay in my (synchronous) finite state machine,
> but I do not want to use "external" counter or to implement
> a certain number of "idle" states in FSM.
> Is it possible (and reasonable) to use a kind of iteration
> scheme ("for" loop) within FSM state(s)?
>
> Jarek
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 16651
Hi,all:
I need convert a ALTERA design(MAX+PLUSII) into a XILINX design (Foundation
F1.3). I try export a Edif 200 file from MAX+PLUS and import Netlist into
Schematic Editor of Foundation. I complet the design with the new component
( IBUF,OBUF,pads) and save. When i try export the netlist in a XNF file, i
have a error message ("Missing AND1 model or library error") then i export
in a VHD file and have ("Canot read pin descriptors for AND1") error.
I want to generate a VHDL file(XILINX Foundation compatibility) from a EDIF
or other ALTERA file. How i can to do?
Article: 16652
Hi, all:
I need convert a ALTERA design(MAX+PLUSII) into a XILINX design (Foundation
F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist into
Schematic Editor of Foundation. I complet the design with the new component
(IBUF, OBUF, pads) and save. When i try export the netlist in a XNF file,
ihave a error message ("Missing AND1 model or library error") then i export
in a VHD file and have ("Cannot read pin descriptors for AND1") error.
I want to generate a VHDL file (XILINX Foundation compatible) from a EDIF
,or other, ALTERA file. How i can to do?
Article: 16653Alvin E. Toda wrote: > > On Mon, 31 May 1999 micheal_thompson@my-deja.com wrote: > > > Precisely. So, any suggestions on the code that will will give me a > > desirable implementation, namely a DFF whose (asynch) set and reset > > inputs are connected to my set and clear signals, whilst its clock and > > D inputs are effectively unused? > > regds > > Mike > <snip> I am suprised that no one has offered this solution to your problem. Rather than trying to synthesize an RS latch, why not instantiate one? Look in the library docs for your target part and find the logic resource you want (in this case DFF with async Rese/Clear). Then wire it up the way you want. The only problems with this are (1) you lose portability, and (2) you may not have a simulation model for the device. These days (2) will probably not be a problem as most vendors ship timing models for their device primitives and you may not care about (1). -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 16654
There's a fairly comprehensive list of books on The Programmable Logic Jump Station at http://www.optimagic.com/books.html -- many arranged by subject matter. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- username@dso.org.sg wrote in message <37522363.124D@dso.org.sg>... >Hello, > >Does anyone out there have any good recommendations on books about >FPGA which contains a good explanation of how FPGA works and >its physical construction, LCA/LCB design analysis, programming >circuit and logic etc.? > >Not the usual data sheets though. >Thanks in advance. > >email: csoolan@dso.org.sgArticle: 16655
Jonas Thor wrote: > > Hej, > > There's an even better approach if you have Acrobat Exchange. But you > have to install a plugin. Goto > > http://www.adobe.com/supportservice/custsupport/LIBRARY/acewin.htm > > and download the "Export PS 1.2d Plug-in". Now you can crop the PDF > sheet you are interested in exporting and then eport to EPS. Then you > have a EPS (vector graphics) file than you can import in word > > / Jonas Thor > > On Mon, 31 May 1999 20:08:40 -0400, Ray Andraka <randraka@ids.net> > wrote: > > >Apparently when you copy an acrobat image to the clipboard, it converts the > >image at the current zoom into a bit map. By zooming in, you get better > >quality images. No, I didn't find this written anywhere. I discovered it > >by accident when I was trying to do pretty much the same thing you are. I was able to print directly to an EPS file from the original application. The PDF file was an attempted intermediate format. The problem with EPS is that it does not show up in Word. It also won't print to anything other than a PostScript printer. Apparently Word just acts as a passthrough for EPS files. But then once I read up on them, that is what EPS is supposed to do. Is there something I am missing about EPS files? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16656
If you need controlled impedance software for single/differential strip/microstrip line you can purchase it from me(under win95/NT) very easy to use.. If you intersted email to meArticle: 16657
Ray Andraka wrote: > > Just to clarify, change the zoom to 800% (the max) after selecting the > graphic. Most likely, it will be bigger than your screen, but that is OK. > Everything enclosed in the selection box, even if it is off the screen gets > copied. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka Thanks Ray, This helped a lot. I can't go much above 300% when I copy, else it gives me an out of memory error. I have shut down everything I have running at the time and I have 64 MB on this machine. But this gives an acceptable quality. Too bad there is not a format that will let me preserve the lines and symbols so that the quality is maintained regardless of picture size. At least there is not one I can output. Can the autocad DXF format handle this? How can I print to a DXF file from Foundation? Has anyone out there done this before? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16658
1 June 1999
What's new in the Qualis Library
--------------------------------
At Qualis, we believe in sharing knowledge with the design community.
We seek out worthwhile whitepapers, productivity scripts, and other
useful information and slip them into the Qualis Library for your
perusal. Recently, we've added several new items to the Library on
topics related to:
1. Behavioral Synthesis (2 items)
2. Design Reuse (2 items)
3. ASIC/FPGA design productivity scripts (1 item)
4. Verilog design info resource (1 item)
Check them out in the Qualis Library by clicking on the hotlinks shown
below. If you don't already have one, you'll need a Library card to
access the Library. You can get a library card instantly -- you'll
find more information by clicking on the hotlinks below.
1. Case studies in Behavioral Synthesis.
We've added two informative case studies on Behavioral Synthesis that
offer unique and useful insight into appropriate (and inappropriate)
applications for Behavioral Synthesis. Focusing on Synopsys'
ever-evolving Behavioral Compiler, you'll gain a great deal of wisdom
from the experiences of the designers on these projects at Intel and
Tandem Computers.
"Pushing the Limits with Behavioral Compiler"
by Scott Smith (Tandem Computers) and David Black (Qualis Design)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=dd008
"Designing a big-number Arithmetic Processor using Behavioral Synthesis"
by Tim Wilson (Intel Corporation)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=ds003
2. Design reuse.
Design reuse is a hot topic, and rightly so. Companies are shifting
their design cultures toward reuse and IP creation, a non-trivial
task. Learn more about how Siemens AG has tackled the problem in
this informative and timely article on their "Core Supply Process",
the cornerstone of the Siemens reuse strategy.
"Constructing a Solid Framework for Design Reuse Companywide"
by Ulf Schlictmann, Udo Grehl, Bernd Wurth (Siemens)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tt008
Many of the third-party IP companies that popped up in 1998 seem to be
having a hard time making money. Not ARM. As one of the few success
stories in third-party IP, ARM knows the secret recipe for success.
Read this article and you'll realize that attention to a few basic
principles, plus a lot of hard work, can yield great results for nearly
any third-party IP company. And that's good news for the design
community.
"How to Make Money in IP"
by Mike Muller (ARM)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tt007
3. Productivity scripts.
We have included a detailed paper on a helpful project automation script
called 'run_proj'. run_proj helps manage ASIC/FPGA synthesis and
verification tasks, including the top-evel harness and pin list,
design configuration, simulator selection/invocation, regression testing,
and links to revision control. The perl script improves team
productivity and reduces project risk by automating many of the
support tasks commonly found on today's design projects.
"run_proj: An ASIC/FPGA Project Productivity Script"
by Keith Greeney (Focus Enhancements) and Fred Meyer (Qualis Design)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=ds003
4. Information resource.
If you're a Verilog designer and you don't already know about the now
famous "Celia's Verilog & EDA Info Site", you'll want to check this out.
Celia is a well-known Verilog expert (that's why she's at Qualis:),
and her independent site proves useful as a handy Verilog and design
resource. Created years ago, she has kept it up-to-date with useful
information she has collected over time.
"Celia's Verilog & EDA Info Site"
by Celia Clause (Qualis Design)
URL: http://www.qualis.com/cgi-bin/qualis/libObject.pl?object=tr015
As you are probably aware, we have created the Qualis Library as a
opinionated, selective repository for high-quality information about
complex ASIC, SoC and system design issues. Sharing knowledge is an
integral part of the Qualis culture, and the Qualis Library is our
way of giving back to the engineering community. Check it out
and send us your feedback.
We'll keep you posted as new content is added to the Library.
Michael
(You can easily reach us by e-mail or telephone. Send your e-mail to
mailto:hot@qualis.com, or call us at +1.503.670.7200)
Article: 16660Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog & EDA Page : http://www.angelfire.com/in/rajesh52/verilog.html ) Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16661
>I was able to print directly to an EPS file from the original >application. The PDF file was an attempted intermediate format. The >problem with EPS is that it does not show up in Word. It also won't >print to anything other than a PostScript printer. Apparently Word just >acts as a passthrough for EPS files. But then once I read up on them, >that is what EPS is supposed to do. > >Is there something I am missing about EPS files? No, you are rigth. I did not think about this... When using Word and EPS files you need a postscript printer. When you create the EPS you can select a bitmap preiview which will be visible in Word, but still you need a postscript printer. To print on a non-postscript printer you could convert to PDF and then print from Acrobat... but this seems tedious. / JonasArticle: 16662
On Sat, 29 May 1999 13:31:08 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: >The solution to that is to also use a sync reset. The async reset should >cause a FF to assert a sync reset which can be removed either on the >next clock edge or by software or other external stimulus. Each clock >domain needs a separate reset FF working off of that clock. Then the >circuit will come out of reset cleanly. > >If your reset FF is coming out of reset on the next clock edge, you may >want to also apply the metastability issues (much of which I have >learned here) to this FF and use two in cascade to reduce the likelyhood >of this causing a problem. this is also what i do, and it raises an obvious question - what's the point of having a user-accessible GSR net if it has undefined timing? IIRC, virtex has only 3 GSR specs, and there are only maybe 4 or 5 in the 4Ks, and *none* of these give the important number - GSR setup to clock at a CLB. this makes it impossible to come out of reset cleanly, and you have to use general purpose routing for a sync reset, which could have a large fanout. i checked the delay from a reset pin, through GSR, to a CLB recently, and the simulator reported, IIRC, 17ns on an XCV300-4. this also had the effect of making my functional sim different from my timing sim, since the delay was longer than a clock period. evanArticle: 16663
On Mon, 31 May 1999 08:55:26 GMT, micheal_thompson@my-deja.com wrote:
>Precisely. So, any suggestions on the code that will will give me a
>desirable implementation, namely a DFF whose (asynch) set and reset
>inputs are connected to my set and clear signals, whilst its clock and
>D inputs are effectively unused?
library IEEE;
use IEEE.std_logic_1164.all;
entity MY_RS is
port (S,R : in std_logic;
Q : out std_logic);
end entity MY_RS;
architecture STRUCT of MY_RS is
-- this decln will be in a vendor package, so isn't
-- necessary here
component VENDOR_DFF
port (D, CE, C, S, R : in std_logic;
Q : out std_logic);
end component;
begin
U1: VENDOR_DFF port map (
D => '1', CE => '1', C => '1',
S => S, R => R, Q => Q);
end architecture STRUCT;
if you haven't got '93, you won't be able to specify '1' as an actual-
declare a signal, drive it with '1' or '0', and connect it instead.
evan
Article: 16664If you are a Synplicity customer and are interesting in attending this years Users Group meeting, please visit: http://www.synplicity.com/support/usr_group/usersmain.html for more information. Registration ends this week. Thank you.Article: 16665
Designing with Reuse in Mind
A Special 3-day Workshop
June 16-17-18 1999
San Jose, California
Qualis Design is hosting a special workshop on design reuse this
June 16-17-18 in San Jose, California. This intense workshop will be led by
Janick Bergeron, Vice President of Technical Wisdom at Qualis. Janick
will work closely with the attendees of this stimulating workshop,
covering all of the critical areas of design reuse. As a recognized expert
in reuse methodologies and large system design, Janick deeply understands
the reuse issues designers face. In this interactive workshop, you will
learn how to set up a reuse-friendly design environment, how to architect,
implement, and verify a reusable component and SoC design, and how to
package it for future reuse. Join other top engineers for this unique
opportunity to network and discuss today's reuse challenges and solutions.
Find detailed information about this seminar on our website at:
http://www.qualis.com/cgi-bin/qualis/session.pl?event=reuse_990616.html
or call Michael McDowell at 888-214-4224 (or +1-503-968-8550) to secure
your seat.
Michael
Article: 16666Tim Tyler wrote: > > A number of researchers in the area use FPGAs which are designed to try to > avoid contention issues in all but the I/O stage - you can send a > random bitstream to them without much fear that contention issues will > arise. The Xilinx 6200 series is one family which exhibits this type of > safety. I wonder how many projects will be affected by Xilinx decision to discontinue the part. > Essentially the cellular automata is implemented in the programmable > logic. Low-level reprogrammability may not even be strictly necessary if > the design of the CA itself is fixed - ordinary VLSI slilcon could > be employed, in principle. Aha! This explains a lot! Presumably the CA design takes into account the target hardware. The final interconnects produced by this approach are probably not as "random" as I thought. I saw final results produced by an evolved low frequency / high frequency square wave discriminator (sorry, I don't remember the reference), and the logic looked like spaghetti. > [...] > These links were mainly taken from http://www.alife.co.uk/links/hardware/ Great links! Here are two that I had previously come across which I didn't find referenced (directly) in those pages: NASA Goddard's work: http://rk.gsfc.nasa.gov/richcontent/Adaptive%20Computing/AdaptiveComputingMainPage.htm An Introduction to Evolvable Hardware By Marco Tomassini and Moshe Sipper (different from your links) http://www.evonet.polytechnique.fr/Coordinator/evonews/news3/ehard.htm I had come across Hugo de Garis' work on the the Cam Brain, applied to the Robot Kitten, and just recently heard a press release for Sony's Robot Dog ( http://www.virtualpet.com/vp/farm/sony/sony.htm ). The artwork for the two look remarkably similar -- there's got to be a connection. Clearly, this work is not just purely theoretical at this time. Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16667
I was thinking about putting up a page devoted to new engineers entering the FPGA market. It was somewhat difficult for me to get started and I'd like to ease the pain for anyone just getting into this technology. My question is this...Other than the differences between CPLD/FPGA, the programming, vendors, languages (VHDL or simple ABEL), what other things would be appropriate for this type of page? Your input could benefit future designers. ---Article: 16668
Much more important to the newbie is learning design styles and techniques for efficiently using the FPGA resource. This necessarily includes discussion on the architecture, typical logic (whatever that is) and how it maps into the architecture, design styles for HDLs to make sure you get what you want etc. Unfortunately, there is a lot of information that is required before one becomes a good FPGA designer, and some of it only comes with experience. A page with all the information would certainly be a useful resource, but as I found out first hand, it is also a very ambitious undertaking. Best of luck. news.pcnet.com wrote: > I was thinking about putting up a page devoted to new engineers entering the > FPGA market. > > It was somewhat difficult for me to get started and I'd like to ease the > pain for anyone just getting into this technology. > > My question is this...Other than the differences between CPLD/FPGA, the > programming, vendors, languages (VHDL or simple ABEL), what other things > would be appropriate for this type of page? > > Your input could benefit future designers. > > --- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16669
Probably some insider tips of trade ...wrt. mapping circuits on to FPGAs and any peculiarities faced. Also the basic flow can be highlighted with emphasis on optimizations targetted to specific FPGAs -- Pranav In article <DBZ43.5$9i6.6192@news.pcnet.com>, "news.pcnet.com" <desrosi@pcnet.com> wrote: > I was thinking about putting up a page devoted to new engineers entering the > FPGA market. > > It was somewhat difficult for me to get started and I'd like to ease the > pain for anyone just getting into this technology. > > My question is this...Other than the differences between CPLD/FPGA, the > programming, vendors, languages (VHDL or simple ABEL), what other things > would be appropriate for this type of page? > > Your input could benefit future designers. > > --- > > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16670
Steve Rencontre wrote: > > In article <3752C959.B6A78501@yahoo.com>, spamgoeshere4@yahoo.com said... > > I am working on documentaion for my last design and I would like to > > include schematic pages in the document. I could just print them out and > > add the pages. But I was tring to add them electronically so that > > everything is in one file. > > > > I am writing this in Word 97 and using Xilinx Foundation 1.5i for the > > schematic capture. I was able to print to a PDF file, but Word won't > > accept that as a picture. I also tried printing Postscript to a file, > > but Word won't show that on the screen. It will only print it to a > > Postscript printer. > > > > Does anyone have an idea of how to do this? Are there any programs that > > will let me print the schematic to a picture file without a big loss of > > resolution? I found that I could cut and paste from Acrobat to Word. But > > the intermediate file format was a bit mapped file of some type and most > > of the text blurred a great deal. > > Have you tried copying your schematic to the clipboard in Foundation and > then pasting into Word? I was pleasantly surprised to find that this > technique worked with Rational Rose diagrams, even though I could find no > way of generating a useful graphic file format. > > -- > Steve Rencontre - Design Consultant > http://www.rsn-tech.demon.co.uk/ Good idea, but it didn't work. It is not a big deal. I have finished the docs and will simply add the schematics as an appendix. But it would have been nice to have been able to put the pictures into the doc file so that it was self contained rather than to have to print out the schematics and add them as paper copies. Does anyone know if Viewlogic is better at this? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16671
ems@riverside-machines.com.NOSPAM wrote: > > On Sat, 29 May 1999 13:31:08 -0400, Rickman <spamgoeshere4@yahoo.com> > wrote: > > >The solution to that is to also use a sync reset. The async reset should > >cause a FF to assert a sync reset which can be removed either on the > >next clock edge or by software or other external stimulus. Each clock > >domain needs a separate reset FF working off of that clock. Then the > >circuit will come out of reset cleanly. > > > >If your reset FF is coming out of reset on the next clock edge, you may > >want to also apply the metastability issues (much of which I have > >learned here) to this FF and use two in cascade to reduce the likelyhood > >of this causing a problem. > > this is also what i do, and it raises an obvious question - what's the > point of having a user-accessible GSR net if it has undefined timing? > IIRC, virtex has only 3 GSR specs, and there are only maybe 4 or 5 in > the 4Ks, and *none* of these give the important number - GSR setup to > clock at a CLB. this makes it impossible to come out of reset cleanly, > and you have to use general purpose routing for a sync reset, which > could have a large fanout. > > i checked the delay from a reset pin, through GSR, to a CLB recently, > and the simulator reported, IIRC, 17ns on an XCV300-4. this also had > the effect of making my functional sim different from my timing sim, > since the delay was longer than a clock period. > > evan You are probably not looking for advice, but it is easy to ignore if so. A synchronous reset with a high fanout can be routed through multiple pipeline registers in a manner analogous to a clock tree. As long as the total number of FFs from GSR to any device being reset is the same, you can fan out through many levels. I like the idea of the synchronous reset since many of my circuits have them for other reasons anyway, processor control, system reset... It is a simple thing to add the GSR as an input to the sources for the sync reset. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16672
Rick, I've done it with Viewlogic Workview Office 7.5 + Ghosscript 5.2 + Paint Shop Pro 3 + Word 6 In Viewlogic : export schematic individually in Poscript format (.PS) then go to ghoscript In Ghostcript : load the .PS file, zoom to the maximum, copy entire image to the clipboard the go to Paint Shop Pto In Paint Shop Pro : load the image from the clipboard and save it to a Word 6 compatible format (.GIF or .TIF) In Word 6 : insert the image in full page format the print the document When printing the document to Poscript Printer the resolution of images is pretty good I think Foundation 1.5 is not able to export schematics to Poscript format Thierry GARREL +----------------------------------------------+ | MATRA Systèmes & Information (MS&I) | | 6 avenue des tropiques - BP 80 | | 91943 COURTABOEUF CEDEX / FRANCE | | Tel : (33) 1 69 86 85 00 | | Fax : (33) 1 68 07 03 70 | | Mail : ceo@matra-des.mgn.fr | +----------------------------------------------+Article: 16673
I found rather simple trick for such purpose: 1) Install Microsoft's FAX program for the WinNT 4.0 "NTWFax_i386" (which is a free download from www.microsoft.com , intended for sending FAX-messages via FAX-modem). 2) Configure FAX printer for writing to a file, not to fax-modem! 3) Now, you can print from XILINX Foundation to FAX printer, and the result is immediately stored as a TIF file - FAX printer driver prompts for the file name. Alex Sherstuk ===== Rickman wrote in message <3752C959.B6A78501@yahoo.com>... >I am working on documentaion for my last design and I would like to >include schematic pages in the document. > ... >Does anyone have an idea of how to do this? Are there any programs that >will let me print the schematic to a picture file without a big loss of >resolution? > ... >Rick Collins >rick.collins@XYarius.com >remove the XY to email me. >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design >Arius >4 King Ave >Frederick, MD 21701-3110 >301-682-7772 Voice >301-682-7666 FAX > >Internet URL http://www.arius.comArticle: 16674
Thierry Garrel wrote: > > Rick, > > I've done it with Viewlogic Workview Office 7.5 + Ghosscript 5.2 + Paint > Shop Pro 3 + Word 6 > In Viewlogic : export schematic individually in Poscript format (.PS) > then go to ghoscript > In Ghostcript : load the .PS file, zoom to the maximum, copy entire > image to the clipboard the > go to Paint Shop Pto > In Paint Shop Pro : load the image from the clipboard and save it to a > Word 6 compatible format > (.GIF or .TIF) > In Word 6 : insert the image in full page format the print the document > > When printing the document to Poscript Printer the resolution of images > is pretty good > > I think Foundation 1.5 is not able to export schematics to Poscript > format Wow, that's a lot of work. Actually if you are printing to a Postscript printer, you can print from any program an EPS file which is encapsulated Postscript. This can be brought directly into Word. But it can only be printed to a Postscript printer, which I don't have. I guess I could go through Ghostscript, but I was looking for something a little easier. It's not that important. I got the job done the low tech way. Thanks. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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