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For those interested, more info can be found in the Xilinx press release at http://www.xilinx.com/prs_rls/philacq.htm Tom BurgessArticle: 16951
Thomas A. Coonan <tcoonan@mindspring.com> wrote in message news:376a5a2c.694032145@news.mindspring.com... [SNIP] > That's it. I hope someone out there has had a similar issue and can > help me! (I'll be at DAC next week if anyone would actually like to > discuss this sort of thing..) [SNIP] Oh, and a follow up to my last post. We'll be at the DAC in New Orleans all day Monday and Tuesday morning next week (in the Lucent Booth), so if you would like to look at the demo for our PIC core just stop by. We'll have a PIC uC running on an FPGA, and I can show you how that works, too. There's a little display on it and stuff, and you can program it right there. I'd be glad to kibbitz with you about PIC microcontroller architectures if you want too. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 16952
Rickman wrote in message <376A87F0.577C41CD@yahoo.com>... >... You could even use different >addresses on the read and write by using a dual port ram. Or if you >multiplex the address, you can still use different addresses on read and >write by clocking the read data into an output register on the falling >edge of the clock and changing the address with the clock as well. You >will need to be very careful about timing of the multiplexer in this >case. If it changes too quickly, you will not meet the address >setup/hold times on the ram. Yes! For my 1+eps instruction/clock XC4000 RISC processor register files, I choose the second technique above, because it saves significant area. Each clock, write a result back into the register file ram on the clock rising edge and read an operand and capture it into the ram's CLB's FFs on the clock falling edge. A multiplexor selected by clock provides the write address (destination register no.) while clock is low (e.g. ahead of the clock rising edge) and the read address (source register no.) while clock is high. (Another timing issue: assume you are writing a new result to register 1 and in the next half clock are reading/latching register 1 as a source operand. You must provide enough time for the new value to be written *and* read out before that clock falling edge. Presumably this is no longer than tWOS + tICK, but intra-CLB should be better.) Keep two copies of the register file to enable two arbitrary read ports. Explicitly floorplan the register file and its register file address mux. The latter can be placed directly above the column of rams to drive the vertical longlines on that column. The Xilinx dual port distributed rams are nice but they are half as dense as the single port ones. (Also note, one dual port ram bank provides one write and two read ports IF your instruction set is entirely of the form dest = dest op src and provided you don't pipeline your datapath.) Example RISC CPU register file / datapath area costs using single and dual port ram: Word size / # Regs / Target / Datapath area (CLBs) / 2R1W regfile area (CLBs) / ram type / percent area --- 16-bit / 16 regs / XC4005XL / 8x8 / 8x2 / single port / 25% 16-bit / 16 regs / XC4005XL / 8x10 / 8x4 / dual port / 40% 32-bit / 16 regs / XC4010XL / 16x8 / 16x2 / single port / 25% 32-bit / 16 regs / XC4010XL / 16x10 / 16x4 / dual port / 40% 32-bit / 32 regs / XC4010XL / 16x10 / 16x4 / single port / 40% (*) 32-bit / 32 regs / XC4010XL / 16x14 / 16x8 / dual port / 57% (**) (*) see e.g. http://www3.sympatico.ca/jsgray/sld021.htm (**) or worse, since we must fashion each 32x1 dual port ram from two 16x1 ones, requiring a 2-1 mux per bit, and since M1 tools do not allow two FMAPs and an HMAP to be RLOC'd to the same CLB. Now then, register file design for an FPGA VLIW machine, *that* is a fun topic. Jan GrayArticle: 16953
That's right, alot of tools don't handle the "inverted sense" label. You can go back and edit the symbol to change the pin sense (which puts a bubble on the symbol pin) without affecting the netlist. Austin Franklin wrote: > In fact, I'd suggest NOT using the overbar convention. Some tools may not > process the name correctly. The overbar has to be translated into 'some' > other character, per se, because one can not have an overbar in a text file > ;-) They used to translate it to a tilde. After YEARS of fighting with > tool vendors to all come up with ONE convention for active low signals, and > getting no where, I got smart and came up with a convention that doesn't > use the overbar. > > It can be any textual convention you want, but I personally use "SIGNAL_L", > and it seems to work fine thru all my tools. > > Austin Franklin > austin@darkroom.com > > Jim Kipps <jkipps@viewlogic.com> wrote in article > <376A421A.737B7038@viewlogic.com>... > > Ingo- > > > > Sorry, but vhdl2sym.exe does not support the creation of bars over pin > names > > in the symbols it creates. You have to edit the symbol after generation. > > > > Regards, > > -Jim > > > > Ingo Purnhagen wrote: > > > > > Sorry, forgot my real name; damned Outlock ;-) !!! > > > > > > Hi newsgroup, > > > I have a simple (?) problem using VHDL and Viewlogic. After declaration > of > > > an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works > fine, > > > but I want to have an active low signal (signalname with overline) in > my > > > schematic. > > > I have no idea how to realize it in VHDL . Any suggestions? > > > > > > -- > > > Ingo Purnhagen > > > OHB-System GmbH > > > Universitaetsallee 27-29 > > > D-28359 Bremen > > > Telefon: 0421-2020-702 > > > Telefax: 0421-2020-610 > > > mailto:Purnhagen@ohb-system.de > > > http://www.ohb-system.de > > > > -- > > -------------------------------------------------------- > > James R. Kipps FPGA Marketing Manager > > jkipps@viewlogic.com Phone: (508) 303-5246 > > -------------------------------------------------------- > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16954
Pete Zaitcev wrote: > >: Does PCI always need lots of interfacing, or, since I'm doing > >: simple, low-speed I/O is there a sort of 'PCI-lite' interface > >: specification for that sort of thing? > > Perhaps it's a dumb idea but what about a small FPGA (Xylinx Spartan) > with PCI Slave code? Helpful folks in comp.arch.fpga suggested me > several possible ways to obtain nearly free cores. Please check > with the Deajanews. > > When I asked them my application was different - I needed some space > in the FPGA, so that ISA bus is completely enclosed inside the chip, > and only demultiplexed signals go in and out. Still, if you have board > space I think if may be feasible to have a homemade PCI-to-ISA bridge, > slave only. > > --Pete Check out our page for the HOT2. It is $695 and you'll have to buy $100 programming package from Xilinx. http://www.vcc.com/Hotii.html picture http://www.vcc.com/photohtwk4.html This board of course is a reconfigurable computer with 128K of configuration cache (will store 3 chips in cache) Comes with a nice little API to talk to the board and reconfigure it at run time. Thanks -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16955
On Fri, 18 Jun 1999 22:58:49 GMT, "Jan Gray" <jsgray@acm.org.nospam> wrote: >(**) or worse, since we must fashion each 32x1 dual port ram from two 16x1 >ones, requiring a 2-1 mux per bit, and since M1 tools do not allow two >FMAPs and an HMAP to be RLOC'd to the same CLB. I'm not quite sure what you mean by this (a 16x1 dual-port RAM requires both the F and G function generators, so you couldn't pack 2 in a 4K CLB), but M1 has no problem with 2 FMAPs and an HMAP in the same CLB - for a VHDL example, see: http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm You'll have to manually navigate to rloc4.vhd, since my ISP keeps messing around with 'upgrades' and screwing up FTP accesses. Can anyone recommend an ISP who allows FTP accesses based solely on unix file permissions (preferably in the UK, or anywhere else failing that?) Thanks EvanArticle: 16956
On Fri, 18 Jun 1999 18:04:44 -0700, Steven Casselman <sc@vcc.com> wrote: > > >Pete Zaitcev wrote: > >> >: Does PCI always need lots of interfacing, or, since I'm doing >> >: simple, low-speed I/O is there a sort of 'PCI-lite' interface >> >: specification for that sort of thing? >> >> Perhaps it's a dumb idea but what about a small FPGA (Xylinx Spartan) >> with PCI Slave code? Helpful folks in comp.arch.fpga suggested me >> several possible ways to obtain nearly free cores. Please check >> with the Deajanews. >> >Check out our page for the HOT2. It is $695 and >you'll have to buy $100 programming package from >Xilinx. >http://www.vcc.com/Hotii.html >picture >http://www.vcc.com/photohtwk4.html >This board of course is a reconfigurable computer with >128K of configuration cache (will store 3 chips in cache) >Comes with a nice little API to talk to the board and reconfigure >it at run time. > >Thanks As a matter of interest, when running this Spartan PCI interface as a PCI slave, i.e. no DMA capability (in a normal PC), what sort of I?I bandwidth do you get? In other words, do you need the full bus-mastering DMA core to get 100-120MB/second? - BrianArticle: 16957
What is differences the Synopsys FPGA Express 3.2 and FPGA Compiler 3.2 ? Which is the best to Xilinx FPGA VHDL synthesize and optimize? Thank you: Tibor Szolnoki. fpga@dartsgame.comArticle: 16958
What is differences the Synopsys FPGA Express 3.2 and FPGA Compiler 3.2 ? Which is the best to Xilinx FPGA VHDL synthesize and optimize? Thank you: Tibor Szolnoki. fpga@dartsgame.comArticle: 16959
I was just looking at the market statistics page on optimagic.com and I
noticed that there was no data available after 1997. Does anyone know where
I can aquire data regarding the market share of Programmable Logic vendors?
Thanks in advance,
EKC
Article: 16960>Thomas A. Coonan <tcoonan@mindspring.com> wrote in message >news:376a5a2c.694032145@news.mindspring.com... >[SNIP] >> That's it. I hope someone out there has had a similar issue and can >> help me! (I'll be at DAC next week if anyone would actually like to >> discuss this sort of thing..) >[SNIP] > >Oh, and a follow up to my last post. We'll be at the DAC in New Orleans all day >Monday and Tuesday morning next week (in the Lucent Booth), so if you would like >to look at the demo for our PIC core just stop by. We'll have a PIC uC running >on an FPGA, and I can show you how that works, too. There's a little display on >it and stuff, and you can program it right there. I'd be glad to kibbitz with >you about PIC microcontroller architectures if you want too. OK. See you then! > >-- >Wade D. Peterson >Silicore Corporation >3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 >TEL: (612) 722-3815, FAX: (612) 722-5841 >URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.edu > >Article: 16961
Unfortunately Xilinx Tech Support seem to be completely overwhelmed at the moment, at least here in the UK. I wonder if anyone can help me with 2 problems with Foundation 1.5i which have brought my work to a halt: First, I can't seem to LOC a pin on a single wire net in a schematic macro sheet with an entry in the .UCF file. This is strange, because I can lock bus pins in the same macro with no trouble using the same syntax. Both the bus and the single wire are named between the PAD and the BUFF. (The PADs and the BUFs are all in the macro - I assume this is OK?) No error messages are issued, it just doesn't put the signal where I want it. If I deliberately make a syntax or path error in the LOC statement then I get error messages, so I infer it is happy with what I am asking it to do. I can LOC single wires and buses in a top level OK. Second problem. I have an ABEL macro under a schematic top sheet. If the ABEL contains only combinatorial equations then everything works fine. If it contains a simple state machine, then I get "unconnected inputs" and "output driven by 0" errors from the fitter. The ABEL seems to compile OK. None of the log files seem helpful. I get "dangling port" warnings, but I understand this is normal and can be ignored. I get the same warnings in the simple combinatorial case. I note the .edn file refers to CELLxxx items when I use the state machine. Maybe it is not finding them? Where do they come from? Hope this description is enough to ring a bell with someone! -- Alan Hall, Ipswich, UKArticle: 16962
Utku Ozcan schrieb: > > > > I don't use the SPO's of some DP RAM's on XC40150XV. > > > NGDBUILD and XNF2NGD give warnings. Do these warnings > > > imply a possibly bad routing architecture? Shall I > > > use the commands which ignore these pins? I have > > > used following command but the warnings didn't go away: > > > > > > NET "dp_ram_spo<*>" TIG=TS01; > > > > > > Shall this TS01 be defined for write clock of the Dual > > > Port RAM? Shall I use such a command to improve the > > > performance? > > > > > > Utku > > The warnings can be safely ignored, but there is a way to get rid of them (so finding the really interesting warnings in the report becomes much, much easier): You can just modify the XILINX DP-RAM Macros so they only contain the DP-Output. Do not worry, you won't be able to change the macros in the original XILINX library. Just save the modified macros in your own library and use these instead of the original XILINX versions. This little trick helped me very much since I got more than 300 warnings just because of this single problem. SvenArticle: 16963
Seems like you get the advantages that Actel devices already enjoyed over Xilinx/Altera devices (i.e. lower power consumption, design security, and non-volatility) ... the new proASIC offerings add higher density (~100K - 1M gates) and reprogrammability :-) Martin Duffy wrote: > > I see Actel have announced their new proASIC family. This is billed as a > cheap (programmable) alternative to using gate arrays. > This sounds familiar - Xilinx/Altera have similar product offerings. > > But it's different in that it's 1) flash-based, and 2) a fine-grained > sea-of-gates architecture. > > Does anyone know why this choice of technology & architecture should prove > superior - or even the equal - of those of the 2 big boys ? > Because to me "flash-based" means CPLDs, "sea-of-gates FPGA" means Motorola, > Toshiba, Xilinx 8K (and what happened to them?). > So this product is definitely going against the grain (sorry! couldn't > resist!).Article: 16964
[Newsgroup list trimmed to comp.arch.fpga only.] ems@riverside-machines.com.NOSPAM wrote in message <376b6ef7.3817695@news.dial.pipex.com>... >On Fri, 18 Jun 1999 22:58:49 GMT, "Jan Gray" <jsgray@acm.org.nospam> >wrote: >>(**) or worse, since we must fashion each 32x1 dual port ram from two 16x1 >>ones, requiring a 2-1 mux per bit, and since M1 tools do not allow two >>FMAPs and an HMAP to be RLOC'd to the same CLB. > >I'm not quite sure what you mean by this (a 16x1 dual-port RAM >requires both the F and G function generators, so you couldn't pack 2 >in a 4K CLB), but M1 has no problem with 2 FMAPs and an HMAP in the >same CLB - for a VHDL example, see: > >http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm > >You'll have to manually navigate to rloc4.vhd, since my ISP keeps >messing around with 'upgrades' and screwing up FTP accesses. Sorry, I was neither clear nor (strictly speaking) correct. I should have said that (in my experience) M1 does not allow two FMAPs and a *fully independent 3-input* HMAP to be RLOC'd to the same CLB. To achieve a 32x1 dpram, we need 2 16x1 dprams (2 CLBs) and a 2-1 mux. (To write, we assert one dprams' WE. To read, the mux selects one of the two rams' outputs.) Depending upon the floorplanned logic surrounding the regfile rams, we can sometimes implement the mux "for free" in nearby, otherwise unused, H function generators. Unfortunately, M1 does not allow you to constrain two FMAPs and an HMAP to a CLB, *if* none of the 3 H inputs is an F output, as is the case here. So "there ain't no such thing as a free mux." See also http://deja.com/getdoc.xp?AN=415774321 and http://www.xilinx.com/techdocs/2289.htm. Your example, rloc4.vhd, has 2 FMAPs and an HMAP constrained to one CLB, but one of the HMAP inputs is an F generator output F_OUT. Thank you for your helpful web pages! Jan GrayArticle: 16965
This is a multi-part message in MIME format. --------------E209D8B1817B187351965208 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Steven Casselman wrote: > The Virtex daughter board will be $4995 for a V800. How much will be daugter boards for a V300 (if any)? -- Regards, Pawel J. Rajda ----------------------------------------------------------------------------- Pawel J. Rajda, MSc. E.E. mail: pjrajda@uci.agh.edu.pl Dept. of Electronic Engineering www: http://galaxy.uci.agh.edu.pl/~pjrajda AGH Technical University tel: (+48-12) 617 3980 Al. Mickiewicza 30 fax: (+48-12) 633 2398 30-059 Cracow, POLAND ----------------------------------------------------------------------------- --------------E209D8B1817B187351965208 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Rajda, Pawel J. Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Pawel J. Rajda n: Rajda;Pawel J. org: AGH Technical University adr: Dept. of Electronics;;Al. Mickiewicza 30;Krakow;;30-059;POLAND email;internet: pjrajda@uci.agh.edu.pl title: M.Sc. E.E. tel;work: +48 12 617 3980 tel;fax: +48 12 633 2398 tel;home: +48 12 634 0653 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------E209D8B1817B187351965208--Article: 16966
Hi can anyone tell me how to design a Digital PLL for FPGA in verilog or VHDL. regards deeps -- **************************** if hope has flown away In a night, or in a day, In a vision, or in none, Is it therefore the less gone? All that we see or seem Is but a dream within a dream. *****************************Article: 16967
A known workaround of a bug in the M1.4 version using the parallel JTAG cable was either to leave the PROG-Pin unconnected or upgrading the software with a supported bugfix. Is there also a similar bugfix for the M1.5i version? Actually, after configuring with the parallel cable and the FPGA connector, the outputs remain in their initial state. However, leaving the PROG-Pin unconnected the FPGA device (XC4003E) works fine. Thank youArticle: 16968
A known workaround of a bug in the M1.4 version using the parallel JTAG cable was either to leave the PROG-Pin unconnected or upgrading the software with a supported bugfix. Is there also a similar bugfix for the M1.5i version? Actually, after configuring with the parallel cable and the FPGA connector, the outputs remain in their initial state. However, leaving the PROG-Pin unconnected the FPGA device (XC4003E) works fine. Thank youArticle: 16969
Would designers who are using Viewdraw 7.5 and Foundation FPGA Express 1.5i like to share there design flow methodology? I would like to hear experiences for both VHDL and schematic as the top level. My own design flow still centers around the Metamor compiler and schematic as the top level and is as follows: 1) Setup the Foundation project manager to implement an XACT Step 6 design using the appropriate target device. 2) For each out of date VHDL source invoke the Metamor compiler and compile 3) From the project directory invoke a makefile which will run XNF2WIR then VIEWGEN on each VHDL XNF file which is out of date with respect to its schematic. 4) From the project directory run "check -p projname" to ensure that all the WIR files are derived from the schematics 5) From Viewdraw and the top level schematic produce the Xilinx EDIF listing 6) Implement the design from the Xilinx design manager. This is cumbersome to say the least and evolved out of many XC5200 series designs that I did. Now that I am targeting the Spartan series I would like to use FPGA Express but I don't have the Viewlogic version so I can't use Intelliflow (typical Viewlogic decision - screw ease of use just make money) and I can't seem to marry buses between Viewlogic and FPGA express when I invoke the tools manually. Please don't use this post as the start of yet another schematic only versus VHDL only design entry flame war. Let's just assume for the sake of discussion that a few people would like to use mixed entry methods and limit the discussion to evaluating that flow.Article: 16970
This paper examines some general concepts concerning Phase Locked Loop (PLL) usage and their application in programmable logic devices. A critique of a newly-announced PLL implementation for FPGAs also is included. http://www.xilinx.com/xbrf/xbrf006.pdf DEEPAK KUMAR T wrote in message <376DF9FF.19896B63@cisco.com>... >Hi > >can anyone tell me how to design a >Digital PLL for FPGA >in verilog or VHDL. > > >regards >deeps > >-- >**************************** >if hope has flown away >In a night, or in a day, >In a vision, or in none, >Is it therefore the less gone? >All that we see or seem >Is but a dream within a dream. >***************************** > > >Article: 16971
Hi, Can a FPGA's be used in Wireless Telecom applications ( e.g. 3G wireless, software radios, wireless base-stations.....etc.) If yes, what specific functions could the FPGA perform in these designs ? Any help/reference would be appreciated ! Thanks in advance......... AnuragArticle: 16972
> > As a matter of interest, when running this Spartan PCI interface as a > PCI slave, i.e. no DMA capability (in a normal PC), what sort of I?I > bandwidth do you get? In PCI, there really is no DMA, just target and master.... DMA has traditionally been though of as you program a start address and a length, and tell it to 'go' and the data is transferred without the CPU doing it. PCI master does NOT mean it does 'DMA', it just means the chip that can be a master can initiate cycles on the PCI bus, as opposed to a Target, that just receives them. Point I am trying to make, is just because you have PCI master capability, doesn't mean you can do traditional 'DMA', and in fact, the Xilinx PCI 'core' doesn't have DMA, you have to provide the logic for it in your back end. > In other words, do you need the full bus-mastering DMA core to get > 100-120MB/second? As I said above, 'full bus-mastering' and 'DMA' are two different things. It doesn't matter whether you are a target or a master, the bandwidth is based on what BOTH target and master are capable of. To get maximum bandwidth, BOTH target and master have to support burst transfers. Austin Franklin austin@darkroom.comArticle: 16973
Hi,
How about use the EPC2 reconfigable device(PLCC 20 pin)
Lewis
Garrick Kremesec ¼¶¼g©ó¤å³¹ <376678FC.5CEA58AF@ews.uiuc.edu>...
>Hello,
>
> This was brought up recently, but are there any erasable replacements
>for the 8 pin dip Altera EPC1? I'm really looking for something that is
>pin/function equivalent yet either electronically erasable or UV
>erasable.
>
>Thank you for the help.
>
>Garrick Kremesec
>University of Illinois
>gkremese@ews.uiuc.edu
Article: 16974Hi, I have a question about using OrCAD Express 7.2. I am using OrCAD 7.2 for FPGA design. 90% of the design is done using Schematic capture and the other 10% using VHDL. The design is being targeted to an Actel ACT2 device. I have to use a third party tool to synthesize the VHDL part in order to be able to make it TMR. For this I am using Actel's ACTMAP. I compile the VHDL file, get an EDIF netlist, translate it to a structural VHDL file and use it as a heirarchical block in the OrCAD schematic. I am able to compile fine, but when I run the resulting EDIF netlist through Actel Designer, it complains about the fanout on a particular signal in the VHDL block being above the limit and hence results in an error. The only way it seems like to overcome this problem is to go in and manually add buffers in the VHDL code to decrease the fanout. I was wondering if anyone had any similar experience with this flow and what you did to overcome this problem. I would also appreciate if anyone could share their experience about using OrCAD with other synthesis tools. Thanks in advance. -Raghu Tumkur. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.
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