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<mench@mench.com> wrote in message news:7folsd$kok$1@mench.mench.com... > In comp.lang.vhdl Ian St John <istjohn@spamcop.net> wrote: <snip> > Don't do it (as someone else said). > > But if you must rather than a long posting, just post a URL to the > information not suggested by Ian St. John for the subject line. And, > crossposting is preferred to multiposting, when the job may be > relevant to multiple groups. That way, people who read multiple > groups will see it only once. Posting an url for the details is good. Not often seen, but a good idea. Thanks for posting. To some degree I have to think it better to promote jobs for such specialized area's as fpga/vlsi by posting. The alternative would be direct email, or other even less desirable activities. Targetting is plain lousy. At least with postings clearly giving enough information to determine interest levels, the reader has the choice of looking closer. I.E. I much prefer using search engines to find companies selling products I am interested in, rather than having reams of email adverts delivered for products I have no use for. (spam) On balance, I see the need to advertise, and prefer it to be contained in a setting where I can chose to search it out. Search engines aren't perfect, so finding the urls that way doesn't alway work one hundred percent. Advertising specialized opportunities to special interest NGs meets my tolerance levels. The .jobs NG are for more popular or general opportunities. In my opinion.Article: 15951
You will need to give the 40150 its fuul bitstream. There is no way to partially configure the device. Philip In article <371EB665.C05DAC4@netas.com.tr> Utku Ozcan <ozcan@netas.com.tr> writes: > >We have XC40110XV device but we want to use the pin-to-pin >compatiable XC40150XV instead of that. 110 needs 3 x 1 Mb PROM >but 150 needs 4 x 1 Mb PROM. > >But the board of XC40110XV does only have 3 PROMs. Despite that, >is it possible to load XC40140XV configuration data into 3 x 1 Mb PROMs? >Is it possible to restrict the size of XC40150XV data to the one for >XC40110XV? > >Utku > >-- >I feel better than James Brown. > > >Article: 15952
How can I implement on EAB? Seems like it is needed to specify explicitly in VHDL code using utility like genmem, etc... Or can it be done during synthesis in synopsys, compilation in MAXPLUS? I need to implement many tables of 8-bit input and 8-bit output. And still many 32-bit registers. Please give me hint or any references.Article: 15953
It's quite good, I have more than 300 items in the bookmark. It can organize bookmark or favorite as a tree and find the websites which updated. how ever, it's very good as a 225K little program. :) it can be download from 209.207.230.17/download/bmm.exe -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15954
Ian Jamison <IJamison@iss-dsp.com> wrote: > Can anyone tell me (or point me in the direction of) any rules or > guidelines for posting Job adverts here? (eg. Don't, or prefix the > subject with "Job:"). Follow the guidlines in the misc.jobs.offered FAQ. Post only newsgroup-related jobs. If you're a head hunter, expect to get flamed.Article: 15955
We just finished a project in which we used XCS20XL's and XCS30XL's... From an engineering standpoint, they work great. There's less global clock resources than in say the 4000XL family which caused a little pain, but nothing too tough. The software works good, probably since it's heavily based on the 4000 family. Early on, Xilinx had trouble with yields on the XCS30XL part which caused us to miss some target dates. They seem to have it under control now, but I'd ask some pointed questions about yield and delivery on any of their newer parts... John Jon Sletvold wrote: > Hello. > > I'm in the design phase of a new electronic card, and at present > evaluating FPGA circuit. I'm familiar with the xilinx 3xxx series, but > consider to use the Spartan series, XC520, XC530 or XC540. > > Any experience whith pittfals or general problems using this device(es)? > > (Design information: registers, buffers and counters, totally about 300 > CLB. CPU buss interface to an Am186ES) > > Regards > > Jon S. > Dev. engineer Thomson-CSF Nortech asArticle: 15956
Hi everyone, I am not sure if this can be done using Xilinx Alliance. I have dug into the documentation but cannot find a simple answer. My global clock is 50 MHz, and there are signals that do not have to operate at this frequency, rather at 10-20 MHz. How do I specify this requirement in the ucf file? Any example will be highly appreciated. Regards, MicheleArticle: 15957
Hong Eun Jong wrote:
> How can I implement on EAB?
> Seems like it is needed to specify explicitly in VHDL code using utility
> like genmem, etc...
> Or can it be done during synthesis in synopsys, compilation in MAXPLUS?
> I need to implement many tables of 8-bit input and 8-bit output. And
> still many 32-bit registers.
> Please give me hint or any references.
I don't know how to do it with Synopsys, but I succeeded with
Leonardo-Spectrum and Synplify:
1. Leonardo-Spectrum recognizes memory-constructs and inferes RAM as an
LPM-Function
"LPM_RAM_DQ".
2. Synplify compiles LPM-Functions as black boxes (see ALTERA Application
Note 101
"Improving Performance in FLEX 10K Devices with the Synplify Software").
Hope this helps,
M.Michel
Article: 15958Bill- I agree with Andy's statement. FPGA Express will discard unconnected ports, which would account for the problem you observed. If this is not the case, then you should contact Viewlogic technical support (support@viewlogic.com). You can also contact me directly and I'll look at the design and tell you more. -Jim william pawlowski wrote: > Has anyone ever seen the when in a viewlogic schematic with a bus labeled > > DATA[27:00] > > that FPGA Express strips out bits 09 through 00 and all componets? > > Bill -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 15959
Austin- FPGA Express from Viewlogic and FPGA Express from Xilinx are essentially the same, with the exception that the licensing is different and the Xilinx version only supports Xilinx devices while Viewlogic supports all vendors. It is also possible that the revisions can be different. Viewlogic is at rev 3.1 and testing the 3.2 beta. -Jim Austin Franklin wrote: > Anyone know of any differences between the Viewlogic offering of FPGA > Express and the Xilinx offering of FPGA Express? > > Thanks, > > Austin Franklin > austin@darkroom.com -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 15960
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Hello Michele,
To answer your question, yes this can be done. Let me try to give
you a little example.
Lets say you have a clock running at 50 MHz and you have a clock enable
signal that runs to some of the FFs running off this same clock that you
know enables the registers every other period (i.e. run at half the
frequency). You could write a UCF file or use the constraints editor in
this fashion:
NET MY_CLOCK TNM_NET = Clock_1;
TIMESPEC TS_Clock_1 = PERIOD : Clock_1 : 50 MHz;
NET MY_CE TMN__NET = CE_1;
TIMESPEC TS_CE_1 = FROM : MY_CE : TO : MY_CE : 25 MHz;
TIMESPEC TS_CE_2 = FROM : PADS : TO : MY_CE : 25 MHz;
In this case, even though the FFs grouped together by the clock enable
signal MY_CE are clocked by the same clock, MY_CLOCK, as specified by
the period spec to run at 50 MHz, the timespecs TS_CE_1 and TS_CE_2 are
specified by a FROM-TO spec which will over-ride the Period constraint
because FROM-TO specs have a higher priority for the software and these
FFs will be targeted to run at 25 MHz. Alternatively, you could group
the registers together using a TIMEGRP rather than the TNM_NET if it is
more convenient.
Each type of constraint has a priority which can either override another
constraint or be overridden depending on the constraint. Also, if two
overlapping timespecs of the same type are specified, the tighter
constraint will reside unless it is qualified with a PRIORITY lower than
the other however this is rarely used so I will not go into too many
details about that in order to try not to confuse this situation any
more than it already has.
There is a good explanation of these priorities and many more examples
of timing constraints on our web site at:
http://support.xilinx.com/support/techsup/journals/timing/index.htm
I especially suggest going through the presentation
http://support.xilinx.com/support/techsup/journals/timing/presentation/timing/noframe/index.htm
as I know it has a few slides on constraint priorities that should do a
better job of explaining this than I can here.
Hope this helps you out.
-- Brian
"C. Michele Rogers" wrote:
> Hi everyone,
>
> I am not sure if this can be done using Xilinx Alliance. I have
> dug into the documentation but cannot find a simple answer.
> My global clock is 50 MHz, and there are signals that
> do not have to operate at this frequency, rather at 10-20 MHz. How
> do I specify this requirement in the ucf file?
>
> Any example will be highly appreciated.
>
> Regards,
> Michele
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
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<html>
<p>Hello Michele,
<p> To answer your question, yes this can be done.
Let me try to give you a little example.
<p>Lets say you have a clock running at 50 MHz and you have a clock enable
signal that runs to some of the FFs running off this same clock that you
know enables the registers every other period (i.e. run at half the frequency).
You could write a UCF file or use the constraints editor in this fashion:
<p>NET MY_CLOCK TNM_NET = Clock_1;
<br>TIMESPEC TS_Clock_1 = PERIOD : Clock_1 : 50 MHz;
<p>NET MY_CE TMN__NET = CE_1;
<br>TIMESPEC TS_CE_1 = FROM : MY_CE : TO : MY_CE : 25 MHz;
<br>TIMESPEC TS_CE_2 = FROM : PADS : TO : MY_CE : 25
MHz;
<p>In this case, even though the FFs grouped together by the clock enable
signal MY_CE are clocked by the same clock, MY_CLOCK, as specified
by the period spec to run at 50 MHz, the timespecs TS_CE_1 and TS_CE_2
are specified by a FROM-TO spec which will over-ride the Period constraint
because FROM-TO specs have a higher priority for the software and these
FFs will be targeted to run at 25 MHz. Alternatively, you could group
the registers together using a TIMEGRP rather than the TNM_NET if it is
more convenient.
<p>Each type of constraint has a priority which can either override another
constraint or be overridden depending on the constraint. Also, if
two overlapping timespecs of the same type are specified, the tighter constraint
will reside unless it is qualified with a PRIORITY lower than the other
however this is rarely used so I will not go into too many details about
that in order to try not to confuse this situation any more than it already
has.
<p>There is a good explanation of these priorities and many more examples
of timing constraints on our web site at: <A HREF="http://support.xilinx.com/support/techsup/journals/timing/index.htm">http://support.xilinx.com/support/techsup/journals/timing/index.htm</A>
<br>I especially suggest going through the presentation <A HREF="http://support.xilinx.com/support/techsup/journals/timing/presentation/timing/noframe/index.htm">http://support.xilinx.com/support/techsup/journals/timing/presentation/timing/noframe/index.htm</A>
as I know it has a few slides on constraint priorities that should do a
better job of explaining this than I can here.
<p>Hope this helps you out.
<br>
<p>-- Brian
<br>
<p>"C. Michele Rogers" wrote:
<blockquote TYPE=CITE>Hi everyone,
<p>I am not sure if this can be done using Xilinx Alliance. I have
<br>dug into the documentation but cannot find a simple answer.
<br>My global clock is 50 MHz, and there are signals that
<br>do not have to operate at this frequency, rather at 10-20 MHz. How
<br>do I specify this requirement in the ucf file?
<p>Any example will be highly appreciated.
<p>Regards,
<br>Michele</blockquote>
<pre>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</pre>
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Article: 15961
Bill --
The only other thing I can think of here is your syntax is a little
non-standard. The typcial way to label this bus is DATA[27:0] instead of
DATA[27:00]. Perhaps a change to the label will maintain the bits. Also,
there is no guarantee, even if the signals are used, that the names will be
maintained if they are a purely internal signal. The only names in a design
that will never change are the I/O of the FPGA.
Tom Barber
Viewlogic
Corporate Applications Manager
Jim Kipps <jkipps@viewlogic.com> wrote in message
news:3720A903.10894450@viewlogic.com...
> Bill-
>
> I agree with Andy's statement. FPGA Express will discard unconnected
ports,
> which would account for the problem you observed. If this is not the
case,
> then
> you should contact Viewlogic technical support (support@viewlogic.com).
> You can also contact me directly and I'll look at the design and tell you
> more.
>
> -Jim
>
> william pawlowski wrote:
>
> > Has anyone ever seen the when in a viewlogic schematic with a bus
labeled
> >
> > DATA[27:00]
> >
> > that FPGA Express strips out bits 09 through 00 and all componets?
> >
> > Bill
>
> --
> --------------------------------------------------------
> James R. Kipps FPGA Marketing Manager
> jkipps@viewlogic.com Phone: (508) 303-5246
> --------------------------------------------------------
>
>
Article: 15962
Adam --
I have been able to resolve this with your design. I'll be in touch via
email.
Tom Barber
Viewlogic
Corporate Applications Manager
Adam J. Elbirt <aelbirt@nac.net> wrote in message
news:37101B7C.8DC68C59@nac.net...
> Anyone out there a SpeedWave user for VHDL Simulation? I have a
> structural netlist output from FPGA Express for a design I synthesized
> into a Xilinx Virtex chip. I analyzed the VHDL in SpeedWave but when I
> go to load the design my top level entity isn't available for me to
> choose. When I examine the VHDL the entity is there. I have waited 5
> days now and Viewlogic tech support can't get the thing to analyze let
> alone verify the problem and propose a potential solution (big shock).
> Any help would be appreciated.
>
> Adam
>
Article: 15963
Eldho --
In the initial release of Intelliflow 7.5 with Workview Office 7.5, when
processing a Xilinx design, Intelliflow could not correctly parse the Xilinx
M1 output files to create the .ORD file, and Intelliflow simply "hung" at
this phase. Upgrading to the latest Intelliflow (version 7.53) which works
with Xilinx Alliance 1.5x will resolve the problem.
Tom Barber
Viewlogic
Corporate Applications Manager
<ekuria01@kepler.poly.edu> wrote in message
news:7f61hj$j54$1@nnrp1.dejanews.com...
>
>
> Hello,
> I just want to first thank everyone who wrote back to my earilier
> enquiries. I have one more.
>
> I am using the FPGA express package from synopsys to do my synthesis. I
> used the intelliflow program they have to try to synthesize a design. When
I
> bring my design into intelliflow, it checks my design to make sure that it
is
> synthesizable, and it passes the checks. When I then run the routing and
> placement routines after targeting a device, they also work fine. But, the
> program gets stuck in the process of generating a board level symbol. This
> symbol I guess would show me the schematic of how the CLBs are actualyl
wired
> toghether. The program stalls on the ORD file generation method which has
to
> be completed before a board level symbol can be generated.
>
> ANy help is greatly appreciated.
>
> --
> Eldho Kuriakose
> Nature Photography
> http://kepler.poly.edu/~ekuria01/
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 15964Please where can I find Xilinx JBITs classes or they are not free? ThanksArticle: 15965
Michele - There are a few ways to do what you want. Below is an example of one way to do it. You can also use the TPTHRU attribute to name slow paths. In your case you can leave your global 50MHz constraint in place, create a TIMGRP for the slow FFs, and use FROM:TO consraints to cover the paths from and to the TIMGRP. I recommend you learn the precedence rules that the tools use to determine which constraint to apply to multiply-constrained paths. I think those rules are in the libraries guide. Good luck. And don't forget to use your Xilinx FAE, the hotline, and the Xilinx website. Bob Sefton TIMEGRP addr_cntr = FFS(U_AUD_DRAM_CTL/ADDR_CNT_Q*); TIMEGRP fast_ffs = FFS(U_AUD_DRAM_CTL/* : U_AUD_TIMING/REFRESH_CNTR/* : U_AUD_TIMING/REFRESH_REQ_Q : U_AUD_TIMING/FETCH* : STARTN_* : PLAY_*) : EXCEPT : addr_cntr; TIMEGRP group1 = addr_cntr : fast_ffs; TIMEGRP slow_ffs = FFS : EXCEPT: group1; TIMESPEC TS_FF1 = FROM : fast_ffs : TO : fast_ffs : 14; TIMESPEC TS_FF2 = FROM : addr_cntr : TO : fast_ffs : 28; TIMESPEC TS_FF3 = FROM : addr_cntr : TO : addr_cntr : 28; TIMESPEC TS_FF4 = FROM : fast_ffs : TO : addr_cntr : 14; TIMESPEC TS_FF5 = FROM : slow_ffs : TO : slow_ffs : 50; TIMESPEC TS_FF6 = FROM : fast_ffs : TO : slow_ffs : 14; TIMESPEC TS_FF7 = FROM : slow_ffs : TO : fast_ffs : 28; "C. Michele Rogers" wrote: > > Hi everyone, > > I am not sure if this can be done using Xilinx Alliance. I have > dug into the documentation but cannot find a simple answer. > My global clock is 50 MHz, and there are signals that > do not have to operate at this frequency, rather at 10-20 MHz. How > do I specify this requirement in the ucf file? > > Any example will be highly appreciated. > > Regards, > MicheleArticle: 15966
On 23 Apr 1999 14:37:42 GMT, cr795@FreeNet.Carleton.CA (C. Michele Rogers) wrote: > >Hi everyone, > >I am not sure if this can be done using Xilinx Alliance. I have >dug into the documentation but cannot find a simple answer. >My global clock is 50 MHz, and there are signals that >do not have to operate at this frequency, rather at 10-20 MHz. How >do I specify this requirement in the ucf file? > >Any example will be highly appreciated. > >Regards, >Michele this can be difficult. the best sources of information are a couple of xilinx powerpoint presentations; i've got copies at: http://www.riverside-machines.com/pub2/xilinx/constraints/constraints.htm (but my server seems to be down at the moment). 'timingcsts.ppt' contains sections on constraining between multiple clocks and 'slow exceptions'. one tip: if you can, do a timing simulation, since this is the only way to check that your constraints are right, and that they work. evanArticle: 15967
Anyone using Lattice's version of Synplicity? -- Steven J. Ackerman, Consultant ACS, Sarasota, FL sja@gte.net http://www.acscontrol.comArticle: 15968
I'm using the embedded RAM within a Virtex chip and having some troubles with the post-route simulation. It seems that the RAM aren't "turned on" and all I get out of them is X's. Is there anything special that I need to do to access the data in the simulation? Thanks. AdamArticle: 15969
Using the WebFITTER tool, how would an individual obtain a back annotated VHDL netlist and SDF file for post-route simulation/verification ? Sanjeev Kwatra wrote: > > Hello, > I'm the developer of Xilinx WebFITTER -- a free CPLD design tool > on the web at http://www.xilinx.com/sxpresso/webfitter.htm . You can > submit your design in VHDL/Verilog/EDIF and get back a jedec file and > reports in a few minutes. > Please give it a try -- I am interested in comments/feedback. > > Regards > SanjeevArticle: 15970
In synplicity, you can use the use_altera_EAB attribute (I don't recall the exact name, but this is close) on a block of code to force it into an EAB. Be careful that you either make all the outputs registered or all unregistered or MaxPlus will kick it out of the EAB. This works both for logic and tables. You can also use the RAM LPMs as a black box, but it is a pain for simulation that way. I'm not sure what synopsis has, if anything in the way of attributes to accomplish the same thing. In that case you might have to resort to black-boxing the LPM ram function. Markus Michel wrote: > Hong Eun Jong wrote: > > > How can I implement on EAB? > > Seems like it is needed to specify explicitly in VHDL code using utility > > like genmem, etc... > > Or can it be done during synthesis in synopsys, compilation in MAXPLUS? > > I need to implement many tables of 8-bit input and 8-bit output. And > > still many 32-bit registers. > > Please give me hint or any references. > > I don't know how to do it with Synopsys, but I succeeded with > Leonardo-Spectrum and Synplify: > 1. Leonardo-Spectrum recognizes memory-constructs and inferes RAM as an > LPM-Function > "LPM_RAM_DQ". > 2. Synplify compiles LPM-Functions as black boxes (see ALTERA Application > Note 101 > "Improving Performance in FLEX 10K Devices with the Synplify Software"). > > Hope this helps, > M.Michel -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15971
Take the spartan over the 5K parts. It is alot more routable, faster and cheaper. The spartan architecture is very similar to the 4000E architecture. That architecture has quite a few features not present in the 3000 series that you may find useful, including the ability to use the CLBs as small rams, and carry chains (which make the counter timing consistent). Jon Sletvold wrote: > Hello. > > I'm in the design phase of a new electronic card, and at present > evaluating FPGA circuit. I'm familiar with the xilinx 3xxx series, but > consider to use the Spartan series, XC520, XC530 or XC540. > > Any experience whith pittfals or general problems using this device(es)? > > (Design information: registers, buffers and counters, totally about 300 > CLB. CPU buss interface to an Am186ES) > > Regards > > Jon S. > Dev. engineer Thomson-CSF Nortech as -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15972
Check to make sure they have valid data in them. You need to load them at somepoint. Until they have valid data at the addresses you are reading you will get 'x's out. Adam J. Elbirt wrote: > I'm using the embedded RAM within a Virtex chip and having some troubles > with the post-route simulation. It seems that the RAM aren't "turned > on" and all I get out of them is X's. Is there anything special that I > need to do to access the data in the simulation? > > Thanks. > > Adam -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15973
The report has links to VHDL (or Verilog or EDIF, as required) netlist and SDF file that you can click on to download. Alternatively you can click on the "download" button to save a file called allfiles.zip which contains all the relevant files created during implementation. The report also has a link to the VHDL or Verilog models of Xilinx primitives used in the implementation netlist. Sanjeev Richard Guerin wrote: > Using the WebFITTER tool, how would an individual obtain a back > annotated VHDL netlist and SDF file for post-route > simulation/verification ?Article: 15974
What is a good eval board for a hobbyist? I'm talking about the daydreamer sort of electronics fan. The kind who wants to realize a CPU out of a FPGA. But actually something easy on the wallet and ego...
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