Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
The availability of very high pin count FPGA's (think at the Xilinx XCV1000 in the small pitch FG860 package, a device with 512 user I/Os) makes the design of systems with very wide memory data buses very attractive when you figure the bandwidth that you can achieve by dedicating the majority of user I/Os to memory data lines. What I would like to understand are the potential limitations of this approach from a system level perspective, especially in terms of constraints given by routing congestions of the memory controllers inside the FPGAs and signal integrity issues like ground bounce noise generated by simultaneous switching outputs. Has anyone ever had any experience with regard to these problems? thanks in advance -Arrigo -- Dr. Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 < > phone: (626) 395-3695 Pasadena, CA 91125 / \ fax: (626) 795-8649Article: 15801
The Philips coolpld family ( 3.0 - 3.6V - PZ3064 2kgates & PZ3032) may be an alternate to the Xilinx 3030 Device. The spec sheet indicates a static IDDof 40ua for the PZ3064 device with a 2MHZ IDD of 1.3ma. The PZ3032 2MHZ IDD is specified at 200ua. For low current battery powered FPGA applications there are limited choices; Xilinx 3000L family or Philips. John Cain, Power Processing, Inc. Phoenix, AZ jjcain@goodnet.comArticle: 15802
Steve Casselman writes: > From what I here the Virtex will soon have lots of documentation > on the bit stream. That sounds helpful. > Also you don't really need the fully documented > bitstream if you have and API that allows you to manipulate the bit > stream > (ie JBITS http://www.xilinx.com/products/software/sx/sxpresso.html#JBITS ) I couldn't tell from the article if this API makes it possible to produce a synthesis tool for Virtex. [Please, no flames or "why?" questions]. I'd imagine not, going by the history of FPGA vendors. But Xilinx did release the 6200 documentation. -- JamieArticle: 15803
Arrigo Benedetti writes: > Has anyone ever had any experience with regard to these problems? Making a PCB that will route all those signals is a real challenge! -- JamieArticle: 15804
Hi Craig:
I assume you left the AD data sheet on my desk. Do you know what form
the CIC filters take.
I.E. how many multiplies? Seems like we could outperform this chip by
10x based on the claim of 130 M FIR taps/sec. At 65 MSP/ we would have a
budget of 64 mults/sample.
Brad
--
----------------------------------------------------------------
Web Page: file:////chamfs/share/applications/web/top.html
----------------------------------------------------------------
Brad Taylor Chameleon Systems
Phone: 1-408-730-3300 ext 108
Fax: 1-408-730-3303
Email: <Brad Taylor> blt@cmln.com
WWW: www.cmln.com
Location: 1195 W. Fremont Ave
Sunnyvale, CA 94087-3825
----------------------------------------------------------------
Article: 15805
Hi everyone,
Has been dissapointing not to get any responses to my question. So I'll
pose it again. What is the best way to learn about fpga's, specially XILINX?
I want to be able to get my hands dirty with them, since I think they are
becoming an important trend in logic design. Schools don't do a good job, so
I want to know what's available ( student editions maybe?) for people like
me that want to learn about this subject. Thanks in advanced. Vic Lopez.
Article: 15806
Yes, you can download it, but it won't work correctly. You will have to drop
back to XACT 6.0 I think. I had the same type of problem, in that I was
fielding some new bitsteam images for a board with 4000e and/or 4000 series
FPGAs. In order to satisfy all the fielded boards I had to use some old
synthesis and XACT6.0. For some reason the new XILINX tools will not support
the non E series 5v 4000s. You can compile the new image and load it, butr it
won't work. The older 4000 series had no clock enables, and different routing
features.
Richard
Gianni Comoretto wrote:
> I have several Xilinx chips, series 4000 and 4000A
> None of the current support tools are able to implement a design using
> these chips, the first supported family is 4000E.
>
> It is possible to use a bitstream for a 40xxE in a 40XXA? Has anybody
> tried this?
>
> Thank you
> [if possible, send answer by E-mail]
> --
> Gianni Comoretto Osservatorio Astrofisico di Arcetri
> gcomoretto@arcetri.astro.it Largo E. Fermi 5
> http://www.arcetri.astro.it/~comore 50125 Firenze - ITALY
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15807
First Annual SNUG'99 Boston (Synopsys Users Group) Call For Papers
October 7 - October 8, 1999
The Westford Regency Hotel
Westford, Massachusetts
Preliminary Schedule: SNUG'99 Boston
Thursday, October 7th
Morning Tutorial Sessions
Afternoon Tutorial Sessions
Evening Cocktail Party
Friday, October 8th
Morning Executive Status
Mid-Morning User Breakout Sessions
Afternoon User Breakout Sessions
An Invitation to Contribute
Share your experiences ... The success of our users group depends on the
active participation of users who are willing to share their experiences
with others. If you have information on high-level design methodology or
experiences with Synopsys tools that would be of interest to other users,
you are encouraged to present in one of the sessions described below.
Awards
First, Second and Third place awards will be given for "Best Paper". The
winners are selected by the User Conference attendees.
Preliminary User Breakout Sessions
These sessions are always the hit of the conference. Hear Synopsys users'
experiences on specific topics. Each user breakout session will consist of
three presentations, twenty-five minutes each, with another five minutes
for questions and answers.
Preliminary topics include:
Synthesis/Design Productivity:
Strategies, experiences, and best practices for design productivity with an
emphasis on synthesis. Users share experiences with automation techniques
for synthesis.
High-Level Verification/Simulation Techniques using Behavioral Coding:
The higher level a design is coded, the more complex the design becomes to
verify. This session calls for papers on behavioral system modeling
approaches when given design descriptions and performance goals. Further
discussion includes the verification/simulation strategies to ensure design
correctness.
FPGA & PLD Synthesis:
Having surveyed the User community, it was brought to our attention that
there is a desire to see more User papers on FPGA. If you have any FPGA
stories to share with us, please come forward! Concentrating on the unique
challenges of programmable logic, the tricks and techniques used for
designing and synthesizing FPGAs or PLDs will be presented. Incremental
synthesis, fanout control, and floorplanning issues relative to FPGAs will
also be part of this section.
High-Level Verification/Simulation Techniques - (VCS):
System-level strategies covering design functional verification using
Verilog and VCS. Users share experiences in developing a test bed to verify
combined hardware and software systems for large complex designs.
High-Level Verification/Simulation Techniques - (VSS):
System-level strategies covering design functional verification using VHDL
and VSS. Users share experiences in developing a test bed to verify
combined hardware and software systems for large complex designs.
Higher Levels of Abstraction/Behavioral Synthesis:
User experiences with using behavioral synthesis are explored in this
session. Topics include high-level design techniques, behavioral
scheduling, datapath synthesis, pipeline retiming, and integration with
other ASIC design and verification tools. Other topics include the
methodology for top-down design, and high-level techniques for DSP design.
Hardware/Software Co-design:
Authors are invited to submit original papers describing recent experiences
in designing and verifying embedded processor-based ASIC/SOC systems. This
includes the methodologies used and tools required to handle tasks of
verifying both the hardware and software before physical prototypes are
available for these systems. Authors are encouraged to share their insights
on the use of the Eagle hardware/software tools, Cyclone, VSS, and VCS from
Synopsys and the overall impact on the project. Explore system design
objectives: Users experience with system development, verification and
integration.
Deep Submicron/Large Designs/Power/Physical Design:
This session concentrates on the unique challenges of submicron and low
power design techniques that may involve large design, deep submicron and
physical aspects. Low power & physical design sessions provide experience
with automating scripts for submicron, special techniques for managing
wireloading, floorplanning, over consumption, and non-linear delay modeling.
Makefiles Methodology/Configuration Management:
This popular session addresses the increased effort to automate and extend
the synthesis process through scripting. The session includes case studies
by users who have taken advantage of the power of Make and Perl to drive
synthesis iterations, to extend DC Shell, and to manage complex designs.
Design Reuse:
This session includes a practical methodology for design reuse based on
real-world experiences. Issues and guidelines are explored. Does anybody
really have a working Design Reuse methodology in place? Let us know about
it and how it works.
Test - DFT:
This session focuses on strategies and real-world experiences implementing a
manufacturing test strategy (DFT) for large SOC-type designs. Various SCAN
and isolation techniques are explored in the context of core-based designs.
Techniques used to interface a DFT solution (Full or Partial) with
synthesis and power will be included.
Protocol Compiler:
User experiences with Protocol Compiler in system or ASIC design,
explaining what the advantages and disadvantages are of using Protocol
Compiler over conventional HDL methodologies. Users will discuss how
Protocol Compiler's high abstraction level eases the designing of
structured data streams.
Module Compiler:
This session explores the use of Module Compiler to achieve high
performance datapath designs, focusing on effective datapath synthesis
strategies, coding styles, and integration with other ASIC design tools.
User experiences with datapath synthesis are shared.
PrimeTime Techniques/Formal Verification:
This session explores strategies and user experiences using a static
verification flow, concentrating on highlights and lowlights of static
timing analysis using Primetime and Formal Verification using Formality.
Further Information
Please check the SNUG Web site for the latest information on conference
dates, logistics, registration and ways you can contribute. Look for the
SNUG Boston logo. http://www.snug-universal.org/
To present your experiences by a contribution in a user session:
1. Please forward a brief summary description and an outline of your
idea to the Boston Conference Technical Committee,
(snug_boston@synopsys.com), by May 20th, 1999.
2. You will be notified of your acceptance by June 2nd, 1999.
3. When an Author is selected, an assigned Technical Committee member
will work with them to develop and review the paper and presentation.
4. Please review Author's Kit for details on paper format, deadlines,
and structure. http://www.snug-universal.org/
Important Dates
Submit Abstracts from April 14th - May 20th.
Notification of Abstract Acceptance will be June 2nd, 1999.
In-depth Outline due by June 23, 1999.
Papers for review are due by July 16, 1999.
Final papers for print are to be completed by August 4, 1999.
Slides for review due August 10, 1999.
Final slides for print are due August 14, 1999.
Registration Information
Registration information is not available at this time. Early registration
will start July 12, 1999. Check the web site frequently for the latest
information. Seek the SNUG Boston logo. http://www.snug-universal.org/
Who to Contact
Should you wish to discuss your potential contribution, please feel free to
contact your local Synopsys applications engineering manager or the SNUG'99
Boston Technical Committee via email at snug_boston@synopsys.com.
All email sent to this alias will be reflected to the User Group Technical
Chairperson and the Technical Committee. These addresses are not for basic
information on attending the conference itself.
SNUG'99 Boston Technical Chair
Don Mills
Salt Lake City, UT
drmills98@earthlink.net
SNUG'99 Boston Conference Manager
Renae Cunningham
700 E. Middlefield Road
Mtn. View, CA. 94043
Fax: 650-584-4987
renae@synopsys.com
SNUG'99 Boston Conference Coordinator
Joanne Wegener
700 E. Middlefield Road
Mtn. View, CA. 94043
Fax: 650-584-4987
jwegener@synopsys.com
SNUG'99 Boston Conference Chairpeople
Bob Hauser, Woody Norwood, and Vito Mazzarino
700 E. Middlefield Road
Mtn. View, CA. 94043
Fax: 650-584-4987
hauser@synopsys.com
woody@synopsys.com
vito@synopsys.com
===========================================================================
Trying to figure out a Synopsys bug? Want to hear how 6,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 15808Hi, For one of my SOC designs, I need to take a make / buy decision for JPEG(codec) synthesisable soft core(preferably in verilog). If any one has any idea on any of the following then please respond. 1. The complexity in terms of gate count/ man month effort say for a 50Mhz core. 2. Pricing info of any JPEG core available off the shelf in the market. An early response will be highly appreciated. Thanks and regards -- Madaan -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15809
Go to Amazon.com and get the Xilinx student edition plus tutorial book. About $75 I think. In article <7f3qfd$43b$1@news.chatlink.com> "Vic Lopez" <lopez@networld.com> writes: >Hi everyone, > Has been dissapointing not to get any responses to my question. So I'll >pose it again. What is the best way to learn about fpga's, specially XILINX? >I want to be able to get my hands dirty with them, since I think they are >becoming an important trend in logic design. Schools don't do a good job, so >I want to know what's available ( student editions maybe?) for people like >me that want to learn about this subject. Thanks in advanced. Vic Lopez. > >Article: 15810
Does PC can read "Composer (Cadence)" Schematic ?Article: 15811
Peter Alfke <peter@xilinx.com> wrote: > No, do not even try! The XC4000A is a reduced-interconnect subset of the > XC4000. As you can see in its data sheet, it has fewer bits in the bitstream. > So, although you can implement the same functionality as in XC4000( accepting > the more limited interconnects ), the software is different. You have to use the > old software. Did reducing the interconnects really reduce the price (of manufacturing) much? (I'm curious!) Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/Article: 15812
Hamish Moffatt <hamish@rising.com.au> writes:
> Did reducing the interconnects really reduce the price (of
> manufacturing) much? (I'm curious!)
Reducing the density of critical wiring can easily double or triple
the yield. Since the wafercost stays the same, the cost per part
drops accordingly. If you can get rid of one interconnect layer
(don't think that's the case here), you strip of some wafercost as
well. The test and packaging cost is still the same, so even if you
get perfect yield at no wafercost the chips would still have to cost
something.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 15813Hello, I am trying to synthesize a pretty simple interface board using Xilinx xc4000 series and Fpga express. I am having some trouble. 1. When I go into FPGA express and load my code (a simple vhdl file with 1 entity and 1 behavioral arch), it compiles fine. I see that the icon that represents my code has a green check on it. When i clik on this icon, i get a yellow box with a pic of an or gate on it. Now, I click on FPGA express "create implimentation". This gives me an error saying that my negative clock edge triggered event will not work. Error: This use of clock edge specification not supported in routine QSM1 line 129 in file 'C:/din/qsm1.vhd' (HDL-109) this is line 129 129: if (ext_clk'event and ext_clk ='0') then -- and so on.. I know that teh xc4000 can do neg clock edges from looking at its CLB architechture. Any ideas on why this is so ? Thanks a lot for any help. -- Eldho Kuriakose Nature Photography http://kepler.poly.edu/~ekuria01/ -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15814
Brad, I'm not sure what the context was here, but a CIC (Cascaded integrator comb) filter is multiplier-less. It consists of cascaded integrators (basically an accumulator) and comb filters (an adder and delay element(s)). There is not a whole lot of flexibility in the response of these filters, but they work well for high order decimation. You might look up papers by Hogenaur for more information. Brad Taylor wrote: > Hi Craig: > I assume you left the AD data sheet on my desk. Do you know what form > the CIC filters take. > I.E. how many multiplies? Seems like we could outperform this chip by > 10x based on the claim of 130 M FIR taps/sec. At 65 MSP/ we would have a > budget of 64 mults/sample. > Brad > -- > > ---------------------------------------------------------------- > Web Page: file:////chamfs/share/applications/web/top.html > ---------------------------------------------------------------- > Brad Taylor Chameleon Systems > Phone: 1-408-730-3300 ext 108 > Fax: 1-408-730-3303 > Email: <Brad Taylor> blt@cmln.com > WWW: www.cmln.com > Location: 1195 W. Fremont Ave > Sunnyvale, CA 94087-3825 > ---------------------------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15815
Hi all does anybody have experience using the Sapien - or another - USB library to realize a USB end device with an Altera Flex10K? I'm getting into this situation and would like to prevent turning in circles, means learning from your experience. Thanks a lot Matthias Monhart, m.monhart@octopus.chArticle: 15816
Hello everybody.
Does anyone out there have a couple of spare XC 6200 FPGAs or,
better indeed, any PC board with the XC 6200 FPGA on it?
We are willing to buy them for a research prject.
You can answer to fabregat@inf.uji.es
Regards,
Germán Fabregat.
Article: 15817The latest Tech Nore from VisiCom describes how an FPGA-based board can be reconfigured to implement DSP function for image processing applications. Check under Today's Featue at www.edtn.com/pld Murray Disman Editor PLD Design CenterArticle: 15818
Germán Fabregat wrote: > Hello everybody. > > Does anyone out there have a couple of spare XC 6200 FPGAs or, > better indeed, any PC board with the XC 6200 FPGA on it? > > We are willing to buy them for a research prject. > > You can answer to fabregat@inf.uji.es > > Regards, > Germán Fabregat. There are still 6200 Hotworks boards stocked at marshalls. See our web site for details -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 15819
In article <c3e22p0c8.fsf@ite127.inf.tu-dresden.de>, Achim Gratz <gratz@ite.inf.tu-dresden.de> wrote: >Hamish Moffatt <hamish@rising.com.au> writes: >> Did reducing the interconnects really reduce the price (of >> manufacturing) much? (I'm curious!) >Reducing the density of critical wiring can easily double or triple >the yield. Since the wafercost stays the same, the cost per part >drops accordingly. If you can get rid of one interconnect layer >(don't think that's the case here), you strip of some wafercost as >well. The test and packaging cost is still the same, so even if you >get perfect yield at no wafercost the chips would still have to cost >something. Remember that ~90% of the area of most FPGAs is in the interconnect, and smaller designs generally have lower interconnect requirements, so it makes sense to have the small parts use a less rich interconnect, to save area. Also, when die size goes down, yeild goes up considerably, which also reduces part cost. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 15820
> > > Brad Taylor wrote: > > > Hi Craig: Hey who is this Craig dude?? ;-) Hey Brad is there anything you can tell us about the device architecture your working with? I'm sure the rest of us would like to know!! -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 15821
Oooops! Big mistake here. I somehow sent this message to the news group here instead of my co-worker. (I can't explain how, but I must have been browsing the newsgroup when I started up the message). I guess it could have been much worse. Does anyone know how to get a message off this newsgroup? This isn't the first time I've wanted to retract a post, but this is the first time I've had an excuse. I can't say much about what we are developing here, except that it's a chip, it's not an FPGA and it's going to have good performance. Brad Steve Casselman wrote: > > > > > > > Brad Taylor wrote: > > > > > Hi Craig: > > Hey who is this Craig dude?? ;-) > > Hey Brad is there anything you can tell us > about the device architecture your working > with? I'm sure the rest of us would like to know!! > > -- > Steve Casselman, President > Virtual Computer Corporation > http://www.vcc.comArticle: 15822
Jamie Lokier wrote:
> Steve Casselman writes:
> > From what I here the Virtex will soon have lots of documentation
> > on the bit stream.
>
> That sounds helpful.
>
> > Also you don't really need the fully documented
> > bitstream if you have and API that allows you to manipulate the bit
> > stream
> > (ie JBITS http://www.xilinx.com/products/software/sx/sxpresso.html#JBITS )
>
> I couldn't tell from the article if this API makes it possible to
> produce a synthesis tool for Virtex. [Please, no flames or "why?"
> questions].
>
> I'd imagine not, going by the history of FPGA vendors.
> But Xilinx did release the 6200 documentation.
>
> -- Jamie
I think Peter Athanas from Virginia Tech. has already written
a router based on JBits. But the answer to your question is
Yes. While JBits is is not a synthesis tool.
You write programs with JBits these programs can be used
to construct bit streams, modify bit streams (safest mode),
load bit streams (even over the net to remote nodes) and
read back bit streams (even over the net). Below is some
code snip to get a flavor of what JBits. It is a Java based
API for generation and manipulation of Xilinx 4000 based
(soon to be Virtex) bit streams (FPGA object code).
System.out.println("Writing LUTs.");
for (row=0; row<clbRows; row++)
for (col=0; col<clbColumns; col++)
try {
/* Write F LUT */
lut = Util.intToIntArray(row, 16);
jBits.setF(row, col, lut);
/* Write G LUT */
lut = Util.intToIntArray(col, 16);
jBits.setG(row, col, lut);
/* Write H LUT */
lut = Util.intToIntArray((row+col), 8);
jBits.setH(row, col, lut);
} catch (ConfigurationException ce) {
System.out.println("Error writing LUT at CLB(" + row + "," + col + "). Exiting.");
System.exit(-1);
} /* end catch() */
/* Write the bitstream */
System.out.println("Writing bitstream.");
try {
bytes = jBits.write(outfileName);
} catch (IOException ioe) {
System.out.println("Error writing file " + outfileName + ". Exiting.");
System.exit(-2);
} /* end catch() */
System.out.println(bytes + " bytes written to " + outfileName + ".");
// Read you FPGA
for (row=0; row<clbRows; row++)
for (col=0; col<clbColumns; col++)
try {
System.out.print("CLB(" + row + "," + col + "): ");
/* Read Tag */
tag = jBits.getTag(row, col);
System.out.print("Tag: " + Tags.GetName(tag) + " ");
if (tag != Tags.PROTECTED) {
/* Read F LUT */
lut = jBits.getF(row, col);
f = Util.intArrayToInt(lut);
System.out.print("F: " + f + " ");
/* Read G LUT */
lut = jBits.getG(row, col);
g = Util.intArrayToInt(lut);
System.out.print("G: " + g + " ");
/* Read H LUT */
lut = jBits.getH(row, col);
h = Util.intArrayToInt(lut);
System.out.print("H: " + h + " ");
}
--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
Article: 15823Hi Guys, I am a researcher at HR Advisors in Laguna Beach, California and I am assisting Newport Microsystems with their search for some High Speed Mixed-Signal Design guys. Please take a moment to browse the attached job descriptions and see if you may fit the bill and be up to the job at hand. Or, if you might know some people, professors, or engineering gurus who could do this type of work send them this way. Have a good year and.... Thanks a Million, Dimitrios K. (Cybrarian at HR Advisors) Please reply to dkhradvise@hotmail.com or hradvisors@earthlink.netArticle: 15824
begin 644 NPMS Jobs.htm
M/"%D;V-T>7!E(&AT;6P@<'5B;&EC("(M+R]W,V,O+V1T9"!H=&UL(#0N,"!T
M<F%N<VET:6]N86PO+V5N(CX-#0H\:'1M;#X-#0H\:&5A9#X-#0H@("`\;65T
M82!H='1P+65Q=6EV/2)#;VYT96YT+51Y<&4B(&-O;G1E;G0](G1E>'0O:'1M
M;#L@8VAA<G-E=#UI<V\M.#@U.2TQ(CX-#0H@("`\;65T82!N86UE/2)'14Y%
M4D%43U(B(&-O;G1E;G0](DUO>FEL;&$O-"XU,2!;96Y=("A7:6XY.#L@22D@
M6TYE='-C87!E72(^#0T*/"]H96%D/@T-"CQB;V1Y(&)G8V]L;W(](B-&1D9&
M1D8B/@T-"CQB/CQF;VYT(&9A8V4](F%R:6%L(CX\9F]N="!S:7IE/2LR/DYE
M=U!O<G0@36EC<F]S>7-T96US/"]F;VYT/CPO9F]N=#X\+V(^#0T*/&)R/CQF
M;VYT('-I>F4]+3(^5V5D+"`Q-"!!<'(@.3D@,C,Z-3$Z-34@0T14/"]F;VYT
M/@T-"CQB<CXF;F)S<#L-#0H\=&%B;&4@0D]21$52(%=)1%1(/2(X."4B(#X-
M#0H\='(^#0T*/'1D/DUA;F%G97(L($AI9V@@4W!E960@36EX960M4VEG;F%L
M($1E<VEG;CPO=&0^#0T*#0T*/'1D($-/3%-004X](C4B/DY035,M,#$\+W1D
M/@T-"CPO='(^#0T*#0T*/'1R/@T-"CQT9"!#3TQ34$%./2(V(CY"87-E9"!I
M;B!)<G9I;F4L($-!+"!.97=P;W)T($UI8W)O<WES=&5M<R!I<R!A;@T-"CQB
M<CYE>&-I=&EN9R!S=&%R="UU<"!S96UI8V]N9'5C=&]R(&-O;7!A;GD@9F]U
M;F1E9"!I;@T-"CQB<CY-87)C:"!O9B`Q.3DV+B!.97=P;W)T($UI8W)O<WES
M=&5M<R<@8V]M<&5T:71I=F4-#0H\8G(^861V86YT86=E(&ES(&EN('1H96ER
M('1E8VAN;VQO9WDN($-O;7!E=&ET;W)S(&EN('1H90T-"CQB<CY#;VUM=6YI
M8V%T:6]N<R!)0R!-87)K970@87)E(&-U<G)E;G1L>2!D979E;&]P:6YG#0T*
M/&)R/G!R;V1U8W1S(&EN(&UO<F4@97AO=&EC('1E8VAN;VQO9WDN($)Y(&1E
M=F5L;W!I;F<-#0H\8G(^=&AE<V4@<')O9'5C=',@:6X@0TU/4R!M:7AE9"US
M:6=N86P@=&5C:&YO;&]G>2P-#0H\8G(^3F5W<&]R="!-:6-R;W-Y<W1E;7,@
M8V%N(&]F9F5R(&ET<R!C=7-T;VUE<G,@=&AE#0T*/&)R/FEM<&]R=&%N="!A
M9'9A;G1A9V5S(&]F(&QO=V5R(&-O<W0L(&AI9VAE<@T-"CQB<CYI;G1E9W)A
M=&EO;BP@86YD(&EM<')O=F5D('!O=V5R(&1I<W-I<&%T:6]N+B!7:71H(&ET
M<PT-"CQB<CYE>&-E;&QE;G0@<')O9'5C="!S=')A=&5G>2!A;F0@<W1R;VYG
M(%9E;G1U<F4@0V%P:71A;`T-"CQB<CYB86-K:6YG+"!.97=P;W)T($UI8W)O
M<WES=&5M<R!I<R!I;B!P;W-I=&EO;B!T;R!B96-O;64-#0H\8G(^82!M86IO
M<B!P;&%Y97(@:6X@=&AE($-O;6UU;FEC871I;VYS($E#(&UA<FME="X-#0H\
M<#Y0;W-I=&EO;B!);F9O<FUA=&EO;CH-#0H\<#Y4:&ES('!O<VET:6]N('-E
M96MS(&$@2&%R9'=A<F4@16YG:6YE97)I;F<@36%N86=E<@T-"CQB<CYW:71H
M(#4@=&\@,3`@>65A<G,@97AP97)I96YC92X@475A;&EF:65D(&-A;F1I9&%T
M97,-#0H\8G(^;75S="!P;W-S97-S('!R;W9E;B!A;F%L>71I8V%L(&%B:6QI
M='D@86YD(&$@:&EG:`T-"CQB<CYL979E;"!T96-H;FEC86P@8F%C:V=R;W5N
M9"!T;R!P97)F;W)M(&-O;7!L97@@<F5S96%R8V@-#0H\8G(^86YD(&1E=F5L
M;W!M96YT('=O<FLN(%1E8VAN:6-A;"!L96%D97)S:&EP(&%B:6QI='D-#0H\
M8G(^<F5Q=6ER960N(%1H:7,@<&]S:71I;VX@:6YV;VQV97,@=&AE(&1E<VEG
M;BP-#0H\8G(^<VEM=6QA=&EO;BP@86YD(&EM<&QE;65N=&%T:6]N(&]F(&AI
M9V@@<W!E960-#0H\8G(^=&5L96-O;6UU;FEC871I;VYS(&%N9"!D871A(&-O
M;6UU;FEC871I;VYS(&-I<F-U:71S#0T*/&)R/G5T:6QI>FEN9R!#34]3('1E
M8VAN;VQO9VEE<RX-#0H\8G(^)FYB<W`[#0T*/'`^4F5S<&]N<VEB:6QI=&EE
M<R!I;F-L=61E.B9N8G-P.PT-"CQP/BH@1&5V96QO<"!A;F0@87!P;'D@<W1A
M=&4@;V8@=&AE(&%R="!E;F=I;F5E<FEN9RP-#0H\8G(^<V-I96YT:69I8R!T
M:&5O<FEE<R!A;F0@;65T:&]D<R!T;R!T:&4@<V]L=71I;VX@;V8-#0H\8G(^
M8V]M<&QE>"!T96-H;FEC86P@<')O8FQE;7,-#0H\8G(^*B!#;VYD=6-T(&EN
M=F5S=&EG871I;VYS(&%N9"!D97-I9VYS('1E<W0@87!P<F]A8VAE<PT-"CQB
M<CYF;W(@=&AE(&1E=F5L;W!M96YT(&]F(&YE=R!D97-I9VYS+"!M971H;V1S
M(&]R#0T*/&)R/G!R;V-E<W-E<PT-"CQB<CXJ(%-E<G9E(&%S('-C:65N=&EF
M:6,@8V]N<W5L=&%N="!O;B!A<F5A<R!O9@T-"CQB<CYE>'!E<G1I<V4N#0T*
M/'`^4F5Q=6ER960@17AP97)I96YC92]3:VEL;',Z#0T*/'`^*B!+;F]W;&5D
M9V4@;V8@86YA;&]G(&%N9"!D:6=I=&%L('1R86YS:7-T;W(@;&5V96P-#0H\
M8G(^9&5S:6=N(&ES(')E<75I<F5D+B9N8G-P.PT-"CQB<CXJ($$@4&AD(&]R
M($U3144@=VET:"!R96QE=F%N="!E>'!E<FEE;F-E(&ES(')E<75I<F5D+@T-
M"CQB<CXJ(%%U86QI9FEE9"!C86YD:61A=&5S(&UU<W0@8F4@97AP97)I96YC
M960@:6X@=7-I;F<-#0H\8G(^<W1A=&4M;V8M=&AE+6%R="!A;F%L;V<@86YD
M(&UI>&5D('-I9VYA;"!S:6UU;&%T:6]N#0T*/&)R/G1O;VQS+"!I;F-L=61I
M;F<@2%-024-%+"!-1%,@971C+B9N8G-P.PT-"CQP/B9N8G-P.SPO=&0^#0T*
M/"]T<CX-#0H-#0H\='(@0D=#3TQ/4CTB(T-#0T-#0R(^#0T*/'1D($-/3%-0
M04X](C8B/CQF;VYT(&-O;&]R/2(C0T-#0T-#(CX\9F]N="!S:7IE/2TR/BTM
M/"]F;VYT/CPO9F]N=#X\+W1D/@T-"CPO='(^#0T*#0T*/'1R/@T-"CQT9#Y%
M;F=I;F5E<BP@2&EG:"!3<&5E9"!-:7AE9"U3:6=N86P@1&5S:6=N/"]T9#X-
M#0H-#0H\=&0@0T],4U!!3CTB-2(^3E!-4RTP,CPO=&0^#0T*/"]T<CX-#0H-
M#0H\='(^#0T*/'1D($-/3%-004X](C8B/D)A<V5D(&EN($ER=FEN92P@0T$L
M($YE=W!O<G0@36EC<F]S>7-T96US(&ES(&%N#0T*/&)R/F5X8VET:6YG('-T
M87)T+75P('-E;6EC;VYD=6-T;W(@8V]M<&%N>2!F;W5N9&5D(&EN#0T*/&)R
M/DUA<F-H(&]F(#$Y.38N($YE=W!O<G0@36EC<F]S>7-T96US)R!C;VUP971I
M=&EV90T-"CQB<CYA9'9A;G1A9V4@:7,@:6X@=&AE:7(@=&5C:&YO;&]G>2X@
M0V]M<&5T:71O<G,@:6X@=&AE#0T*/&)R/D-O;6UU;FEC871I;VYS($E#($UA
M<FME="!A<F4@8W5R<F5N=&QY(&1E=F5L;W!I;F<-#0H\8G(^<')O9'5C=',@
M:6X@;6]R92!E>&]T:6,@=&5C:&YO;&]G>2X@0GD@9&5V96QO<&EN9PT-"CQB
M<CYT:&5S92!P<F]D=6-T<R!I;B!#34]3(&UI>&5D+7-I9VYA;"!T96-H;F]L
M;V=Y+`T-"CQB<CY.97=P;W)T($UI8W)O<WES=&5M<R!C86X@;V9F97(@:71S
M(&-U<W1O;65R<R!T:&4-#0H\8G(^:6UP;W)T86YT(&%D=F%N=&%G97,@;V8@
M;&]W97(@8V]S="P@:&EG:&5R#0T*/&)R/FEN=&5G<F%T:6]N+"!A;F0@:6UP
M<F]V960@<&]W97(@9&ES<VEP871I;VXN(%=I=&@@:71S#0T*/&)R/F5X8V5L
M;&5N="!P<F]D=6-T('-T<F%T96=Y(&%N9"!S=')O;F<@5F5N='5R92!#87!I
M=&%L#0T*/&)R/F)A8VMI;F<L($YE=W!O<G0@36EC<F]S>7-T96US(&ES(&EN
M('!O<VET:6]N('1O(&)E8V]M90T-"CQB<CYA(&UA:F]R('!L87EE<B!I;B!T
M:&4@0V]M;75N:6-A=&EO;G,@24,@;6%R:V5T+@T-"CQP/E!O<VET:6]N($EN
M9F]R;6%T:6]N.@T-"CQP/E1H:7,@<&]S:71I;VX@<F5Q=6ER97,@82!H87)D
M=V%R92!E;F=I;F5E<B!W:71H(#(M(#4-#0H\8G(^>65A<G,@97AP97)I96YC
M92!T;R!W;W)K(&EN(&$@:&EG:&QY+6-H87)G960L#0T*/&)R/F5N=')E<')E
M;F5U<FEA;"!E;G9I<F]N;65N="X@270@:6YV;VQV97,@9&5S:6=N+`T-"CQB
M<CYS:6UU;&%T:6]N+"!A;F0@:6UP;&5M96YT871I;VX@;V8@:&EG:"!S<&5E
M9"!L:6=H='=A=F4-#0H\8G(^86YD(&1A=&$@8V]M;75N:6-A=&EO;G,@8VER
M8W5I=',@=71I;&EZ:6YG($--3U,-#0H\8G(^=&5C:&YO;&]G:65S+B!+;F]W
M;&5D9V4@;V8@86YA;&]G(&%N9"!D:6=I=&%L#0T*/&)R/G1R86YS:7-T;W(@
M;&5V96P@9&5S:6=N(&ES(')E<75I<F5D+B9N8G-P.PT-"CQP/D$@35-%12!O
M<B!"4T5%('=I=&@@<F5L979A;G0@97AP97)I96YC92!I<R!R97%U:7)E9"X-
M#0H\8G(^5&AE(&-A;F1I9&%T92!M=7-T(&)E(&5X<&5R:65N8V5D(&EN('5S
M:6YG#0T*/&)R/G-T871E+6]F+71H92UA<G0@86YA;&]G(&%N9"!M:7AE9"!S
M:6=N86P@<VEM=6QA=&EO;@T-"CQB<CYT;V]L<RP@:6YC;'5D:6YG($A34$E#
M12P@3413(&5T8RXF;F)S<#L-#0H\<#XF;F)S<#L\+W1D/@T-"CPO='(^#0T*
M#0T*/'1R($)'0T],3U(](B-#0T-#0T,B/@T-"CQT9"!#3TQ34$%./2(V(CX\
M9F]N="!C;VQO<CTB(T-#0T-#0R(^/&9O;G0@<VEZ93TM,CXM+3PO9F]N=#X\
M+V9O;G0^/"]T9#X-#0H\+W1R/@T-"@T-"CQT<CX-#0H\=&0^36%N86=E<BP@
M1&EG:71A;"!63%-)($1E<VEG;CPO=&0^#0T*#0T*/'1D($-/3%-004X](C4B
M/DY035,M,#,\+W1D/@T-"CPO='(^#0T*#0T*/'1R/@T-"CQT9"!#3TQ34$%.
M/2(V(CY"87-E9"!I;B!)<G9I;F4L($-!+"!.97=P;W)T($UI8W)O<WES=&5M
M<R!I<R!A;@T-"CQB<CYE>&-I=&EN9R!S=&%R="UU<"!S96UI8V]N9'5C=&]R
M(&-O;7!A;GD@9F]U;F1E9"!I;@T-"CQB<CY-87)C:"!O9B`Q.3DV+B!.97=P
M;W)T($UI8W)O<WES=&5M<R<@8V]M<&5T:71I=F4-#0H\8G(^861V86YT86=E
M(&ES(&EN('1H96ER('1E8VAN;VQO9WDN($-O;7!E=&ET;W)S(&EN('1H90T-
M"CQB<CY#;VUM=6YI8V%T:6]N<R!)0R!-87)K970@87)E(&-U<G)E;G1L>2!D
M979E;&]P:6YG#0T*/&)R/G!R;V1U8W1S(&EN(&UO<F4@97AO=&EC('1E8VAN
M;VQO9WDN($)Y(&1E=F5L;W!I;F<-#0H\8G(^=&AE<V4@<')O9'5C=',@:6X@
M0TU/4R!M:7AE9"US:6=N86P@=&5C:&YO;&]G>2P-#0H\8G(^3F5W<&]R="!-
M:6-R;W-Y<W1E;7,@8V%N(&]F9F5R(&ET<R!C=7-T;VUE<G,@=&AE#0T*/&)R
M/FEM<&]R=&%N="!A9'9A;G1A9V5S(&]F(&QO=V5R(&-O<W0L(&AI9VAE<@T-
M"CQB<CYI;G1E9W)A=&EO;BP@86YD(&EM<')O=F5D('!O=V5R(&1I<W-I<&%T
M:6]N+B!7:71H(&ET<PT-"CQB<CYE>&-E;&QE;G0@<')O9'5C="!S=')A=&5G
M>2!A;F0@<W1R;VYG(%9E;G1U<F4@0V%P:71A;`T-"CQB<CYB86-K:6YG+"!.
M97=P;W)T($UI8W)O<WES=&5M<R!I<R!I;B!P;W-I=&EO;B!T;R!B96-O;64-
M#0H\8G(^82!M86IO<B!P;&%Y97(@:6X@=&AE($-O;6UU;FEC871I;VYS($E#
M(&UA<FME="X-#0H\<#Y0;W-I=&EO;B!);F9O<FUA=&EO;CH-#0H\<#Y,;V]K
M:6YG(&9O<B!$:6=I=&%L($1E<VEG;B!-86YA9V5R('=I=&@@-2TQ,"!Y96%R
M<PT-"CQB<CYE>'!E<FEE;F-E(&9O<B!H:6=H;'DM8VAA<F=E9"P@96YT<F5P
M<F5N975R:6%L#0T*/&)R/F-O;7!A;GDN(%1E<W0@97AP97)I96YC92!W:71H
M(&QA<F=E(&1E<VEG;G,@86YD#0T*/&)R/F-O;7!L97@@=&5S=&EN9R!C:&%L
M;&5N9V5S+B!3=')O;F<@8F%C:V=R;W5N9"!I;B!T97-T#0T*/&)R/G!A='1E
M<FX@<')O8V5S<VEN9R!A;F0@=&5S="!P<F]G<F%M(&1E8G5G(&%R90T-"CQB
M<CYR97%U:7)E9"X@2&EG:"US<&5E9"!D:6=I=&%L('1E<W0@97AP97)I96YC
M92!W;W5L9"!B90T-"CQB<CYH:6=H;'D@=F%L=65D+B!4:&4@86)I;&ET>2!T
M;R!D979E;&]P('1E<W0@8V%S97,@9F]R#0T*/&)R/F)O=&@@;&%B(&%N9"!S
M:6UU;&%T:6]N(&5N=FER;VYM96YT<R!I<R!A;'-O(&%N#0T*/&)R/F%D=F%N
M=&%G92X-#0H\<#Y4:&ES('!O<VET:6]N(&EN=F]L=F5S('1H92!D969I;FET
M:6]N(&%N9"!D979E;&]P;65N=`T-"CQB<CYO9B!H:6=H+7-P965D(%9,4TD@
M1&5V:6-E<RX-#0H\<#Y3<&5C:69I8R!S:VEL;',@:6YC;'5D93H@5F5R:6QO
M9R]62$1,(&1E<VEG;BP-#0H\8G(^<WEN=&AE<VES+"!S=&%T:6,@=&EM:6YG
M(&%N86QY<VES+"!F;W)M86P-#0H\8G(^=F5R:69I8V%T:6]N+"!S8V%N(&EN
M<V5R=&EO;BP@=&5S="!V96-T;W(@9V5N97)A=&EO;BP-#0H\8G(^<V]L:60@
M9&EG:71A;"!D97-I9VX@<VMI;&QS+"!C:&EP(&9U;F-T:6]N86P-#0H\8G(^
M=F5R:69I8V%T:6]N(&EN(&QA8B!E;G9I<F]N;65N="X-#0H\<#Y!(%!H1"!O
M<B!-4T5%('=I=&@@<F5L979A;G0@97AP97)I96YC92!I<R!R97%U:7)E9"X-
M#0H\<#XF;F)S<#L\+W1D/@T-"CPO='(^#0T*#0T*/'1R($)'0T],3U(](B-#
M0T-#0T,B/@T-"CQT9"!#3TQ34$%./2(V(CX\9F]N="!C;VQO<CTB(T-#0T-#
M0R(^/&9O;G0@<VEZ93TM,CXM+3PO9F]N=#X\+V9O;G0^/"]T9#X-#0H\+W1R
M/@T-"@T-"CQT<CX-#0H\=&0^16YG:6YE97(L($1I9VET86P@5DQ322!$97-I
M9VX\+W1D/@T-"@T-"CQT9"!#3TQ34$%./2(U(CY.4$U3+3`T/"]T9#X-#0H\
M+W1R/@T-"@T-"CQT<CX-#0H\=&0@0T],4U!!3CTB-B(^0F%S960@:6X@27)V
M:6YE+"!#02P@3F5W<&]R="!-:6-R;W-Y<W1E;7,@:7,@86X-#0H\8G(^97AC
M:71I;F<@<W1A<G0M=7`@<V5M:6-O;F1U8W1O<B!C;VUP86YY(&9O=6YD960@
M:6X-#0H\8G(^36%R8V@@;V8@,3DY-BX@3F5W<&]R="!-:6-R;W-Y<W1E;7,G
M(&-O;7!E=&ET:79E#0T*/&)R/F%D=F%N=&%G92!I<R!I;B!T:&5I<B!T96-H
M;F]L;V=Y+B!#;VUP971I=&]R<R!I;B!T:&4-#0H\8G(^0V]M;75N:6-A=&EO
M;G,@24,@36%R:V5T(&%R92!C=7)R96YT;'D@9&5V96QO<&EN9PT-"CQB<CYP
M<F]D=6-T<R!I;B!M;W)E(&5X;W1I8R!T96-H;F]L;V=Y+B!">2!D979E;&]P
M:6YG#0T*/&)R/G1H97-E('!R;V1U8W1S(&EN($--3U,@;6EX960M<VEG;F%L
M('1E8VAN;VQO9WDL#0T*/&)R/DYE=W!O<G0@36EC<F]S>7-T96US(&-A;B!O
M9F9E<B!I=',@8W5S=&]M97)S('1H90T-"CQB<CYI;7!O<G1A;G0@861V86YT
M86=E<R!O9B!L;W=E<B!C;W-T+"!H:6=H97(-#0H\8G(^:6YT96=R871I;VXL
M(&%N9"!I;7!R;W9E9"!P;W=E<B!D:7-S:7!A=&EO;BX@5VET:"!I=',-#0H\
M8G(^97AC96QL96YT('!R;V1U8W0@<W1R871E9WD@86YD('-T<F]N9R!696YT
M=7)E($-A<&ET86P-#0H\8G(^8F%C:VEN9RP@3F5W<&]R="!-:6-R;W-Y<W1E
M;7,@:7,@:6X@<&]S:71I;VX@=&\@8F5C;VUE#0T*/&)R/F$@;6%J;W(@<&QA
M>65R(&EN('1H92!#;VUM=6YI8V%T:6]N<R!)0R!M87)K970N#0T*/'`^5&AI
M<R!P;W-I=&EO;B!I;G9O;'9E<R!T:&4@9&5F:6YI=&EO;B!A;F0@9&5V96QO
M<&UE;G0-#0H\8G(^;V8@:&EG:"US<&5E9"!63%-)($1E=FEC97,N#0T*/'`^
M4W!E8VEF:6,@<VMI;&QS(&EN8VQU9&4Z(%9E<FEL;V<O5DA$3"!D97-I9VXL
M#0T*/&)R/G-Y;G1H97-I<RP@<W1A=&EC('1I;6EN9R!A;F%L>7-I<RP@9F]R
M;6%L#0T*/&)R/G9E<FEF:6-A=&EO;BP@<V-A;B!I;G-E<G1I;VXL('1E<W0@
M=F5C=&]R(&=E;F5R871I;VXL#0T*/&)R/G-O;&ED(&1I9VET86P@9&5S:6=N
M('-K:6QL<RP@8VAI<"!F=6YC=&EO;F%L#0T*/&)R/G9E<FEF:6-A=&EO;B!I
M;B!L86(@96YV:7)O;FUE;G0N#0T*/'`^475A;&EF:6-A=&EO;G,@:6YC;'5D
M92!"4T5%(&]R(&5Q=6EV86QE;G0O35-%12]0:$0-#0H\8G(^<')E9F5R<F5D
M('!L=7,@82!M:6YI;75M(&]F(#(@>65A<G,@97AP97)I96YC92XF;F)S<#L-
M#0H\<#XF;F)S<#L\+W1D/@T-"CPO='(^#0T*#0T*/'1R($)'0T],3U(](B-#
M0T-#0T,B/@T-"CQT9"!#3TQ34$%./2(V(CX\9F]N="!C;VQO<CTB(T-#0T-#
M0R(^/&9O;G0@<VEZ93TM,CXM+3PO9F]N=#X\+V9O;G0^/"]T9#X-#0H\+W1R
M/@T-"@T-"CQT<CX-#0H\=&0^16YG:6YE97(L($AI9V@@4W!E960@36EX960M
M4VEG;F%L($1E<VEG;CPO=&0^#0T*#0T*/'1D($-/3%-004X](C4B/DY035,M
M,#4\+W1D/@T-"CPO='(^#0T*#0T*/'1R/@T-"CQT9"!#3TQ34$%./2(V(CY"
M87-E9"!I;B!)<G9I;F4L($-!($YE=W!O<G0@36EC<F]S>7-T96US(&ES(&%N
M#0T*/&)R/F5X8VET:6YG('-T87)T+75P('-E;6EC;VYD=6-T;W(@8V]M<&%N
M>2!F;W5N9&5D(&EN#0T*/&)R/DYO=F5M8F5R(&]F(#$Y.3@N($YE=W!O<G0@
M36EC<F]S>7-T96US)R!C;VUP971I=&EV90T-"CQB<CYA9'9A;G1A9V4@:7,@
M:6X@=&AE:7(@=&5C:&YO;&]G>2X@0V]M<&5T:71O<G,@:6X@=&AE#0T*/&)R
M/F-O;6UU;FEC871I;VYS($E#($UA<FME="!A<F4@8W5R<F5N=&QY(&1E=F5L
M;W!I;F<-#0H\8G(^<')O9'5C=',@:6X@97AP96YS:79E(&5X;W1I8R!T96-H
M;F]L;V=Y+B!.97=P;W)T#0T*/&)R/DUI8W)O<WES=&5M<R!C86X@;V9F97(@
M:71S(&-U<W1O;65R<R!T:&4@;W!T:6UA;`T-"CQB<CYC;VUB:6YA=&EO;B!O
M9B!C;VUP971I=&EV92!E8V]N;VUI8W,L(&AI9VAE<@T-"CQB<CYI;G1E9W)A
M=&EO;BP@86YD(&EM<')O=F5D('!O=V5R(&1I<W-I<&%T:6]N+B!7:71H(&ET
M<PT-"CQB<CYE>&-E;&QE;G0@<')O9'5C="!S=')A=&5G>2!A;F0@<W1R;VYG
M(%9E;G1U<F4@0V%P:71A;`T-"CQB<CYB86-K:6YG+"!.97=P;W)T($UI8W)O
M<WES=&5M<R!I<R!I;B!P;W-I=&EO;B!T;R!B96-O;64-#0H\8G(^82!M86IO
M<B!P;&%Y97(@:6X@=&AE($-O;6UU;FEC871I;VYS($E#(&UA<FME="X-#0H\
M<#Y0;W-I=&EO;B!);F9O<FUA=&EO;CH-#0H\<#Y4:&ES('!O<VET:6]N(')E
M<75I<F5S(&$@:&%R9'=A<F4@96YG:6YE97(@=VET:"`R+34-#0H\8G(^>65A
M<G,@97AP97)I96YC92!T;R!W;W)K(&EN(&$@:&EG:&QY(&-H87)G960L#0T*
M/&)R/F5N=')E<')E;F5U<FEA;"!E;G9I<F]N;65N="X@270@:6YV;VQV97,@
M9&5S:6=N+`T-"CQB<CYS:6UU;&%T:6]N+"!A;F0@:6UP;&5M96YT871I;VX@
M;V8@:&EG:"US<&5E9"!L:6=H='=A=F4-#0H\8G(^86YD(&1A=&$@8V]M;75N
M:6-A=&EO;G,@8VER8W5I=',@=71I;&EZ:6YG($--3U,-#0H\8G(^=&5C:&YO
M;&]G:65S+B!+;F]W;&5D9V4@;V8@86YA;&]G(&%N9"!D:6=I=&%L#0T*/&)R
M/G1R86YS:7-T;W(@;&5V96P@9&5S:6=N(&ES(')E<75I<F5D+@T-"CQP/D$@
M35-%12!O<B!"4T5%('=I=&@@<F5L979A;G0@97AP97)I96YC92!I<R!R97%U
M:7)E9"X-#0H\8G(^5&AE(&-A;F1I9&%T92!M=7-T(&)E(&5X<&5R:65N8V5D
M(&EN('5S:6YG('-T871E(&]F#0T*/&)R/G1H92!A<G0@86YA;&]G(&%N9"!M
M:7AE9"!S:6=N86P@<VEM=6QA=&EO;B!T;V]L<RP-#0H\8G(^:6YC;'5D:6YG
M($E)4U!)0T4L($U$4R!E=&,N#0T*/&)R/B9N8G-P.SPO=&0^#0T*/"]T<CX-
M#0H-#0H\='(@0D=#3TQ/4CTB(T-#0T-#0R(^#0T*/'1D($-/3%-004X](C8B
M/CQF;VYT(&-O;&]R/2(C0T-#0T-#(CX\9F]N="!S:7IE/2TR/BTM/"]F;VYT
M/CPO9F]N=#X\+W1D/@T-"CPO='(^#0T*/"]T86)L93X-#0H-#0H\<#X\8CXU
M/"]B/B!R97-U;'1S(')E='5R;F5D+@T-"CQP/CQA(&AR968](B]O<V-A<B]R
M<'1M9W(N8V=I+S(T-#(U-#0P,30X,3DO;&ES="(^4F5T=7)N('1O(&UE;G4\
:+V$^#0T*/"]B;V1Y/@T-"CPO:'1M;#X-#0IS
`
end
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z