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If your looking for background information on Viterbi decoding I can send you some web links. I doubt if you'll find anything specific about Verilog or FPGAs related to Viterbi decoding, but there is information available about Viterbi decoding in VLSI. Good luck Tony **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****Article: 15676
Sorry to break the news to you, but both the Xilinx 4K (and Spartan) and Virtex architectures are superior to Altera 10K for typical DSP applications. There are several reasons for this. First, consider that DSP applications typically involve arithmetic operations. Using the carry chain in Altera breaks each LE into a pair of 3-LUTs, one for the 'sum' function and one for the 'carry'. Of the 3 inputs, one is dedicated to the carry in from the previous LE. That means that functions using the carry chain are limited to two inputs if you wish to stay in one level of logic. Moreover, if you need a function that has a third input such as an accumulator with load/clear, an adder-subtractor or the like, the second level of logic has to be outside of the LAB because of the carry chain structure. The interconnect between LABs in the 10K architecture have to go onto row routing, which stretches across the chip. This is slow, and it chews up routing you need to connect the bus-wide functions together. In contrast, the Xilinx architecture has dedicated carry logic, so you still have a 4-LUT when you invoke the carry chain. Many more arithmetic functions can be implemented in one level of Xilinx logic. Second reason is a little related in that DSP functions tend to be data path architectures with bus-wide connections between the subfucntions. As I stated, there is really no local interconnect aside from that inside the LAB. Connections from one level of the logic to the next need to go out onto the relatively global routing. Connections within a Row are considerably faster than if you cross column boundaries, and carry chain connections must remain within a row. The routing within a row is not sufficient to connect all the LABs in the row, so you run out of row routing long before you run out of logic in the row. The wide local interconnect in typical DSP apps does not map well into this routing model. Crossing a row boundary incurs a substantial timing penalty, especially if the columns are not aligned (and the only way to direct placement in Altera is by hand in the floorplan view). Xilinx is rich in local interconnect (somewhat at the expense of speed on longer signals), which gives the opportunity for very dense high speed data path designs. That said, Xilinx is lots more sensitive to placement, so floorplanning of a DSP design is a must if you want performance. The third reason I prefer Xilinx over Altera is for Xilinx's ability to implement very efficient delay queues. The Synchronous 'select RAM' capability allows you to use a Xilinx CLB as a pair of 16x1 RAMs, a 32x1 Ram or a 16x1 dual port RAM. The synchronous RAM, along with a simple counter makes a delay element of up to 34 clocks per CLB (plus 2 1/2 clbs for the counter which can be shared among many delay elements). In pipelined DSP designs, there is a frequent need for bus-wide delay queues to match pipeline delays on parallel paths. The xilinx Ram does this very efficiently. Altera has no equivalent structure. Implementing a delay queue in Altera uses one LE for each bit and each clock cycle of delay. A 32 bit 16 clock delay in xilinx uses 19 CLBs, while the same delay in ALtera uses up 512 LEs (64 LABs). The xilinx RAM capability also offers a way to reload constant coefficients (in filters for example) with very little overhead by rewriting the RAMs directly. ALtera requires an additional register to hold the programmed coefficients. The RAM is also handy for reordering such as that needed for shared cycle complex multiplies or small FFT. Altera does offer a limited number of EAB blocks (memory blocks with 8 to 11 address and 1 to 8 data lines) which can help as delay queues or in realizng functions. There are too few of these to significantly offset the above mentioned shortcomings. Altera is still an acceptable technology for DSP (and I have used it in many DSP designs), its just not as good as the Xilinx offerings. Tony Kirke wrote: > There seems to be more support/usage of Xilinx than Altera Devices for DSP > Designs (FIRs, FFTs, Cordic, etc). > My company already has Altera tools but I don't want to be limited by that > choice. > Please let me know if you think Altera is better or equivalent for DSP > designs (or if you Xilinx is definitely superior). > Thanks, > I'll sumarise later for the group. > Tony > > **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) **** -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15677
Has anyone yet put together a Virtex part and a ZBT (any manufacturer) memory to work at 100Mhz or beyond? DaveArticle: 15678
Do you think we should put this DSP Q&A in the FAQ? On Wed, 07 Apr 1999 18:02:12 -0400, Ray Andraka <randraka@ids.net> wrote: <snip of merits of X vs A for DSP> >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > > For Email remove "NOSPAM" from the addressArticle: 15679
Andy Fatkullin wrote: > Hello, > > Could somone please tell me is there any FPGA for voltage working range > 3...6 V? > > Thanks in advance, > > Andrew XC3000A works between 3.0 and 5.5 V. At 6.0 V you are in non-guaranteed territory, but I am sure it will work. Don't know about 6.1 V :-) Is this a case of two Lithium batteries? Watch out for max voltage ! Peter Alfke, Xilinx ApplicationsArticle: 15680
FPGA Downloader for Altera FPGA/EPLD - ONLY $75.00 Works with any voltage from target board 1.8 V - 5.5 V Replaces Altera ByteBlaster and ByteBlaster MV downloader You will never need another downloader Please visit us at: http://welcome.to/nefdesign.com Sincerely, NEF Design, Inc. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15681
Stuart Clubb wrote: > Do you think we should put this DSP Q&A in the FAQ? > What FAQ?? -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 15682
Problem seems to be solved. It was that PROG-signal. If it is connected, it triggers programming after chip is programmed... So, its better to left that unconnected. Thanks for help! TepaArticle: 15683
I work with Xilinx FPGAs. Does anyone use or heard about a testing board for FPGAs from Xilinx, because I want to test a criptography chip and I wanna introduce data in the chip and to test the outputs. I can't only with the 7 LEDS and the pins from the borders. Thanks to anyone who want to help me!Article: 15684
Hi some comments between the lines.
Paul Butler wrote:
> Modern FPGAs are fast and large enough to handle complex designs. Add HDL
> design methods and in-system reconfiguration and you have hardware that can
> be developed and managed like software. Software developers take full
> advantage of language features to simplify development and support. An
> important technique that is largely ignored for synthesis is the use of
> descriptive data types. Aside from user defined types for state machine
> description, I don't see any encouragement from the press or tool vendors to
> use any VHDL type other than std_logic.
I'm using the other types (integer , integer types , arrays , record ,
enumerations ) all , if they are the right choice from the semantic point of
view. I even used to advocate the approach also with my colleagues. But in that
respect I'm a bit more doubtful nowadays. Some observations however :
- from tool vendor's point of view :
It will never be encouraged and the support for it is nearly always
lagging behind. The reason is obvious : they serve mainly two markets : VHDL
-customers and Verilog - customers. In their view it is the best to let VHDL
deviate as less as possible from Verilog. The best way to achieve this is to
limit types to std_logic_(vector) which has direct correspondence to the build
in Verilog type. Further you don't support any construct that is not found in
Verilog. Then you translate VHDL to Verilog (at least conceptually) and you can
support both with minimum effort.
By the way - at the risk of causing one more war - this is in my opinion one
of the reasons why VHDL is not as successfull as it could be from technical and
language point of view. It has much more potential to tackle the complex design
challenges , but tool support is often limited to the Verilog level. So no
chance to discriminate itself from Verilog. Think of really useful constructs as
configurations , aliasing , generics ...
- from designers point of view :
This time at the risk of sounding vain , but using the descriptive datatypes
('abstract datatypes') asks a level of abstract reasoning that is , I'll be
careful , not always found with the asic designers. For asic designers VHDL is
really in the first place a 'hardware description language' : think of hardware
with all it's wires , flip-flop and gates and try to describe it in text format.
While the more productive approach is often to think in more or less abstract
terms about the problem and describe it in those terms. Synthesizers are there
to map it to the hardware. (exception to be made for hardware where every square
micron needs to be utilized in the most efficient way) Your example is a good
one in the sense that the data-transfer is seen as an abstraction. But I will
show that this can be stretched even further , and probably there are reasons to
do so.
>
>
> The sample VHDL below seems like an obvious example of how to use a VHDL
> record. Any number of fields can be added to the signal_stats_t without
> changing the top-level code. Consider adding a strobe field (of type
> std_logic or maybe boolean) to the record that indicates when the sample
> data is valid. Without the record, signals like the data-valid strobe
> contribute to code clutter and, even with appropriate names, are hard to
> associate with the related data.
Exactly.
> Are designers writing code like this and I just don't know it? If not, why
> not?
I and some of my colleagues.
> library ieee;
> use ieee.std_logic_1164.all;
>
> package type_pack is
>
> subtype cpu_data_t is std_logic_vector(31 downto 0);
> subtype address_t is std_logic_vector(2 downto 0);
I assume that those are addresses and data , the width of which is imposed by an
existing component. As such the definition is OK.
If not , you could as well write (f.i.)
constant c_NumberOfAddresses : integer := 5;
type t_Address is range 0 to c_NumberOfAddresses-1;
> subtype adc_data_t is std_logic_vector(11 downto 0);
Here I even would be surprised that 11 is the emanation of your problem. Most
probably you have an ADC with 4096 possible values :
constant c_NumberOfAdcValues : integer= 4096;
type t_AdcValue is range 0 to C_NumberOfAdcValues-1;
> type signal_stats_t is
> record
> min_sample,
> max_sample,
> median_sample : adc_data_t;
: t_AdcValue;
Best regards,
Jos De Laender
Article: 15685Richard Schwarz wrote in message <370D3BAC.9CFF508F@apsfpga.com>... >. . . >coders go through elaborate means to try and use some VHDL language feature >which inevitably causes the code to become hard to follow and causes problems >later. Do you mean "coders cause problems" or "language features inevitably cause problems"? >I am a firm believer in keeping the code simple and straight foward Regardless of language features, concise writing is hard. A careful writer can use advanced constructs to simplify code. The same features will make a bad writer worse. This is an old issue for software developers yet they continue to add abstractions to their languages. Paul Butler Paul.Butler@natinst.com National Instruments Austin, TXArticle: 15686
Jos De Laender wrote in message <370CB59D.1BAAE3A3@alcatel.be>... >In their view it is the best to let VHDL >deviate as less as possible from Verilog. The best way to achieve this is to >limit types to std_logic_(vector) which has direct correspondence to the build >in Verilog type. Further you don't support any construct that is not found in >Verilog. That's a good point. I don't know Verilog and had assumed it had inherited flexible data types from C including something like "struct". > >Here I even would be surprised that 11 is the emanation of your problem. Most >probably you have an ADC with 4096 possible values : > I prefer to use std_logic as the underlying type because it models uninitialized and undefined states well. That's mainly a benefit in the early stages of debug. Also, my typical design would only transfer the data without modification so the numeric representation doesn't have much value for me. Paul Butler Paul.Butler@natinst.com National Instruments Austin, TXArticle: 15687
Are you proposing to create and maintain a FAQ? Stuart Clubb wrote: > Do you think we should put this DSP Q&A in the FAQ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15688
Go to http://www.optimagic.com. You'll find a listing of many boards in a variety of price ranges from several vendors there. Lower cost boards that come to mind are VCC's hotworks II, APS boards, Annapolis Micro's wild-one. Octavian Florea wrote: > I work with Xilinx FPGAs. > Does anyone use or heard about a testing board for FPGAs from Xilinx, > because I want to test a criptography chip and I wanna introduce data in > the chip and to test the outputs. > I can't only with the 7 LEDS and the pins from the borders. > > Thanks to anyone who want to help me! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15689
In article <370BD89C.1F1BE806@corp.atl.com>, David Reid <dreid@corp.atl.com> wrote: >Has anyone yet put together a Virtex part and a ZBT (any manufacturer) >memory to work at 100Mhz or beyond? > We now have available a synthesizable reference design for Virtex that works with ZBT SRAM up to 143MHz pipelined (ZBT-7ns any Virtex speed) and up to 100 MHz for flowthrough (ZBT-7ns any Virtex speed). with 250ps of board trace. You can download XAPP132 at http://www.xilinx.com/apps/virtexapps.htm This design has been verified on an actual board with Virtex and Micron devices. EdArticle: 15690
Wow, that Programmable Logic Jump Station is a great site! Keep up the good work
Steve. By the way, you all can read columns by Steve Knapp on FPGAs and
programmable logic in Personal Engineering Magazine. ( He would never plug
himself, so I'll do it for him).
Steven K. Knapp wrote:
> The various companies that sell serial configuration PROMs for FPGAs is
> listed on The Programmable Logic Jump Station at
> http://www.optimagic.com/companies.html#SPROM. If you need EEPROM instead
> of one-time programmable (OTP) EPROM, your choices are fairly limited at the
> moment.
>
> -----------------------------------------------------------
> Steven K. Knapp
> OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
> E-mail: sknapp@optimagic.com
> Web: http://www.optimagic.com
> -----------------------------------------------------------
>
> Arnaldo Oliveira wrote in message <370b7033.0@news.ua.pt>...
> >Hello,
> >
> >I need a EEPROM to program a Xilinx XC4010XL FPGA.
> >This device requires a 283,424 bits memory for full programming.
> >Atmel has "FPGA Configuration Memories" with 512Kbit and 1Mbit but the
> >package I need is not available (PDIP8).
> >Could someone please tell me the names of other companies which supply
> these
> >memories in a PDIP8 package?
> >Thanks.
> >
> >Arnaldo
> >
> >--------------------------------------------------------------------
> >Arnaldo Oliveira
> >Dep. de Electronica e Telec. - Univ. de Aveiro
> >Campus Universitario
> >3810 Aveiro
> >Portugal
> >tel.: +351 34 370200 fax.: +351 34 381128
> >email: arnaldo@ua.pt
> >--------------------------------------------------------------------
> >
> >
> >
> >
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15691Spike Technologies, Inc. is a rapidly growing company providing design and engineering services in the areas of VLSI and EDA with offices located in Milpitas, California. We are currently recruiting at various levels for the following full-time opportunities: VLSI Design Engineers (ASIC/FPGA/Circuit Design) Software Design Engineers (EDA) Technical Sales & Marketing Engineer For more information, visit our website http://www.spiketech.com or Apply by mail to H.R Dept. Spike Technologies, Inc. 75 South Milpitas Blvd., Ste 216 Milpitas, CA 95035 or Fax your resume to Fax: (408)945-0293 (Mention "NewsGroup" as reference)Article: 15692
Paul,
Many vendors support integer and signed and unsigned (2's compliment) types.
And subtypes are often is used in the code I have seen from many others in
synthesis. In synthesis I have not seen a lot of code which uses records, but
that does not mean they are discouraged. What I have seen, are cases where
coders go through elaborate means to try and use some VHDL language feature
which inevitably causes the code to become hard to follow and causes problems
later. I am a firm believer in keeping the code simple and straight foward,
unless a clear advantage is gained by using a particular feature. Also, one
problem which crops up from time to time is the VHDL87 and 93 feature support.
There are still some vendors not up to full 93 support. Features like aliases
and numeric_std libraries are often not used for fear of not being compliant
with some VHDL vendors.
Paul Butler wrote:
> Modern FPGAs are fast and large enough to handle complex designs. Add HDL
> design methods and in-system reconfiguration and you have hardware that can
> be developed and managed like software. Software developers take full
> advantage of language features to simplify development and support. An
> important technique that is largely ignored for synthesis is the use of
> descriptive data types. Aside from user defined types for state machine
> description, I don't see any encouragement from the press or tool vendors to
> use any VHDL type other than std_logic.
>
> The sample VHDL below seems like an obvious example of how to use a VHDL
> record. Any number of fields can be added to the signal_stats_t without
> changing the top-level code. Consider adding a strobe field (of type
> std_logic or maybe boolean) to the record that indicates when the sample
> data is valid. Without the record, signals like the data-valid strobe
> contribute to code clutter and, even with appropriate names, are hard to
> associate with the related data.
>
> Are designers writing code like this and I just don't know it? If not, why
> not?
>
> --
> Paul Butler
>
> Paul.Butler@natinst.com
> National Instruments
> Austin, TX
>
> ===============================================================
> library ieee;
> use ieee.std_logic_1164.all;
>
> package type_pack is
>
> subtype cpu_data_t is std_logic_vector(31 downto 0);
> subtype address_t is std_logic_vector(2 downto 0);
>
> subtype adc_data_t is std_logic_vector(11 downto 0);
>
> type signal_stats_t is
> record
> min_sample,
> max_sample,
> median_sample : adc_data_t;
> end record;
>
> end type_pack;
>
> library ieee;
> use ieee.std_logic_1164.all;
> use work.type_pack.all;
>
> entity adc_example is
> port(
> clk,
> cs,
> rd : in std_logic;
>
> address : in address_t;
>
> adc_din : in adc_data_t;
>
> cpu_dout : out cpu_data_t
> );
> end adc_example;
>
> architecture struct of adc_example is
>
> component adc_measurements
> port(
> clk : in std_logic;
> adc_din : in adc_data_t;
> signal_stats : out signal_stats_t
> );
> end component;
>
> component cpu_interface
> port(
> clk, cs, rd : in std_logic;
> address : in address_t;
> signal_stats : in signal_stats_t;
> cpu_dout : out cpu_data_t
> );
> end component;
>
> signal signal_stats : signal_stats_t;
>
> begin
>
> cpux: cpu_interface
> port map(
> clk => clk,
> cs => cs,
> rd => rd,
> address => address,
> signal_stats => signal_stats,
> cpu_dout => cpu_dout
> );
>
> adcx: adc_measurements
> port map(
> clk => clk,
> adc_din => adc_din,
> signal_stats => signal_stats
> );
>
> end struct;
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15693--------------68E6859A16018544666EF971 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Ed McGettigan wrote: > You can download XAPP132 at http://www.xilinx.com/apps/virtexapps.htm > > This design has been verified on an actual board with Virtex and > Micron devices. > > Ed Ed that page has moved (one less s) http://www.xilinx.com/apps/virtexapp.htm -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.com --------------68E6859A16018544666EF971 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Ed McGettigan wrote: <BLOCKQUOTE TYPE=CITE>You can download XAPP132 at <A HREF="http://www.xilinx.com/apps/virtexapps.htm">http://www.xilinx.com/apps/virtexapps.htm</A> <P>This design has been verified on an actual board with Virtex and <BR>Micron devices. <P>Ed</BLOCKQUOTE> Ed that page has moved (one less s) <A HREF="http://www.xilinx.com/apps/virtexapps.htm">http://www.xilinx.com/apps/virtexapp.htm</A> <P>-- <BR>Steve Casselman, President <BR>Virtual Computer Corporation <BR><A HREF="http://www.vcc.com">http://www.vcc.com</A> <BR> </HTML> --------------68E6859A16018544666EF971--Article: 15694
APS has several offerings. I would reccomend the APS X208 and APS-X240
boards. Both boards have ISA interfaces for downlaod and control.
Programming and control can be EASILY done using a standard C/PASCAL/BASIC
compiler in a PC environment.
The APS-X208 has a full featured windows control program which downloads the
FPGA configuration file (from the BUS) and controls a programmable Direct
Digital Synthesized (DDS) clock. It also has on board SRAM tied to the
socketed test FPGA. The test FPGA is a 208 pin QFP chip in a test socket.
This is great for general purpose design migration. The board supports FPGAs
in the 4000E, EX, XL, XLA configurations with sizes from a 4005 up to a
4085! And since the test FPGA is socketed, you can replace the FPGA if you
want to use a larger or smaller size.
http://www.associatedpro.com/x208/prod/x208_product.html
The APS-X240 family is designed for more of a stand-alone or embedded
application approach. It does have an optional ISA carrier card, so you can
place it in a PC chassis if you wish. It also comes with an optional PC-104
computer board which has RAM ROM and FLASH and allows full serial, and
ethernet control and downloading of the FPGA. The other nice feature of the
X240 board, is that you can easily stack the boards to give more FPGA
horsepower. Each X240 module has 256Kby 8 SRAM space as well as an
oscillator socket, EPROM socket and XCHECKER port. There are headers galore,
all with mucho ground pins. The new 16 bit verison will also have an on
board rs232 tranceiver chip to allow the board to used stand alone, with a
UART core for control and communications. And all this on the small PC104
format board. The FPGA on this board can be built to order with a
SPARTAN(XCS30 or XCS 40) and SPARTAN XL , XC4013 to XC 4085 E/EX/XL/XLA with
a VIRTEX version to soon follow.
http://www.associatedpro.com/x240/prod/x240prod.html
We also have a low cost X84 board ISA card which take any of the XILINX 5v
FPGAs. These boards are great low cost utility boards with on board eprom
socket, timer, and multi purpose headers. These boards can be purchased with
a small FPGA on board for as little as $170.00 !! (soon to be announced
special in our next newletter).
http://www.associatedpro.com/x84/prod/x84_ds.html
All of our kits are available with optional XILINX Foundation Software, and
come with numerous HDL and C control code examples.
Home page:
http;//www.associatedpro.com
Octavian Florea wrote:
> I work with Xilinx FPGAs.
> Does anyone use or heard about a testing board for FPGAs from Xilinx,
> because I want to test a criptography chip and I wanna introduce data in
> the chip and to test the outputs.
> I can't only with the 7 LEDS and the pins from the borders.
>
> Thanks to anyone who want to help me!
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15695http://www.xilinx.com/apps/virtexapp.htm One more shot -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 15696
Ray Andraka wrote: <snip> > For state machines, the same > applies. One technique that usually works well for larger state machines is to > use a one-hot encoding, which will limit the combinatorial inputs to each > register. Just curious how others handle the 2^N-N illegal states that are possible in a one-hot (or zero-hot) encoded state variable ... Does anyone else have horror stories regarding synthesys tools that totally ignored the 2^N-N "when others =>" cases ?Article: 15697
A one hot state machine has a real problem if it gets into an illegal state (2 flip-flops set). I tell the compiler to ignore all of these possibilities with a //synopsys full_case parallel_case pragma. I suppose you could implement special logic to detect whether 2 states ever exist and use that to reset your state machine. For example, when in state 0 if any other state is set, force it into state 0. I don't expect the compiler to deal with this auto-magically. A 20 state one-hot machine would eat a lot of logic (and speed) trying to detect all the illegal states, perhaps losing its advantage over a binary coding. I *always* use 1-hot because "flip flops are free" in most of my designs. (I'm generally LUT limited). Plus, they are fast. bruce Richard Guerin wrote in message <370D6007.712367AA@home.com>... > > >Ray Andraka wrote: ><snip> >> For state machines, the same >> applies. One technique that usually works well for larger state machines is to >> use a one-hot encoding, which will limit the combinatorial inputs to each >> register. > >Just curious how others handle the 2^N-N illegal states that are >possible in a one-hot (or zero-hot) encoded state variable ... Does >anyone else have horror stories regarding synthesys tools that totally >ignored the 2^N-N "when others =>" cases ?Article: 15698
Hello, I'm writing a paper on FPGA's and PGA's and would like any links to technical info on the above. Links to the architectual design of the above will also be helpful trini@wam.umd.eduArticle: 15699
One technique I use to recover from an illegal one hot state is to have the last state fire the reset to the whole machine rather than just blindly going back to the reset state. It may take a little while to recover (depending on how long it takes the first 1 bit to get to a terminal state), but it will recover. If you always look at all the states, the more than one detect logic quickly kills any advantage the one hot technique provided. Another technique I use is a bar graph style machine, where each flip-flop becomes set and then stays set until a terminal state is reached. The current state is indicated where the first 1 is. This style machine uses less combinatorial inputs to a state than a true one-hot. It also self recovers from errors on the next clock in most cases. It can be tricky to design, especially where there are lots of branches (each branch is treated as a separate shift register state machine, and activation of the first flop in one branch blocks activation of the first flop in all other branches at that node). Alot of the encoding style used comes down to the tradeoffs between speed, area and reliability. In lots of applications, you can accept a once in a very long while upset (we're talking a machine that is totally synchronous here - no asynch inputs) as long as it recovers in a reasonable amount of time (may be a whole circuit around the machine). Recovery should be automatic in most cases, although it may not need to happen until something else in the circuit discovers the error. At the other end of the spectrum, even a one clock upset can be devastating. In those cases, fault tolerance in the form of voting circuits etc is the name of the game. The key here is to know what level of tolerance you have for error (it won't happen in a synchronous circuit unless you get some external event such as an errant high energy particle that causes a bit to flip) and understand what recovery is needed to make the risks acceptable. Bruce Nepple wrote: > A one hot state machine has a real problem if it gets into an illegal state > (2 flip-flops set). I tell the compiler to ignore all of these > possibilities with a //synopsys full_case parallel_case pragma. > > I suppose you could implement special logic to detect whether 2 states ever > exist and use that to reset your state machine. For example, when in state > 0 if any other state is set, force it into state 0. I don't expect the > compiler to deal with this auto-magically. > > A 20 state one-hot machine would eat a lot of logic (and speed) trying to > detect all the illegal states, perhaps losing its advantage over a binary > coding. > > I *always* use 1-hot because "flip flops are free" in most of my designs. > (I'm generally LUT limited). Plus, they are fast. > > bruce > > Richard Guerin wrote in message <370D6007.712367AA@home.com>... > > > > > >Ray Andraka wrote: > ><snip> > >> For state machines, the same > >> applies. One technique that usually works well for larger state machines > is to > >> use a one-hot encoding, which will limit the combinatorial inputs to each > >> register. > > > >Just curious how others handle the 2^N-N illegal states that are > >possible in a one-hot (or zero-hot) encoded state variable ... Does > >anyone else have horror stories regarding synthesys tools that totally > >ignored the 2^N-N "when others =>" cases ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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