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Sorry if this doesn't apply to this newsgroup, but check out www.zbestcoffee.com for fresh coffee. You know, Folgers makes coffee, but we heard it sucks. 3bPath: ix.netcom.com!News.Toronto.iSTAR.net!news.istar.net!netnews.com!newspeer.monmouth.com!intgwpad.nntp.telstra.net!nsw.nnrp.telstra.net!bendor.com.au!not-for-mailArticle: 17401
Zoltan Kocsi wrote:
> husby@fnal.gov (Don Husby) writes:
>
> > As did I. And sometimes, when I'm forced to enter the Unix domain and
> > use one of those editors, I realize that I can write an entire 12-page
> > document with diagrams and color pictures using Microsoft Word in the
> > time it takes me to remember what the proper key combination is to exit
> > and save a text file from a Unix editor.
> > And give me Word any day over trying to hack runoff or LaTex.
>
> I offered not to start editor wars ...
just tossing in $0.02, hopefully not enough to fuel a small brushfire ... :-)
---------------------------------------
> As far as I know, StarOffice has been designed to be a MS Office clone
> and according to nettalk it is.
unfortunately, it is not fully compatible. i took some existing files and
tossed it into staroffice and it made, well, a mess. while we use many tools
that have versions on windoze and unix, and we can pass files between the two
platforms with little or no hassles, that is not true for word. (i didn't try
the other packages). since most people i deal with use word for writing, and we
do joint writing, i can't use linux/star office.
-----------------------------------------
> Despite all that, apparently those who got used to LaTeX would not
> trade it for any WYSIWYG WP when it's time to generate publishing
> quality technical or scientific documents.
i know a lot of people who are quite religious and feel strongly about latex. i
have used it and prefer word. i think it's easier to use ... and i can just
pick it up and use it. latex seems more complex. one can argue about which
produces better quality but i think good work could be done in either. in any
event, the content is number 1, right? i do find it very convient to be able to
take out put from own program and drop it into another (ex., placement of macros
from a chip editor). or, if a graph of data is embedded, a double click
automatically opens up the application and you can work on it. that's powerful
and it keeps everything in one file, which i find convenient. esp moving
documents from work to home.
-------------------------------------------
> Anyway, I don't know why would an MS Office clone be much harder to
> use than Office itself ? Or Applixware, for that matter ?
just didn't work reliably.
---------------------------------------------
> > A visual C++ development environment is much better than any Unix
> > environment I've ever used. The visual C++ debugger is quite pleasant.
> > Integrated object browsers, documentation, and resource editors make
> > it almost too easy to develop (windows-based) software. I've struggled
> > with Unix debuggers, but never found them easier to use than just putting
> > printf's in my code.
>
> There might be a significant difference between the SW domains we are in.
<snip a lot of good stuff. >
for developing test software, for example, it's hard to beat the newer graphical
environments on windoze. very impressive and powerful. for large s/w projects,
i understand the tools for configuration management and stuff are better on
unix. most of our stuff is like 2 people working together. quick and reliable
and ease of use is important for me for s/w, as i don't want to spend any extra
time on it and it needs to be very reliable and bug-free. btw, i use delphi.
-----------------------------------------------------
> > for doing other work, Windows is simply more useful. While Unix has
> > thousands of hackers controlling its evolution, Windows has millions
> > of customers and billions of dollars. It has the support of office
> > users, game players, scientific users, hardware developers, multimedia
> > developers, and millions of software developers, too. I agree that
> > evolution applies here, but it looks to me that natural selection
> > favors Windows. I don't like this any more than you do, but I've
> > accepted it.
>
> Well, I do not accept it, not yet anyway. Windows have a hell of a lot
> of development force and billions of dollars behind it, for sure.
> However, Windows still lacks quite a few things that unix can offer to me.
> Those developers care much more about the home user than a designer for
> home user is what most of those millions of Windows users are.
> Natural selection, in the long run, might favour Windows for home use.
> For development work natural selection should favour the flexibility
> and efficiency over the asthetics, I think, therefore either Windows
> changes significantly or unix is here to stay. Wishful thinking :-)
i note that a lot of the engineering packages that i use run on either unix or
windoze and look more or less the same. i think it's the app that is
important. and those apps have too many bugs and stuff in them. the os doesn't
seem to drive things for my environment too strongly. it's more driven by the
apps. for those who do large remote runs and do their work in ascii, obviously
the unix os does provide something that windoze doesn't. i know there are
programs like pcanywhere and stuff, i have heard good things, but i haven't
tried them out yet.
-------------------------------------------------------------------------------------
> > > By the way, what do you exactly do with graphics packages when you
> > > design FPGAs ?
> >
> > Sometimes I have to document my work. :)
>
> I misunderstood you. *That* kind of graphics is certainly available
> under unix - the office packages come with it, you can have CorelDraw
> or even a few free packages that offer fairly good graphics capabilities.
> I thought that you were talking about image processing, raytracing
> animation packages and alike (of which some are available under unix
> but I will believe you if you say they're toys compared to the Windows
> ones).
let's not forget schematic capture, waveform viewers and editors (with automagic
test bench generation), chip editors for examing and altering placement, etc.,
etc.
it's also nice to take a schematic fragment, copy it, and paste it into word.
-----------------------------------------------------------------------
personally, i think choice of os is (or should be) more driven by the tools
needed, what's available, and how they are operated. i don't think hardware
performance is important anymore, for most fpga work, all the hardware is pretty
fast. recent benchmarks show comparable performance or a slight edge to
intel/nt over sun. i like tools that are available on both unix and windoze and
operate similarly in both environments and have databases that are compatible.
for linux, just doesn't seem to be enough software out there yet, although i do
operate one linux machine (which is down and sick since the power blinked on it,
gotta get a ups).
have a nice day,
rk
Article: 17402ADULTS ONLY! http://207.240.225.250/ 3;z-9V+)Path: ix.netcom.com!howland.erols.net!newsfeed.fast.net!uunet!ffx.uu.net!news.usenetserver.com!news1.usenetserver.com.POSTED!dsdfs.comArticle: 17403
ADULTS ONLY! http://207.240.225.250/ N&[W8%H7Path: ix.netcom.com!howland.erols.net!newsfeed.fast.net!uunet!ffx.uu.net!news.usenetserver.com!news1.usenetserver.com.POSTED!dfdfws.comArticle: 17404
ADULTS ONLY! http://207.240.225.250/ R<<ky6f/Path: ix.netcom.com!news.maxwell.syr.edu!logbridge.uoregon.edu!newshub.tc.umn.edu!news1.tc.umn.edu!not-for-mailArticle: 17405
I'm working on a project where we're doing a microcomputer bus (kind of like VMEbus or PCIbus) for use *INSIDE* of FPGAs and ASICs. It's for hooking system-on-chip (SOC) components together. If anyone has done this before, or know of any references to this kind of project, I'd like to hear about it. Our project is called WISHBONE, and we're giving away the rights and specification for anybody who is interested in using the technology. More details can be found at: http://www.silicore.net/wishbone.htm IBM has also recently released a similar project called CoreConnect(tm). More details about this can be found at: http://www.chips.ibm.com/products/powerpc/cores/crcon_ug.html If anybody knows of similar technology, I'd like to hear about it. If there are more, then my intention is to start a FAQ database on our website for all to use. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 17406
Wade D. Peterson wrote in message <7ndpnl$pcu$1@news1.tc.umn.edu>...
>I'm working on a project where we're doing a microcomputer bus (kind of
like
>VMEbus or PCIbus) for use *INSIDE* of FPGAs and ASICs. It's for hooking
>system-on-chip (SOC) components together. If anyone has done this before,
or
>know of any references to this kind of project, I'd like to hear about it.
>If anybody knows of similar technology, I'd like to hear about it. If
there are
>more, then my intention is to start a FAQ database on our website for all
to
>use.
My 1995 J32 system had a 32-bit on-chip peripheral bus. The left 60% of the
XC4010 was a 32-bit RISC processor, using a 32-bit long line bus to
multiplex amongst the various execution stage results (including add/sub,
logic, 1-, 2-, 4-bit shifts left and right, load data, sign extension data,
return address). This used approximately 16x11=176 TBUFs.
The right half of the XC4010 was a 32-bit long line peripheral bus. It had
4 byte-wide lanes. The processor was byte addressable with byte, 16-bit
halfword, and 32-bit word data types.
Call the processor result bus P[31:0], the peripheral data bus D[31:0], and
the external RAM data bus XD[31:0]. I used these sets of TBUFs: (approx.
144 TBUFs + 32 OBUFTs):
* store byte, halfword, word:
D[7:0] <- P[7:0],
D[15:8] <- P[15:8],
D[31:16] <- P[31:16]
* load byte, halfword, word:
P[7:0] <- D[7:0],
P[15:8] <- D[15:8],
P[31:16] <- D[31:16]
* store various byte lanes to external RAM (OBUFTs)
XD[7:0] <- D[7:0]
XD[15:8] <- D[15:8]
XD[23:16] <- D[23:16]
XD[31:24] <- D[31:24]
* load various byte lanes from external RAM
D[7:0] <- XD[7:0]
D[15:8] <- XD[15:8]
D[23:16] <- XD[23:16]
D[31:24] <- XD[31:24]
* copy bytes/halfwords to upper byte lanes
D[15:8] <- D[7:0]
D[23:16] <- D[7:0]
D[31:24] <- D[15:8]
* copy bytes from upper byte lanes
D[7:0] <- D[15:8]
D[7:0]] <- D[23:16]
D[15:8] <- D[31:24]
In case you are interested, here is some of the source code which generated
this. It is my own "CNets HDL", a C++ class library for emitting XNF. ff()
is a flip-flop, tbuf() is a tbuf. Note the use of tlocs (LOCs for TBUFs).
void Mem::emit(Control& c) {
net(zad24n) = adn(23,20) == 0U;
net(zad20n) = adn(19,16) == 0U;
ff(selROM, zad24n & zad20n, c.marce, _, init(1));
ff(selRAM, ~adn[23] & ~(zad24n & zad20n), c.marce);
ackROM = start & selROM;
ack = ackROM | ackRAM | ackUART;
for (unsigned i = 0; i < 4; i++)
bytesel[i] = (byte & ad(1,0) == i) | (half & ad(1,1) == (i>>1)) | word;
// processor to internal dbus interface
ff(doutbytet, ~write, start, _, init(1));
ff(douthalft, ~(write & (byte|half)), start, _, init(1));
ff(doutwordt, ~(write & (byte|half|word)), start, _, init(1));
// dbus internal/external interface:
// emit 3state drivers to copy external dbus to/from internal dbus
bus(dbusin, cbit);
bus(dpads, cbit);
for (i = 0; i < cbit; i++) {
tsIgnore(dpads[i]);
iopad(dpads[i], ploc(dpadlocs[i]));
ibuf(dbusin[i], dpads[i]);
unsigned t = 1 + even(i);
tbuf(xd[i], dbusin[i], dinbyteextt[i / 8]);
obuft(dpads[i], xd[i], doutextt);
}
// byte/halfword load/store alignment logic
ff(b1b0t, ~( write & byte & ad[0]), start, _,
init(1));
ff(b2b0t, ~( write & (byte|half) & ad(1,0) == 2), start, _, init(1));
ff(b3b1t, ~( write & ((byte&(ad(1,0)==3))|(half&ad[1]))), start, _,
init(1));
ff(b0b1t, ~(~write & byte & ad[0]), start, _, init(1));
ff(b0b2t, ~(~write & (byte|half) & ad(1,0) == 2), start, _, init(1));
ff(b1b3t, ~(~write & ((byte&(ad(1,0)==3))|(half&ad[1]))), start, _,
init(1));
for (i = 0; i < 8; i++) {
unsigned t = 1 + even(i);
tbuf(xd[i+ 8], xd[i ], b1b0t, tloc(rowForBit(i+ 8),20,t));
tbuf(xd[i+16], xd[i ], b2b0t, tloc(rowForBit(i+16),20,t));
tbuf(xd[i+24], xd[i+ 8], b3b1t, tloc(rowForBit(i+24),19,t));
tbuf(xd[i ], xd[i+ 8], b0b1t, tloc(rowForBit(i ),19,t));
tbuf(xd[i+ 8], xd[i+24], b1b3t, tloc(rowForBit(i+ 8),18,t));
tbuf(xd[i ], xd[i+16], b0b2t, tloc(rowForBit(i ),17,t));
}
}
The on-chip "peripherals were a UART and on-chip RAM and ROM, enough to boot
and print a "hello world" message. There was also an integrated DRAM
controller.
You can see a floorplan of this at
http://www3.sympatico.ca/jsgray/sld021.htm.
Old articles which touched on this subject:
http://deja.com/getdoc.xp?AN=120389301&fmt=text
http://deja.com/getdoc.xp?AN=136481723&fmt=text
http://deja.com/getdoc.xp?AN=280290025&fmt=text
http://deja.com/getdoc.xp?AN=398007481&fmt=text
Recently I designed another on-chip bus with particular
CPU-to-bus-controller and bus-controller-to-peripheral interfaces. Please
write me for more information.
Jan Gray
Article: 17407I wrote: >...The left 60% of the XC4010 was a 32-bit RISC processor. >...This used approximately 16x11=176 TBUFs. Sigh. Rather, 32x11 = 352 TBUFs. Jan GrayArticle: 17408
This is a multi-part message in MIME format. --------------22D0A0077655F8EA52F15926 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit There is a VHDL2schematic viewer in Foundation-Express F1.5i (Full Express not Base). It can be found by running FPGA Express in stand alone mode ie don't start it from Foundation but rather use the Express icon that is in the Xilinx Foundation Series=>Accessories tab in the Start menu. If you are in a Base system the schematic editor supports "Generate Schematic From Netlist" . This command which can be found in the File menu of the schematic editor can be used to read in an edif or XNF netlist. The schematic may not have the most rational data flow but it is a schematic none the less. Thank You Nick Hartl ant wrote: > Hello, > > I'm using Foundation to synthesis my VHDL code and I wonder whether I > can get gate level layout (schematic) from the synthesis result. I'm > having a hard time debugging the code so that all timing constraints > will be met and the Post Layout Timing Report doesn't help much at all. > > Thank you very much, > Ant --------------22D0A0077655F8EA52F15926 Content-Type: text/x-vcard; charset=us-ascii; name="nickhartlxx.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Nick Hartl Content-Disposition: attachment; filename="nickhartlxx.vcf" begin:vcard n:Hartl;Nick tel;cell:(847)846-4007 tel;work:(847)797-7300 x-mozilla-html:FALSE org:Avnet version:2.1 email;internet:nhartl@hh.avnet.com title:Xilinx Distributor FAE adr;quoted-printable:;;Nick Hartl=0D=0AAvnet=0D=0A300 Salt Creek Lane Suite 300=0D=0A;Arlington Hieghts;IL;60173; end:vcard --------------22D0A0077655F8EA52F15926--Article: 17409
Jan Gray <jsgray@acm.org.nospam> wrote in message news:Jvwm3.331$Xc4.7387@paloalto-snr1.gtei.net... [SNIP] > My 1995 J32 system had a 32-bit on-chip peripheral bus. The left 60% of the > XC4010 was a 32-bit RISC processor, using a 32-bit long line bus to > multiplex amongst the various execution stage results (including add/sub, > logic, 1-, 2-, 4-bit shifts left and right, load data, sign extension data, > return address). This used approximately 16x11=176 TBUFs. > > The right half of the XC4010 was a 32-bit long line peripheral bus. It had > 4 byte-wide lanes. The processor was byte addressable with byte, 16-bit > halfword, and 32-bit word data types. Here are a few questions for you.... 1) When you say "on-chip peripheral bus" is this your terminology, or are you refering to a so-called 'OPB' bus that I'm seeing on some cores? For example, I believe that ARM processors use something called an 'OPB' bus. 2) Do you think your peripheral bus is portable across multiple FPGA architectures, or is it limited to Xilinx? Jan Gray <jsgray@acm.org.nospam> wrote in message news:Jvwm3.331$Xc4.7387@paloalto-snr1.gtei.net... [SNIP] > Old articles which touched on this subject: > http://deja.com/getdoc.xp?AN=120389301&fmt=text > http://deja.com/getdoc.xp?AN=136481723&fmt=text > http://deja.com/getdoc.xp?AN=280290025&fmt=text > http://deja.com/getdoc.xp?AN=398007481&fmt=text I tried these links, but they appear to be dead. Could you double-check the addresses? Jan Gray <jsgray@acm.org.nospam> wrote in message news:Jvwm3.331$Xc4.7387@paloalto-snr1.gtei.net... [SNIP] > Recently I designed another on-chip bus with particular > CPU-to-bus-controller and bus-controller-to-peripheral interfaces. Please > write me for more information. Do you have anything written up on these. I don't want you to create anything special (I know this takes a lot of time). However, if there were any other documentation I'd be interesting in hearing about it. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 17410
Hi! I'm looking for developers/managers to complete my masters thesis survey that has to do with the object-oriented model. Please go to the below link and fill out the form. I appreciate your support! Thanks very much, http://selab4.cs.depaul.edu:8080//consent.html -Robert PasenkoArticle: 17411
herry@poste.isima.fr wrote: > I'm using Renoir to write VHDL code and doing functionnal simulation. > With Leonardo I synthetize this code. Then I use Foundation 1.5 to > place & route (I import a XNF file produced by Leonardo). So when i go > back to Mentor software with my jedec file generated by Foundation 1.5, > I have problems to create a SCF file to do a timing simulation. Can > somebody hlep me, please? > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. Hello To do a timing simulation, you should go back with a .vhd and a .sdf files (time_sim.vhd and time_sim.sdf files by default). These files are created by Foundation. You need the simprim library to be accessible by Modelsim. Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 17412
Steven Derrien wrote: > Hi, > > I'm looking for advice, tips , or whatever information that would help > me with this : We'd like to design a Virtex daughter (WWW.Xilinx.com/) > board to plug on a s5933 matchmaker PCI prototype board > (www.amcc.com/XXX/). the daughterboard would include > > - One SRAM Bank > - A programmable clock > - A power supply/Voltage regulator > - A small XCV50 for the daughterboard control > - An Atmel EEPROM for XCV50 configuration > - A large Virtex device to implement custom designs > > The control FPGA would be initialised by an EEPROM on the board, and > would allow the second FPGA configuration through SelectMap mode with > configuration data coming from the PCI Bus. > > I'm wondering about the complexity of the PCB design for this board as > relatively high clock frequency would be used (over 60 Mhz), and as > different supply voltage are needed : Amcc prototype board can supply > its daughterboard with 5v voltage, however Virtex chips require both > 2.5v and 3.3v supply voltage. > > This would just be a prototype used for academic purpose, so we don't > really care about EMC , PCI compliance or whatsoever, we just want it to > work on a standard x86 PCI slot ... > > Can anyone gives me some tips or share experience on various problems I > may encounter. Specificallly I'd like to have an estimation about the > time required to design such a board : We would be four people involved > in the design, half of them having PCD CAD tool experience (although not > for such kind of boards). > > Thanks > > Steven Hello We are working on a similar project with the S5933 and 5 fpgas (2 virtex). The duration of the project depends mainly of the custom part. Our S5933 can only meet 33Mhz. Fully synchronous or asynchronous design? From my point of view, two unrelated clocks is the most difficult point. You should define if you want or not burst transfer, slave and master mode, mailbox, interrupt, 1 up to 4 BAR .... 3.3 V is not a problem as the I/O is 5V TTL compatible. The 2.5V regulator should be able to supply enough current. Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 17413
FPGA and FCCM are available from ACM and IEEE offices. FPL I think are published by Springer Verlag(97,98,99 ?), though I am not sure of the older ones. RAW 98,99 are available in the collection of proceedings of workshops as part of IPPS/SPDP from Springer Verlag. The earlier years have been by different publishers. Cheers, -- Kiran Eduardo Augusto Bezerra wrote: > Hello > > I'd like to know where to buy the proceedings of the following > conferences: > > - ACM/SIGDA International Symposium on Field-Programmable Gate Arrays > FPGA '97, FPGA '98 and FPGA '99 > > - Reconfigurable Architectures Workshop: RAW 1997, 1998 and 1999 > > - IEEE SYMPOSIUM ON FPGAs FOR CUSTOM COMPUTING MACHINES > FCCM '97, FCCM '98, FCCM '99 > > - International Workshop on Field-Programmable Logic and Applications > FPL '97, FPL '98, FPL '99 > > Thanks > > Eduardo. -- #ifndef kiran #define kiran kiran@usc.edu /* Mr.Bond */ #endif ------------------------------------------------------------------------ Kiran Kumar Bondalapati(BOND) kiran@usc.edu Ph.D. Candidate, Comp.Engg.,USC. http://www-scf.usc.edu/~bondalap ------------------------------------------------------------------------Article: 17414
http://www.teleline.es/personal/elyuma/home.htm Interesting Links http://www.teleline.es/personal/elyuma/pag7.htm Search http://www.teleline.es/personal/elyuma/pag9.htm Sound Wav MIDI http://www.teleline.es/personal/elyuma/pag10.htm Imagen Pictures gif Free Sex PicturesArticle: 17415
I have asked Xilinx if the data outputs from the Block Selct RAM are registered, or unregistered. (Flow-through). The person on the help line did not know. He said that he would get back to me. On the data sheet the terms "fully Sycnhronous" is used, but in another place it states the it states "the data out bus reflects the memory cells referenced by the address at the last active ckock edge. This last fact, plus the data sheet times of 3.3 ns of clock to output suggest to me that this is a fow through output, (unregistered) Has any one else asked this question and got a definite answer? I need to get on with design work, so I can't afford to wait for a few days while this gets answered. Thanks Courtenay JohnsonArticle: 17416
Hello,
I search soft and experience to translate XC7272 PC84 to XC9572
PC84 design.
(I am a french technicien with no experience in the epld and
fpga chip).
Thanks to reply at :
rdruesne@prosyst.fr
Bests regards.
Article: 17417Courtenay Johnson wrote in message <7nhis2$6q5$1@news.igs.net>... > >On the data sheet the terms "fully Sycnhronous" is used, but in another place it >states the it states "the data out bus reflects the memory cells referenced by >the address at the last active ckock edge. > >This last fact, plus the data sheet times of 3.3 ns of clock to output suggest >to me that this is a fow through output, (unregistered) > Contrariwise, this last fact, plus the data sheet times of any clock to output suggest to me that this is a registered output. I think I misunderstand the question. I have found that questions like this are often answered quickest by simulating a test design. I assume that the simulation models Xilinx provides are, if not timing accurate, at least functionally correct. Paul Butler Paul.Butler@natinst.comArticle: 17418
Many thanks to Andreas C. Doering for finding PI-BUS to add to my list. I've now found three FPGA/ASIC interconnection buses. I've started a summary web page (with hotlinks) at http://www.silicore.net/uCbusum.htm in case anybody else is interested in this. Keep em coming! -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 17419
Paul Butler wrote: > Courtenay Johnson wrote in message > > > >This last fact, plus the data sheet times of 3.3 ns of clock to output > suggest > >to me that this is a fow through output, (unregistered) > > > > Contrariwise, this last fact, plus the data sheet times of any clock to > output suggest to me that this is a registered output. I think I > misunderstand the question. > The data sheet is clear and unambiguous: In BlockRAM the outputs are synchronous = registered, with a clock-to-out specification. We work hard to wordsmith these descriptions clearly. In the CLB-based SelectRAM, however, the read output is non-synchronous = combinatorial. Just tell us when you find something confusing, and we will improve the description. Peter Alfke, Xilinx ApplicationsArticle: 17420
Mark Kinsley wrote: > We are currently investigating upgrading of our platform hardware. We > have a team of 3 designers each with an out-dated PC, these are > networked with two somewhat obsolete Spark Workstations. We are > running(crawling) ModelSim, Leonardo Spectrum and Maxplus II (Upgrade to > Quartus planned). > ModelSim and MaxPlusII run perfectly OK under PC's (I've never tried the others). > > With the good price performance ratio of PC platforms and the ease of > use of NT, we are considdering migrating our toolset to high end NT > machines. What the heck, we need new PC's anyway. What does concern me > however is the lack of multi-user support and performance levels. > Multi user support is not really an option under windows NT (compared to Solaris) but the performance is directly comparable > > I would hate to overlook any important issues which should be > considdered in making this decision, so if you have any input please > mail it to me / post it to the group. > > ...how beneficial is a Multi-CPU system for these tools ? Very important. Windows NT under multiprocessor systems run properly designed multi-threaded applications at almost n-times (n no of processors) a single processor speed (there is always an overhead there). The NT environment is undoubtly more user friendly and has a ten times better and more efficiently designed desktop. On the other hand more IC related applications have been designed towards Unix based related systems (over the years) and it may be considered more convinient to run them there. If I were you I would try to keep my options open and use both NT and Solaris systems (as most of the companies do !). > > > Regards, > Mark Kinsley > mkinsley @ xs4all.nlArticle: 17421
In article <7nhis2$6q5$1@news.igs.net>, Courtenay Johnson <cjohnson@igs.net> wrote: >I have asked Xilinx if the data outputs from the Block Selct RAM are registered, >or unregistered. (Flow-through). As the Virtex datasheet and Xilinx XAPP130 state that the Block SelectRAM in Virtex is fully synchronous. This means that all inputs have a setup-to-port_clock and all outputs have a port_clock-to-out timing specification. Both the read and write operations take only 1 clock edge to complete. For a read operation, the data appears on the Block SelectRAM outputs ~3ns after the port clock edge that captured the port memory address. In addition the outputs are glitchless. EdArticle: 17422
Peter Alfke wrote in message <379C8C06.33EE2CE6@xilinx.com>... > >Paul Butler wrote: > >> >> Contrariwise, this last fact, plus the data sheet times of any clock to >> output suggest to me that this is a registered output. >> > >The data sheet is clear and unambiguous: I never said otherwise. Paul Butler Paul.Butler@natinst.com National Instruments Austin, TXArticle: 17423
Hi, I am a grads student and just start to learn FPGA. My research direction is FPGA routing. I may use some FPGA design software like XACT step or Workview Office. I would like to know if there are any major differences between XACT or Workview Office. Any help would be appreciated. ZhibinArticle: 17424
Wade D. Peterson wrote in message <7nf1rv$5r$1@news1.tc.umn.edu>... >1) When you say "on-chip peripheral bus" is this your terminology, or are you >refering to a so-called 'OPB' bus that I'm seeing on some cores? For example, I >believe that ARM processors use something called an 'OPB' bus. My terminology, just a descriptive phrase. (It hosted on-chip memory elements and peripheral elements and interfaced to off-chip memory.) >2) Do you think your peripheral bus is portable across multiple FPGA >architectures, or is it limited to Xilinx? It is port-able, but not especially so, portability was not a design goal. 1. design tool: the CNets C++ class library, would need to be retargeted. Easy for Orca or Virtex, somewhat less so for other families. 2. implementation: used generic logic expressions and flip-flops, but there were lots of 3-state buffers, and the design was optimized using LOC constraints that would not apply to a non-XC4000. 3. interfaces (signaling): would work unchanged across architectures. (I do not propose the J32 bus for any purpose. I thought it might of historical interest.) >> Old articles which touched on this subject: >I tried these links, but they appear to be dead. Try again! >> Recently I designed another on-chip bus with particular >> CPU-to-bus-controller and bus-controller-to-peripheral interfaces. ... >Do you have anything written up on these. Sorry, the docs are not yet ready for publication. But I think some of the design space issues are: * zero, one, or more processors? on-chip or off-chip processor? :-) * clocking -- do CPU clocks equal bus clocks? 1-1? 2-1? 1-2? * processor has one memory port or two (Harvard)? * one bus (share processor result bus with on-chip data bus) or two? * any access to processor resources (e.g. reg file ports)? * byte addressing? byte/halfword/word types? byte-lane shifting? * is the on-chip bus connected to an off-chip I/O or memory bus? same width? same clock discipline? * wait state insertion? * multi-master? arbitration? * interrupt requests? * DMA requests? * pipelined bus transactions? * split transactions? In my current work-in-progress, the bus is: 1-1 with on-chip CPU's clock, Harvard, one bus, byte addressable, byte/16-bit-word data types, attached to a double-cycled external data bus, with arbitrary wait-states, interrupts, DMA, and pipelined bus transactions. Other comments. FPGA Device Architects: this on-chip bus stuff is so much easier if you follow the XC4000 lead and provide the abstraction of long, wide, partitionable buses with *abundant* 3-state drivers -- one per logic cell is good. The bus control itself can be built in programmable logic. Finally, in designing a on-chip bus with an eye on standardization, note some interesting design tensions: 1. malleable or fixed bus topologies and clocking disciplines? -- why not take advantage of FPGA flexibility and define a general bus architecture space, making allowance for one or more 8-, 16-, 32-, even arbitrary k-bit buses, and other dimensions of the design space I described above? Then customers can specialize designs to suit. -- Oops, that adds complexity and makes validation much harder. 2. lightweight or heavyweight? My current bus has a control overhead of ~2 CLBs per peripheral. At the opposite extreme, imagine an on-chip PCI bus. The latter would offer many features, like configuration registers, but these would be of little value in a cheap SOC in an XCS10XL or 20XL. I can't wait to see an on-chip bus standard (or standards) for FPGAs -- then we might finally see a marketplace of plug-and-play processors and peripherals cores. Jan Gray
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