Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> [snip[ > o Have you tried setting the Synplify ``max fanout'' parameter to something > lower than the Xilinx default of 100 ? My normal setting is 32 and in some > circumstances I take it down as far as 8. why do you choose this value always a power of 2? > o Have you checked the parameters that Foundation passes to MAP/PAR ? Some of > these are really for non-HDL designs & should be switched off. would you please give an example? > o You have tripped over some subtle and brand new bug in the Xilinx tools. If > so join the club. > > In order to really find out what's going on I think you'll have to make your > move out of the GUI playground sooner than you expected. I find Template Manager difficult to handle, so I think I would switch to command line. With a Perl script it would be easy to generate iterations and more abstract statistic reporting among a parameter region of the tools, by individually handling log files. UtkuArticle: 21126
Take a look at XAPP058 on this page: http://www.xilinx.com/apps/config.htm Jim Stewart wrote: <snipped> > > > Also, does Xilinx have anything like the "player" code that Altera has > that would allow an onboard processor to reprogram an XC9500 part from a > a programming file. > > Jim regards, Tom Burgess -- tom.burgess@hia.nrc.ca Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 21127
Kate Atkins wrote: > I didn't notice a significant difference in power consumption between the > A14100A and XC4028EX. Have you done a dynamic power estimate with that big > long formula Actel provide? If I remember correctly, the A14100A (5V, 0.8 um) is not one of the lower power devices, even compared with their Act 2 family. In fact, just looking at the die, you'll see it's quite huge and simply driving the clock network at a fairly high speed will consume quite a bit of juice. The 0.25 um, 2.5V SX-A series will give much lower power. Of course, the QL30xx series (0.35 um, 3.3V) devices should do pretty well too, with the magazines hinting that a new family is coming out from Quicklogic. Also, the more modern, low voltage Xilinx devices should do reasonably well in power when compared with older parts. I don't know much about Altera except for the fact that the 5192's, even when running very slowly (2 MHz) are a bit toasty to the touch. Naturally, your mileage will vary and I can look up numbers for many of these if anyone is that interested. rkArticle: 21128
MC68000 docs can be found at: http://ebus.mot-sps.com/ProdCat/sg/0,1251,934310184622,00.html Lee. -- Boycott Amazon: http://www.gnu.org/philosophy/amazon.html Trent Worthington wrote: > > On Tue, 07 Mar 2000 06:57:25 GMT, Tobin Fricke > <tobin@cory.eecs.berkeley.edu> wrote: > > >I've recently become interested in microprocessor architecture and have > >adopted as a personal project to implement a simple processor of some > >sort in an Altera FPGA. I'd like to learn about the architectures and > >implementations of various processors in use today and from the past. > >I'm familiar with the general "big ideas" such as load-store > >architectures, accumulator-architectures, etc, but I'd like to see some > >real world designs. I'd like to find some information on the early > >Intel and Motorola processors; where can I find data on the Intel 4004 > >and 8080? How about the Motorola 6800? Is there some book or website > >that offers a comparison of various designs? I'm also interested in > >seeing a comparison of modern designs, such as x86, Alpha, MIPS, ARM, > >PA-RISC, PowerPC, etc. > > > >Thanks, > >Tobin > > Datasheets for the 8080 can ge had here: > ftp://www.jameco.com/jameco_gifs/gallery2/000646/Article: 21129
Hans Holm <ff@sigcom.de> wrote: ... : 5.Did someone made experiences with programming services for higer : values of these devices? ... You might consider Quicklogic's WebAsic program as a (free) programming services... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 21130
Hmmm. I have heard no rumours, malicious or otherwise, but things in general must be very bad for Synplicity not to IPO. Almost everyone wants to invest in sexy high-tech stock these days so it makes you wonder how bad things have gotten if the assertion is true. I suspect it is not true. As for Mentor buying them, why bother? A private sale in todays climate would be indicative (IMHO) of an exercise in loss-limitation on the part of the private investors. It may be that they might figure on playing the big three off against each other, but I suspect neither Mentor nor Synopsys would be particularly interested (except for some small tid-bits of technology). That leaves Cadence in "Borg mode" again. Cheers Stuart On Mon, 06 Mar 2000 13:39:25 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >1209@my-deja.com wrote: > >> I heard that Synplicity is for sale and will not IPO. Who do you think >> will buy them, Cadence??? >> >> Sent via Deja.com http://www.deja.com/ >> Before you buy. > >What if its Mentor ? > An employee of Saros Technology: Model Technology, Exemplar Logic, TransEDA, Renoir. www.saros.co.ukArticle: 21131
The 4000E does not have SelectMAP available as a configuration mode. Check the datasheet for details. Mike Peattie usenet201@hotmail.com wrote: > I am developing an interface to configure a 4000E Xilinx Virtex FPGA > through the Select-Map paralell configuration method. > Can anyone direct me to a Xilinx document that > illustrates the necessary setup and hold times for Data with respect to > CCLK? I coulnd't find anything in their online documentation > (configuration documents and electrical specifications), nor could I > find anything in their tech. support answer database. I would appreciate > any info. Thanks. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 21132
Try to look here: http://www.free-ip.com/cores.htm They have a 6502 and a PIC core in VHDL. IvarArticle: 21133
Hi, I have some questions for WorkView Office and Alliance XACT: 1. Can Workview Office generate a .XNF netlist from ViewDraw? I only got .WIR files. 2. I produced a .EDN file from a Schematic by using EDIF tools in WVO. But when I use it on Alliance XACT to perform mapping, I got a message: ERROR:basnu:93 - logical block "$1I30/$1I1" of type "NOR2" is unexpanded. I think I missed something. What's wrong? 3. Is there a way to get information like switch consumption, number of connections and average length of connection in Xilinx tools? I appreciate any advice you provided! ZhibinArticle: 21134
Mike Peattie wrote: > The 4000E does not have SelectMAP available as a configuration mode. Check > the datasheet for details. the timing details for master parallel and for synchronous or asynchronous peripheral modes are on pages 6-62 through 68 of the '99 data book. Peter AlfkeArticle: 21135
On Tue, 7 Mar 2000 01:52:42, John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote: > Ian, > > A suggestion: Protection shouldn't prevent a copy from working; that's > too obvious. Protection should make a copy unreliable. Bad plan. The customers who *thought* they bought from you are no longer your customers. If you show them that it is not your product and will not support it, they will be far more understanding. Even a hint that they've accepted stolen merchanise will get many to pitch counterfeits. Bottom line: you really don't want to piss off your customers. ---- KeithArticle: 21136
On Tue, 7 Mar 2000 05:18:14, Phil Hays <Spampostmaster@sprynet.com> wrote: > "Keith R. Williams" wrote: > > > Possibly, but a UNIX make isn't going to help much. This is NT, > > sorry to say. > > There are make utilities for NT as well. I misunderstood. I thought you were talking about a particular "make". ---- KeithArticle: 21137
On Tue, 7 Mar 2000 01:14:07, krw@attglobal.net (Keith R. Williams) wrote: > On Fri, 3 Mar 2000 15:37:52, "Monte Dalrymple" > <monted@systemyde.com> wrote: > > > > > Keith R. Williams wrote in message ... > > > >1) What the hell am I doing wrong? Is this normal? > > > > > > > How much memory does your machine have? I had a design that > > fit nicely in a 4085 that could not complete the route before the MTBF > > of the machine with 256M of memory, but routed in about an hour on > > a machine with 1024M of memory... (ouch, $$$) > > 160MB PII-333. THe disk isn't active except when the log files > are written, so it's not paging. Even though it's not paging I > can see where more memory *might* help, but I' d like to hear > facts (BTW, I ordered more memory today and have drefted" a > PIII-600). Just to add a little to this, I ran the same P&R on my office PII-333 (160MB) and a lab PIII-600 (128MB). The P&R times were almost exactly proportinal to the processor speed. I don't think I'm memory constrained, though I "found" some 256MB sticks laying around. Unfortunately they're registered, so they won't do my office system any good. ---- KeithArticle: 21138
Make utilities: I use the nmake that comes with Microsoft Visual C++. I'm aware that there are many other make utilities, some of which are clones of Unix make utilities. Ray Andraka wrote: > I don't know what your design is, but I kinda suspect you are not registering > at the IOBs. I push registers into the IOBs whenever I can because it makes > the external timing independent of the internal implementation. If Synplify handles SpartanXL the same as it did the 4000 series, then IOB data registers are built when possible by default. Check using technology view, or otherwise look at the results to verify. The tristate enable register was a special case and I think that it still is. Synplify currently doesn't do this for Virtex, but it is rumored for next release. -- Phil HaysArticle: 21139
Ivar <[nospam]@[nospam]vip.cybercity.dk> wrote in message news:8a3tgj$grp$1@news.cybercity.dk... > > Try to look here: http://www.free-ip.com/cores.htm > > They have a 6502 and a PIC core in VHDL. I never could have imagined the 6502 becoming "freeware" ;-) Has anyone synthesized it into a FPGA just for fun? /**************** * Code Mangler * ****************/ #include <std_disclaimer.h>Article: 21140
> One advantage with the Actel place and route tool is the ability to set > operating voltage and temperature range. You can then check "best" as well > as "worst" case timings. > It will also generate an sdf file with min and max timings so you can > simulate your placed and routed design at "best" and "worst" case timings. > I once > had a design that simulated fine interfacing to external circuitry at > maximum timings but didn't work at minimum timings. Could you please say a bit more. Are you talking about clean digital systems where you just have to meet setup/hold times? How does what you are doing compare to the Xilinx party line that says 0 hold so all you have to do is meet worst case setup? (I think their "0 hold" really means that the min clk to out covers the clock skew.) -- These are my opinions, not necessarily my employers.Article: 21141
> First I'd like to thank you for your very usefull experience report. > Synplify takes about 6 times as long to target the same design to Actel > compared to Xilinx. Reported device usage 85% A14100 (actually pessimistic) > 30% XC4028 (optimistic) > At the time we have 11 Spartan and one Virtex on our protype board. The SX/A-SX Family from actel looks like our "new" target. But its really hard to get a good comperation on gate counts of all these companies. > > > My company usually does one offs so investment in an Actel programmer with > the necessary adaptors was considered uneconomic. Apparently our local Actel > distributor is the biggest provider of programming services in Europe. If > you buy your chips from them they will programme at no extra cost. They are > Gothic Crellon Ltd, tel UK +1189 788878. > the programmer prices are not as high that I can't carry the risk, because if we spend two days with the result that is unusable it's more wasted money and lifetime. > > Kate > > Hans Holm <ff@sigcom.de> wrote in message > news:38C4CFD5.F007E949@sigcom.de... > > Hi folks; > > > > some days ago i tried to start a discussion about experiences with > > antifuse fpgas. > > May be it's been the wrong subject ... > > > > I know two vendors actel and quicklogic. As far as I know, both of them > > are much lower in power consumtion than sram- based fpga's and this is > > exactly what I need. > > We want to replace our digital board with Virtex and SpartanXL with > > antifuse fpga's > > to solve our temperature problem. > > > > We are still in discussion whats better to use > > quicklogic or aldec antifuse FPGAs to replace the xilinx heater. > > > > > > May be someone can give me an any good arguments? > > > > I am interested in following questions: > > > > 1.How are your experiences with unsing sysnopsys and aldec or > > quicklogic? > > > > 2.Did someone ever ported a vhdl- source made for xilinx spartan to any > > of this antifuse devices? Any problems (might have an other timing for > > sure) > > > > 2.5 We want to use synopsis fc2... is it really a good idea? Or should > > we use other eda tools? > > > > 3.How about the eda tool provides by quicklogic and aldec > > > > 4.How many FPGAs has to go until you will hav one workin' > > > > 5.Did someone made experiences with programming services for higer > > values of these devices? > > > > I hope there is someone to find who knows some answers, even if my > > questions are in a rusty english .... > > > > ff > > > > > > > >Article: 21142
Uwe Bonnes schrieb: > Hans Holm <ff@sigcom.de> wrote: > ... > : 5.Did someone made experiences with programming services for higer > : values of these devices? > ... > You might consider Quicklogic's WebAsic program as a (free) programming > services... > > Bye I know it but they have an other service, too. They can produce higher amount of programmed chips. I was looking for experiences with this service if I need 200 times the same one. > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 21143
It was a while back so I don't remember precise details. The A14100 was interfacing with a 25ns static ram, spec'ed over 4.5V to 5.5V, -55C to +125C. One thing we have design and test for is to switch on and function (not necessarily meet spec) at temperature/supply exteremes. In this case it was something like -30C, 5.25V. The timings for the A14100 are easy, they are in the SDF file. The ram chip is not so easy. Often data sheets give a maximum and no minimum or vice versa. When no minimum is given what can you do but assume 0ns? Anyway, IIRC, clock speed was 40MHz (25ns) (+/- a bit over temp), the data out of the ram had been and gone before the FPGA grabbed it as it had moved a whole clock period and the FPGA hadn't changed nearly that much. BTW Actel also quote 0 hold time. Another BTW. If you ever use the high pin count ceramic quad flat packs that need the leads forming and it is going to be subject to vibration, glue the package to the board. The leads are not strong. Hal Murray <murray@pa.dec.com> wrote in message news:8a4v52$qs8@src-news.pa.dec.com... > > > One advantage with the Actel place and route tool is the ability to set > > operating voltage and temperature range. You can then check "best" as well > > as "worst" case timings. > > It will also generate an sdf file with min and max timings so you can > > simulate your placed and routed design at "best" and "worst" case timings. > > > I once > > had a design that simulated fine interfacing to external circuitry at > > maximum timings but didn't work at minimum timings. > > > Could you please say a bit more. Are you talking about clean digital > systems where you just have to meet setup/hold times? > > How does what you are doing compare to the Xilinx party line that > says 0 hold so all you have to do is meet worst case setup? (I > think their "0 hold" really means that the min clk to out covers > the clock skew.) > > -- > These are my opinions, not necessarily my employers.Article: 21144
> > Just to add a little to this, I ran the same P&R on my office > PII-333 (160MB) and a lab PIII-600 (128MB). The P&R times were > almost exactly proportinal to the processor speed. I don't think > I'm memory constrained, though I "found" some 256MB sticks laying > around. Unfortunately they're registered, so they won't do my > office system any good. > > ---- > Keith One more thing I would like to remember (it's about CPUs): It is impossible to speed up Xilinx tools by using two processors on the same UNIX workstation. Xilinx technical support told me that Xilinx executables have not been designed to support multithread procedural programming, so a process (i.e. a PAR run for example) can not be shared among two UNIX CPU processors. The was the case for Sun Ultra-60. Two processors mean two different "hosts" and you came to multipass place&route with nodelist feature. I don't know if it is the same for PCs. AFAIK PCs can have more than one processor on the machine, but I think the processor share is totally dependent upon operating system and the executable that takes the advantage of multithreading (sharing the process -program- into more than one processor). Utku -- I feel better than James Brown.Article: 21145
Hey, why are you not looking at www.open-cores.org? This is a RISC core that resembles a MIPS that fits into a Xinlinx. Regards, Norm Tobin Fricke wrote in message <38C4A852.30EF8B8C@cory.eecs.berkeley.edu>... >I've recently become interested in microprocessor architecture and have >adopted as a personal project to implement a simple processor of some >sort in an Altera FPGA. I'd like to learn about the architectures and >implementations of various processors in use today and from the past. >I'm familiar with the general "big ideas" such as load-store >architectures, accumulator-architectures, etc, but I'd like to see some >real world designs. I'd like to find some information on the early >Intel and Motorola processors; where can I find data on the Intel 4004 >and 8080? How about the Motorola 6800? Is there some book or website >that offers a comparison of various designs? I'm also interested in >seeing a comparison of modern designs, such as x86, Alpha, MIPS, ARM, >PA-RISC, PowerPC, etc. > >Thanks, >TobinArticle: 21146
True enough, but you need to keep it in mind as you do the design. In order to infer the IOB registers, inputs should go only to a register without going through logic. Outputs should have no logic other than a tristate after the output register. Additionally, in order to keep the clock cycle short, outputs should have only very simple logic in front of the register (especially avoid arithmetic) so that the possibly long route leading to the IOB from the internal logic doesn't include combinatorial logic delays too. AFAIK, the xilinx software still doesn't support the tristate register for 4K parts. For Virtex, the xilinx tools automagically push the registers, including the TS registers to the IOBs if the above conditions are met and the use IOB registers is turned on. Phil Hays wrote: > Make utilities: I use the nmake that comes with Microsoft Visual C++. I'm > aware that there are many other make utilities, some of which are clones of Unix > make utilities. > > Ray Andraka wrote: > > > I don't know what your design is, but I kinda suspect you are not registering > > at the IOBs. I push registers into the IOBs whenever I can because it makes > > the external timing independent of the internal implementation. > > If Synplify handles SpartanXL the same as it did the 4000 series, then IOB data > registers are built when possible by default. Check using technology view, or > otherwise look at the results to verify. The tristate enable register was a > special case and I think that it still is. Synplify currently doesn't do this > for Virtex, but it is rumored for next release. > > -- > Phil Hays -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21147
You've got some tools from Viewlogic for Xilinx : In a DOS window For NT users : c:\xilinx\viewlog\data\custmenu.exe xvdrawnt.txt For 95 users c:\xilinx\viewlog\data\custmenu.exe xvdraw95.txt And then you'll have specific tools for Xilinx (for instance to write edif file from your schematic for xilinx implementation tool). "Zhibin Dai" <zdai@uoguelph.ca> a écrit dans le message news: 8a3tt2$qqc$1@testinfo.cs.uoguelph.ca... > Hi, > > I have some questions for WorkView Office and Alliance XACT: > > 1. Can Workview Office generate a .XNF netlist from ViewDraw? I only got > .WIR files. > > 2. I produced a .EDN file from a Schematic by using EDIF tools in WVO. > But when I use it on Alliance XACT to perform mapping, I got a message: > > ERROR:basnu:93 - logical block "$1I30/$1I1" of type "NOR2" is unexpanded. > > I think I missed something. What's wrong? > > > 3. Is there a way to get information like switch consumption, number of > connections and average length of connection in Xilinx tools? > > > I appreciate any advice you provided! > > > > ZhibinArticle: 21148
Hi
>
> I would agree with Peter's comment that the input delay should not be
> the cause of your problem. Also, this delay is only added when you are
> using the input FF in the PIC (IOB in Xilinx terms).
>
> You did not say anything about your design. This is very possibly the
> cause of your problems. By working in VHDL, you may well have a great
> deal of logic in the input or output paths. This is much more likely the
> cause of your problem.
>
> You should be using timing constraints on your design on both internal
> paths as well as input and output paths. Lucent has recently improved
> the utility of the input format for timing constraints so that this is
> much easier to do. I believe that the current version of the back end
> tools (Foundry) is 9.4. I am still using 9.35 which has the same
> capability, but uses an intermediate file for some forms of constraints.
> If you don't have version 9.4, I suggest that you get it. It should be
> much easier to use in this regard.
>
> --
>
> Rick Collins
The logig that is generated in the output and input path is not the
problem.
I got a hint that the given global timing constrains are effecting only
the relevant pathes in the design. Now I have added some timing
constrains also for the input and output pathes and the design is now
running at around 20 MHz.
Thanks again for your help
Harald
---------------------------------------------------------------------------
Harald Simmler Lehrstuhl fuer Informatik V
Universitaet Mannheim
Tel: +49-621-181-2632 ! NEW ! B6, 26
Fax: +49-621-181-2634 ! NEW ! D-68131 Mannheim
eMail: simmler@ti.uni-mannheim.de Germany
Article: 21149[snip] > > They have a 6502 and a PIC core in VHDL. > > I never could have imagined the 6502 becoming "freeware" ;-) > > Has anyone synthesized it into a FPGA just for fun? Yes. Many years ago it was a common benchmark for high end FPGA's and FPGA synthesis software. But it is simply too trivial now (less than 2000 NAND2 equivalent gates). -- Paul W. DeMone The 801 experiment SPARCed an ARMs race of EPIC Kanata, Ontario proportions to put more PRECISION and POWER into demone@mosaid.com architectures with MIPSed results but ALPHA's well pdemone@igs.net that ends well.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z