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Ray Andraka wrote: > > I forgot to mention what is arguably Atmel's strongest point: Atmel's architecture, as > well as the software is well ahead of the rest for doing partial reconfiguration. The > architecture supports it well. I was not aware that Atmel has any special support in the tools. I am pretty sure that no one else supports it in the tools as both Xilinx and Lucent claim that capability in the parts, but then dare you to find a way to use it. > The 40K isn't all that rich in small logic blocks. The 40K cell is basically a 4LUT and > flip-flop, or about a half CLB in 4K if you ignore the H lut and carry stuff. The 4lut > can split into a pair of 3 LUTs to do arithmetic sort of like the altera cell (with the > same problems I've noted here regarding the altera cell for arithmetic apps) If you look > at the number of 4LUTs and FFs, it is not all that great a difference. A 40K20 has > 32x32 cells/registers. compare that with a 4025 which also has 32x32 cells, but it's > cells each have 2 registers, 2 4LUTs, a 3 LUT and a dedicated carry chain. The 4025 > clearly has more than double the logic of a 40K20. A closer comparison is the 4013( > spartan XCS30 ), which is a 24x24 array of these cells or 1152 flip-flops and 4 LUTs and > 576 3 LUTs plus carry chains. > > Years ago I used the Atmel 6K devices in numerous applications that couldn't be touched > with the contemporary xilinx parts, simply because of the large number flip-flops > (AT6010 had an 80x80 array of cells, each with a FF and what amounted to a half adder > with some muxes). Those cells were extremely fast for their time, and the densities > were two or more times the competition. Design was a bit of a bitch though, because the > cell didn't cover all 2 input logic functions, and even fewer 3 input. DeMorgan became > a good friend in those days. I don't miss the long hours of careful hand layout and > permutations of logic to make it all fit. The 40K architecture was at least in part > motivated by the desire to get away from that hand route, but it came at a price of > bigger and slower cells, which meant a lot less of them. The 6K series is what I was familiar with. I didn't realize that the 40K series was so close to the Xilinx parts in function and density. I also remember the way you would need to burn an entire cell to invert one input to a function. Although the speeds per cell were high, the funciton speeds might still be very slow if it needed to run through multiple cells for something simple. But if you could pipeline the functions at a very low level, the many, many FFs would allow the design to run at very high speeds. But that was often a big IF. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 21051
I am a new consultant based on Long Island trying to get some new clients. I have recently become a Xilinx XPERT http://www.xilinx.com/company/consultants/partdatabase/usdatabase/northeast/ ramsden.htm. ). Anyone needing any help out there do not hesitate to call or email myself. Regards, Stan Ramsden -- Stan Ramsden Ramsden Designs 631-956-7720 sramsden@hoflink.comArticle: 21052
Rickman wrote: > Ray Andraka wrote: > > > > I forgot to mention what is arguably Atmel's strongest point: Atmel's architecture, as > > well as the software is well ahead of the rest for doing partial reconfiguration. The > > architecture supports it well. > > I was not aware that Atmel has any special support in the tools. I am > pretty sure that no one else supports it in the tools as both Xilinx and > Lucent claim that capability in the parts, but then dare you to find a > way to use it. > The support Atmel provides is basically for setting and changing constants, but even that is a lot more than what is offered by others. Also if you look at the Virtex architecture, reconfiguration is on a whole column so you need to be cognizant of everything that is going on in that column as well as any routing that crosses the column. Makes for a big headache if you try to partial configuration. Additionally, the xilinx tools do not really have a good way of locking down routes or keeping routes out of areas of silicon, so you are more or less left to hand route if you do partial configuration. The Atmel configuration is done in rectangular windows, the size of which is specified in the reconfiguration stream. That means you really can modify just one cell without affecting the operation of anything else on the chip, and without having to know what is in the cells elsewhere on the chip. I'm not saying their support is stellar...there are still many unanswered problems, but it is miles ahead of the competition. > > > The 40K isn't all that rich in small logic blocks. The 40K cell is basically a 4LUT and > > flip-flop, or about a half CLB in 4K if you ignore the H lut and carry stuff. The 4lut > > can split into a pair of 3 LUTs to do arithmetic sort of like the altera cell (with the > > same problems I've noted here regarding the altera cell for arithmetic apps) If you look > > at the number of 4LUTs and FFs, it is not all that great a difference. A 40K20 has > > 32x32 cells/registers. compare that with a 4025 which also has 32x32 cells, but it's > > cells each have 2 registers, 2 4LUTs, a 3 LUT and a dedicated carry chain. The 4025 > > clearly has more than double the logic of a 40K20. A closer comparison is the 4013( > > spartan XCS30 ), which is a 24x24 array of these cells or 1152 flip-flops and 4 LUTs and > > 576 3 LUTs plus carry chains. > > > > Years ago I used the Atmel 6K devices in numerous applications that couldn't be touched > > with the contemporary xilinx parts, simply because of the large number flip-flops > > (AT6010 had an 80x80 array of cells, each with a FF and what amounted to a half adder > > with some muxes). Those cells were extremely fast for their time, and the densities > > were two or more times the competition. Design was a bit of a bitch though, because the > > cell didn't cover all 2 input logic functions, and even fewer 3 input. DeMorgan became > > a good friend in those days. I don't miss the long hours of careful hand layout and > > permutations of logic to make it all fit. The 40K architecture was at least in part > > motivated by the desire to get away from that hand route, but it came at a price of > > bigger and slower cells, which meant a lot less of them. > > The 6K series is what I was familiar with. I didn't realize that the 40K > series was so close to the Xilinx parts in function and density. I also > remember the way you would need to burn an entire cell to invert one > input to a function. Although the speeds per cell were high, the > funciton speeds might still be very slow if it needed to run through > multiple cells for something simple. But if you could pipeline the > functions at a very low level, the many, many FFs would allow the design > to run at very high speeds. But that was often a big IF. That's what I meant about becoming very friendly with deMorgan. With most functions, there is more than one way to skin the cat. Looking back at my AT6K designs, it is an extremely rare case where I used a cell just as an inverter. I think the bigger problem was the so called color clash problem. Each cell has two local inputs A and B and two local outputs, also A and B. An A output can only connect to the four neighboring cell A inputs, and the B's could only connect to Bs. The problem is the flip-flop is on the A side, and there are many cases where that output has to go to a B input. In the old interact editor (which is much better than the cadence tools for hand crafting) The A routes were red and the B routes were blue...red could only connect to red, hence the term color clash. The cells, for those unfamiliar, are basically half adders with a flip-flop on the sum output (connected to the A output). The carry (B) output is inverted to give a NAND capability, and there are a few extra gates to allow use for some other functions. There is a diagram of the cell on my website under the FPGA vendors section. The neat thing about these devices was the huge number (for their time) of flip flops and the very fast cell speeds. The cell combinatorial delays were about 2ns on early '90's devices. A good design in them took a while though because you needed to try massage almost all the logic to make it really fit well. > > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21053
If the target is the subject of a read or write that cannot be completed, the normal responce is to with terminate without data - ie a retry. The bus master is bound by pci protocol to retry that transfer - and in the PC chipsets I've seen will never time out. The only real solution is to add some code to the target that times out after n retrys and issues a target abort. This is a serious error, but will fix the os hang. mailto:mikej@NOSPAMfreeuk.com (remove NOSPAM of course) Rickman <spamgoeshere4@yahoo.com> wrote in message news:38BE6ECB.EB0397A8@yahoo.com... > Antonio Joaquim A Esteves wrote: > > > > Hello, > > > > We designed a prototyping board with Xilinx FPGAs and a PCI > > interface implemented with the Xilinx LogiCORE 2.0.2 (slave > > only) and a 4013XLT device. > > > > The board has been used, but a problem remain unsolved: > > > > "on faster PCs and/or when using optimized s/w to implement > > read/write operations that access the FPGAs, these operations > > seem not to succeed and in some situations the operating > > system (OS) hangs up". > > > > What makes the OS to hang up when executing a sequence of > > "a writing operation (to send a FPGA configuration > > byte) followed by a read operation (to read FPGA status)" with > > optimized code ? > > The interrupt signal seems not to be asserted ... > > > > Since h/w logic adds long delays, we decided to deassert SREADY > > signal for one state during read operations. Can this cause problems ? > > > > Any ideas will be apreciated. > > Regards. > > > > ----------------------------------------------------- > > Antonio J A Esteves > > Departamento de Informatica - Universidade do Minho > > Largo do Paco - 400-320 Braga Codex - Portugal > > > > Phone: +351 253 604454 Fax: +351 253 604471 > > E-mail: esteves@di.uminho.pt > > Web: http://www.di.uminho.pt/~esteves/ > > ----------------------------------------------------- > > We saw hangups on a board we were designing when the target inboard > logic did not respond to the PCI interface. I don't know exactly what > would appear on the PCI bus, but it seems that the bus master did not > time out waiting for a response. So the OS would hang so hard, that even > the reset button did not work! We would have to cycle power to get the > machine out of lockup. The fix in our case was to identify the bug that > kept the logic from responding. > > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 21054
Ray Andraka <randraka@ids.net> wrote: : Rickman wrote: :> Ray Andraka wrote: :> > I forgot to mention what is arguably Atmel's strongest point: :> > Atmel's architecture, as well as the software is well ahead of the :> > rest for doing partial reconfiguration [...] : The Atmel configuration is done in rectangular windows, the size of : which is specified in the reconfiguration stream. That means you : really can modify just one cell without affecting the operation of : anything else on the chip, and without having to know what is in the : cells elsewhere on the chip. I'm not saying their support is stellar... : there are still many unanswered problems, but it is miles ahead of the : competition. Partial reconfiguration is something I have potential use for - I want to generate designs, evaulate them modify them and then test them in an automated loop. I find that my Atmel board is not likely to be very useful for it, though - since I need to physically disconnect the bitstream download cable and swap a link when switching between program mode and runtime mode ;-| -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com If you're too old to learn, you were born like that.Article: 21055
Ray Andraka <randraka@ids.net> wrote: : The 40K's Achilles heel is the fact it has no fast carry logic. That really : cripples its arithmetic performance/density when compared to Xilinx. If you : don't need a carry chain (unfortunately, I can only think of a few : applications that don't benefit there), it's not all that bad a device. The architechure looks fine to me. I'm planning to simulate cellular automata and finite state machines. I have no need for carry chains - and the fine-grained parallelism seems to match that of the CA I'm simulating. : I truthfully have not looked at their software in a few years. I would hope : that it has been improved. Previously they were using Figaro, which was : dreadfully slow, especially when you tried to do any edits. I think they : still give away the software for free. [...] Figaro lives. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Only users lose drugs.Article: 21056
"Edward Lee" <edlee@seidcon.com> wrote in message news:38BE7A9C.43618B6E@seidcon.com... > Can I use a simpler Jtag cable than the one suggested in Xilinx's web? > Xilinx's cable requires lot of buffers and resistors, which would make the > ISP PCB bigger and more expensive. By the way, I have been programming > Vantis/Mach CPLD's with straight wires from the parallel port. I am > exploring alternative because Vantis/Mach prices went up quite a bit since > Lattice brought it from AMD. Of course you can. I do it for XC95108s, but there are a few things to worry about. First, pulse shape. The series resistors in the Parallel-III cable dampens the reflected wave, saving you from getting double-clocked. Some parallel ports pass out bus noise when you write to them. Get the P3 schematic, cut out the gates in the JTAG datapaths, and you're down to just wires. Pin15 usually has internal pull-up in the port, so the VCC sense circuit is void anyway. When making a cable, use a ribbon cable with every other conductor grounded, and use 100 ohm resistors like in the P3 cable. Won't drive so many devices at once, but it works when you're desperate. Or do like I did - make a plug with an XC9572 once and for all. Emulates every interface I've seen so far. -- /Kasper Pedersen [PGP 0xCAF1E27C, 49B0 F0F1 2A6E AEE8 4AAA 8672 D4B9 5F58 CAF1 E27C]Article: 21057
That's an application where the Atmel architecture is likely to shine. I have an old atmel eval board that has a breadboard area on it. If the new one has such an area, couldn't you put a small PLD on there to take care of the switching for you? Tim Tyler wrote: > Ray Andraka <randraka@ids.net> wrote: > > : The 40K's Achilles heel is the fact it has no fast carry logic. That really > : cripples its arithmetic performance/density when compared to Xilinx. If you > : don't need a carry chain (unfortunately, I can only think of a few > : applications that don't benefit there), it's not all that bad a device. > > The architechure looks fine to me. I'm planning to simulate cellular > automata and finite state machines. I have no need for carry chains - and > the fine-grained parallelism seems to match that of the CA I'm simulating. > > : I truthfully have not looked at their software in a few years. I would hope > : that it has been improved. Previously they were using Figaro, which was > : dreadfully slow, especially when you tried to do any edits. I think they > : still give away the software for free. [...] > > Figaro lives. > -- > __________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com > > Only users lose drugs. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21058
I have a design fully placed and routed using a Virtex 1000 -4 chip. Is
there any way to get timing numbers for the -6 using the exact same
place and route results without rerunning the entire process?
Adam
--
"Intelligence has much less practical application than you'd think."
- Mensa Member to Dilbert
Article: 21059Inside the timing analyzer open the options menu. You'll find a speed grade setting there. "Adam J. Elbirt" wrote: > I have a design fully placed and routed using a Virtex 1000 -4 chip. Is > there any way to get timing numbers for the -6 using the exact same > place and route results without rerunning the entire process? > > Adam > > -- > "Intelligence has much less practical application than you'd think." > - Mensa Member to Dilbert -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21060
Ray,
Thanks much for the info - have one other question. If I want to actually
target the -6 instead of the -4, do I need to rerun bitgen to get the new bit
and msk files or is the same file set good for any speed grade for the same
part?
Thanks.
Adam
Ray Andraka wrote:
> Inside the timing analyzer open the options menu. You'll find a speed grade
> setting there.
>
> "Adam J. Elbirt" wrote:
>
> > I have a design fully placed and routed using a Virtex 1000 -4 chip. Is
> > there any way to get timing numbers for the -6 using the exact same
> > place and route results without rerunning the entire process?
> >
> > Adam
> >
> > --
> > "Intelligence has much less practical application than you'd think."
> > - Mensa Member to Dilbert
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
--
"Intelligence has much less practical application than you'd think."
- Mensa Member to Dilbert
Article: 21061The bit file is good for all speed grades of the same part. No need to re-run anything "Adam J. Elbirt" wrote: > Ray, > > Thanks much for the info - have one other question. If I want to actually > target the -6 instead of the -4, do I need to rerun bitgen to get the new bit > and msk files or is the same file set good for any speed grade for the same > part? > > Thanks. > > Adam > > Ray Andraka wrote: > > > Inside the timing analyzer open the options menu. You'll find a speed grade > > setting there. > > > > "Adam J. Elbirt" wrote: > > > > > I have a design fully placed and routed using a Virtex 1000 -4 chip. Is > > > there any way to get timing numbers for the -6 using the exact same > > > place and route results without rerunning the entire process? > > > > > > Adam > > > > > > -- > > > "Intelligence has much less practical application than you'd think." > > > - Mensa Member to Dilbert > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > -- > "Intelligence has much less practical application than you'd think." > - Mensa Member to Dilbert -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21062
That's the main problem. How do I disable the VCC sensing in the web_pack_jtag programmer? Kasper Pedersen wrote: > Pin15 usually has internal pull-up in the port, so the VCC sense circuit is > void anyway.Article: 21063
Kasper Pedersen <kasper@traceroute.dk> wrote in message news:hsqw4.48$n4.938@news030.image.dk... > Or do like I did - make a plug with an XC9572 once and for all. Emulates > every interface I've seen so far. > What do you exactly mean, and what can it be used for ? I can take a wild guess, but I could be too wrong to make that idea public... greetings, AlainArticle: 21064
I've recently tried to solve the same problem. I've managed to create a
divider which works quite well on the simulator, but I have not yet
implemented it on hardware. Good luck.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity divide is
port ( clck: in STD_LOGIC;
m2:in unsigned(7 downto 0);
m1:in unsigned(7 downto 0);
qout:out unsigned(7 downto 0);
remain:out unsigned(7 downto 0)
);
end divide;
architecture divide_arch of divide is
type state_type is (s0,s1,s2); --s0 = idle
--s1 = subtract divisor if remainder >= divisor
--s2 = increment counter
signal state: state_type;
signal remainder1:unsigned(15 downto 0);
begin
process(clck) --run process whenever clck transitions
variable remainder:unsigned(15 downto 0);
variable divisor:unsigned(7 downto 0);
variable count:integer range 0 to 8;
variable Done:integer range 0 to 1;
begin
if (Done=1) then state<=s0; --goto s0 when division is complete
elsif clck'event and clck='1' then --trigger on leading edge of clck
case state is
when s0 => --idle state
if (Done=0) then state<=s1; --transition to s1 when division is not
complete
divisor(7 downto 0) :=m1(7 downto 0);
remainder(8 downto 1) := m2(7 downto 0);
else
count := 0; --reset counter if division is complete
remainder := "0000000000000000"; --reset remainder if division is
complete
end if;
when s1 =>
if count < 8 then
if remainder(15 downto 8) < divisor(7 downto 0) then
--shift w/o subtracting
remainder(15 downto 1) := remainder(14 downto 0);
remainder(0) := '0'; --set lo bit to 0
else
--subtract divisor
remainder(15 downto 8) := remainder(15 downto 8)-divisor(7 downto
0); remainder(15 downto 1) := remainder(14 downto 0); --shift
remainder(0) := '1'; --set lo bit to 1
end if;
state <= s2;
else
state <= s0;
end if;
when s2 =>
state <= s1; --transition back to state s1
count := count+1; --increment counter
if count >= 8 then
--division is complete when length of dividend (8) is reached
Done := 1;
end if;
when others => null;
end case;
qout(7 downto 0) <= remainder(7 downto 0); --quotient is lower 8 bits
of "remainder"
remainder1 <= remainder;
end if;
end process;
remain(6 downto 0) <= remainder1(15 downto 9); --remainder is top 7
bits of "remainder", shifted rt
remain(7)<='0'; --MSB is zero
end divide_arch;
Steve Brainard
sbrainard@att.net
Antonio Martínez Álvarez wrote:
>
> > Divider is nothing more then a counter with the count vector moved into
> > pins. You need to apply clk and each output will be the division by 2, 4, 8,
> > 16, 32.... It depends on the counter vector only.
> >
> > declare count like:
> >
> > count :buffer std_logic_vector (whatever_you_want to 0);
> >
> > process (clk, reset)
> > begin
> > if reset='1' then
> > count <= (others => '0');
> > elsif clk'event and clk='1' then
> > count <= count + 1;
> > end if;
> > end process;
> >
> > Juliusz
>
> Ok... but I think that it can't divide a non 2 power (2**n, with n
> natural). How can you implement a Integer Divider.
> For example 9 / 2 = 4 and so on...
>
> Thank you !
>
> --
> Antonio Martínez Álvarez, <newton@retemail.es>
> Proyecto Ciencia Libre <http://pagina.de/ciencialibre>
>
> Powered by Linux (Red Hat 6.1)
Article: 21065Greetings - We have some excess QuickLogic inventory up for sale. Please see http://www.gearboxtp.com/for_sale/ql_100144.html http://www.gearboxtp.com/for_sale/ql_208.html http://www.gearboxtp.com/for_sale/ql_base.html thanks - - jesseArticle: 21066
Hi there! In command(console) mode, I want to fpga_synthesys using synplify. (WinNT) HELP reads as following " synplify -batch project.prj" But, in this way, GUI is displayed on screen. Is there any way that don't display GUI. If possible, please help me about Quartus and Foundation. Thanks.Article: 21067
The problem was not the fact that the retry would occur, but rather than it would not occur. The PLX9080 chip did neither a terminate or an abort and the PCI bus master (the PC) would just stop. I don't believe there was any way to add a timeout to the target. I found the problem with the FSM logic and fixed the lockout condition. The other problem we had with that chip was that the local bus side would complete a read, but the data never made it out to the PCI bus. The PCI expert was not really very knowledgeable so I never got any feedback on what was happening there. But this would retry and the local bus would do another read. Since it was a volatile register that was being read, data was lost in the process. We had to change the register so that when the data was received by the host a write cleared the data that was read. In effect a handshake with the software. Good thing this was not a FIFO! mike johnson wrote: > If the target is the subject of a read or write that cannot be completed, > the normal responce is to with terminate without data - ie a retry. The bus > master is bound by pci protocol to retry that transfer - and in the PC > chipsets I've seen will never time out. The only real solution is to add > some code to the target that times out after n retrys and issues a target > abort. This is a serious error, but will fix the os hang. > mailto:mikej@NOSPAMfreeuk.com > (remove NOSPAM of course) -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 21068
why you are going to sell this equipment? we are still in discussion whats better to use quicklogic or aldec antifuse FPGAs to replace our xilinx heater (they are really hot and we dont have enough space for activ cooling) and keeping on the same speed ... May be someone can give me an any good arguments? I am interested in following questions: 1.How are your experiences with unsing sysnopsys and aldec or quicklogic? 2.Did someone ever ported a vhdl- source made for xilinx spartan to any of this antifuse devices? Any problems (might have an other timing for sure) 3.How about the eda tool provides by quicklogic and aldec 4.How many FPGAs has to go until you will hav one workin' 5.Did someone made experiences with programming services for higer values of these devices? I hope there is someone to find who knows the answers, even if my questions are in a rusty english .... ffArticle: 21069
Hi, I want to build a parallel multiplier in a FPGA. Is there any specific method which can be considered as the best option to do it?. I have the software from Xilinx. How difficult is to specify the contents of different LUTs and how easy to use them as a predefined block (if possible, I don't know it) in a greater design?. Thanks. -- __________________________________ qfwfq Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21070
If you puplish your commercial in a new group you product may be discussed. I tried this program and I am sorry but it seem to be buggy. If you use it under non- english windows version you shouldn't change any values otherwise you have to finish it with killing the process. It still does not work under Windows 95/98 NT4.0 and 2000 on non english or us versions. On the other hand its will a great tool if you are going to debug it - because it much easier to use than matlab ... ffArticle: 21071
At the moment I'm using Xilinx XC9500 CPLD's at 5V, but I would like to switch to the XC9500XL family (3.3V). Does anybody have experience how to program them with the Parallel Cable III, which is documented for 5V? Do I have to connect the VCC pin of the cable to 5V or to 3.3V? Thank you very much for every information. -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21072
Parallel cable III (JTAG) will accept 3.3V supply - have a look at Xilinx Answers database 4116 www.xilinx.com/techdocs/4116.htm Klaus Falser <kfalser@durst.it> wrote in message news:8a01r3$g6j$1@nnrp1.deja.com... > At the moment I'm using Xilinx XC9500 CPLD's at 5V, but I would like to > switch to the XC9500XL family (3.3V). > Does anybody have experience how to program them with the Parallel Cable > III, which is documented for 5V? > Do I have to connect the VCC pin of the cable to 5V or to 3.3V? > > Thank you very much for every information. > > -- > > Klaus Falser > > Durst Phototechnik AG > > I-39042 Brixen > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 21073
Andy Peters wrote: > > > 1) Timing constraints. sounds like you might be over-constraining the > design. you may not even be aware of this, because synplicity might be > sitcking its constraints into your xnf (or whatever the result of the > synthesis is). I know that FPGA Express would put an inane number of > constraints into the xnf, so I simply stopped letting it do that. In fact Synplify puts its generated timing constraints for Xilinx parts in a Netlist Control (.ncf) File. These are pulled in & added to the UCF constraints by ngdbuild. In the event of conflict the UCF constraints have priority. Because of similar problems in the past I habitually remove the .ncf between synthesis & layout. This is a shame since this file has the right post-synthesis net names.Article: 21074
1209@my-deja.com wrote: > I heard that Synplicity is for sale and will not IPO. Who do you think > will buy them, Cadence??? > > Sent via Deja.com http://www.deja.com/ > Before you buy. What if its Mentor ?
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