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> Looks like I should go for the new tools. I paid some $15k for the > stuff I have, and recently someone posted a crack for both the > dongles, so I was quite happy to have the investment protected. :) > How do the bugs get found? Do you mean that the design does not work > and there is no indication of why, or does post-route DRC find them? I would go for Xilinx Foundation with FPGA Express - it won't cost anything like $15k. Also, I don't agree that Foundation 2.1i (with service pack 5) is really 'buggy'. > Are the 4000E and EX parts obsolete or just too expensive for what > they do? Xilinx is very slow to make parts obsolete, so if you go with the 4K family you should be ok for years to come, perhaps someone from XLNX (Peter Alfke?) could give you better info. But IMHO you should look carefully at the Spartan, Spartan XL and the Spartan II families. Mark HarveyArticle: 20751
Hi Everybody ! My system consists of only the FPGA (XCS10-5PC84C) configurated via serial Slave interface using a .bit file from Xilinx Foundation 2.1i. I m really unable to configurate it since INITsignal always fall down before the end of configuration process. Is there any wellknown problem with these XCS10-5PC84C? Does anybody can provide me an example of .bit file just to test it ? Thanks, Alain alain.broisin@free.frArticle: 20752
<dave_admin@my-deja.com> wrote in message news:88pa34$li2$1@nnrp1.deja.com... > Hi, > > Does anybody have a HDL source of 32 or 16-bit divider ? > Smaller but parameterized dividers are also welcome. Divider is nothing more then a counter with the count vector moved into pins. You need to apply clk and each output will be the division by 2, 4, 8, 16, 32.... It depends on the counter vector only. declare count like: count :buffer std_logic_vector (whatever_you_want to 0); process (clk, reset) begin if reset='1' then count <= (others => '0'); elsif clk'event and clk='1' then count <= count + 1; end if; end process; JuliuszArticle: 20753
Ray Andraka wrote: > The E and EX are not obsolete...yet. They are the oldest families still > sold though. > Well, we still sell XC3000 and XC3100 parts that were being introduced when I joined Xilinx twelve years ago. Xilinx is very reluctant to obsolete parts, especially since we often benefit from the non-availability of other manufacturers' dedicated devices, that then get ported to our FPGAs. We did obsolete the 14-year old XC2000 family, though. I would agree that XC3000 should not be used for new designs, and XC4000E is more expensive than Spartan. More to the point: For new designs, 5-V technology does not make any sense. 3.3-V devices are faster, cheaper, bigger, consume less power, and have a much longer future. And big devices use 2.5 and 1.8 V, with 1.5 and 1.3 V lurking around the corner. Lower supply voltage is needed for the smaller geometries and thinner gate oxides that bring you faster speed and lower cost, and it also saves power, dramatically. Peter Alfke, Xilinx ApplicationsArticle: 20754
Mark Harvey wrote: > > Looks like I should go for the new tools. I paid some $15k for the > > stuff I have, and recently someone posted a crack for both the > > dongles, so I was quite happy to have the investment protected. :) > > How do the bugs get found? Do you mean that the design does not work > > and there is no indication of why, or does post-route DRC find them? > > I would go for Xilinx Foundation with FPGA Express - it won't cost > anything like $15k. Also, I don't agree that Foundation 2.1i (with service > pack 5) > is really 'buggy'. You apparently haven't pushed the floorplanner or mapper very hard! If you don't do any placement, you won't see the majority of the bugs I've seen. > > > > Are the 4000E and EX parts obsolete or just too expensive for what > > they do? > > Xilinx is very slow to make parts obsolete, so if you go with the 4K family > you > should be ok for years to come, perhaps someone from XLNX (Peter Alfke?) > could give you better info. But IMHO you should look carefully at the > Spartan, Spartan XL > and the Spartan II families. If I were interested in a 4KE for a new design, I'd go for the spartan. You get the same function, better performance, and less power for a lower price. You give up a few minor things that you probably wouldn't be using anyway: async mode of the CLB RAM, wide edge decodes, some of the (the parallel ones) configuration modes. > > > Mark Harvey -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20755
I think he was looking for circuit that does an arithmetic division rather than a frequency divider. Juliusz wrote: > <dave_admin@my-deja.com> wrote in message > news:88pa34$li2$1@nnrp1.deja.com... > > Hi, > > > > Does anybody have a HDL source of 32 or 16-bit divider ? > > Smaller but parameterized dividers are also welcome. > > Divider is nothing more then a counter with the count vector moved into > pins. You need to apply clk and each output will be the division by 2, 4, 8, > 16, 32.... It depends on the counter vector only. > > declare count like: > > count :buffer std_logic_vector (whatever_you_want to 0); > > process (clk, reset) > begin > if reset='1' then > count <= (others => '0'); > elsif clk'event and clk='1' then > count <= count + 1; > end if; > end process; > > Juliusz -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20756
> Divider is nothing more then a counter with the count vector moved into > pins. You need to apply clk and each output will be the division by 2, 4, 8, > 16, 32.... It depends on the counter vector only. > > declare count like: > > count :buffer std_logic_vector (whatever_you_want to 0); > > process (clk, reset) > begin > if reset='1' then > count <= (others => '0'); > elsif clk'event and clk='1' then > count <= count + 1; > end if; > end process; > > Juliusz Ok... but I think that it can't divide a non 2 power (2**n, with n natural). How can you implement a Integer Divider. For example 9 / 2 = 4 and so on... Thank you ! -- Antonio Martínez Álvarez, <newton@retemail.es> Proyecto Ciencia Libre <http://pagina.de/ciencialibre> Powered by Linux (Red Hat 6.1)Article: 20757
Ray Andraka wrote: > > Mathew Wojko wrote: [ ... debate deleted ... ] Ray, Mathew -- can I suggest a contest? It would settle the argument (probably in fewer lines of text ;-), and be highly educational for the rest of us! MarkArticle: 20758
Hi, I am targeting a Verilog design to Xilinx Virtex xcv1000 device. The M1 (Xilinx P&R tool) allow me to define multi cycle timing constrains for a path from specific FF (or PORT) to another FF (or PORT) . As far as I know Synplify supports only FROM FF (or PORT) TO FF (or PORT) multi cycle timing constrains (NOT for specific path). When I tried to define the constrains in Synplify (using Synplifys format) the M1 seemed to ignor them. Did anyone ever bumped into this problem ? Thanks in advance, ----------------------------------------------- Rotem Gazit mailto:rotemg@mysticom.com MystiCom LTD. http://www.mysticom.com ----------------------------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20759
Hi, I am targeting a Verilog design to Xilinx Virtex xcv1000 device. The M1 (Xilinx P&R tool) allow me to define multi cycle timing constrains for a path from specific FF (or PORT) to another FF (or PORT) . As far as I know Synplify supports only FROM FF (or PORT) TO FF (or PORT) multi cycle timing constrains (NOT for specific path). When I tried to define the constrains in Synplify (using Synplifys format) the M1 seemed to ignor them. Did anyone ever bumped into this problem ? Thanks in advance, ----------------------------------------------- Rotem Gazit mailto:rotemg@mysticom.com MystiCom LTD. http://www.mysticom.com ----------------------------------------------- Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20760
In article <88pa34$li2$1@nnrp1.deja.com>,
dave_admin@my-deja.com wrote:
> Hi,
>
> Does anybody have a HDL source of 32 or 16-bit divider ?
> Smaller but parameterized dividers are also welcome.
>
> regards,
> Dave.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>
Here is an implementation in Verilog. It has been
borrowed from a C implemrntation, so there are
places where you can compact the code. Also I have
not tested it extensively, nor did I try
to synthesize it, so you may get some
surprizes there. A signed version of the algorithm
(in C) is also available from the same site :
http://www.bearcave.com/software/divide.htm
Good luck!
- Swapnajit.
module unsigned_div_module;
/*
Author: Swapnajit Mittra
This is a simple unsigned division algorithm
implemented in Verilog. This has been translated
from a C implementation originally done by Ian
Kaplan. His copyright notice is given below.
This Verilog program is being dedicated to
the Verilog community for free use, further
development and improvement.
[Copyright stuff of Ian Kaplan:
Use of this program, for any purpose, is granted the author,
Ian Kaplan, as long as this copyright notice is included in
the source code or any source code derived from this program.
The user assumes all responsibility for using this code.
Ian Kaplan, October 1996]
*/
reg [31:0] numer, denom, remai, quoti;
parameter N = 32;
initial begin // {
numer = 32'h8;
denom = 32'h2;
unsigned_divide(numer, denom, quoti, remai);
$display("quotient = %h, remainder = %h", quoti, remai);
$finish;
end // }
task unsigned_divide;
input [N-1:0] dividend;
input [N-1:0] divisor;
output [N-1:0] quotient;
output [N-1:0] remainder;
integer num_bits, i;
reg [N-1:0] d, t;
reg bit, q;
begin // {
remainder = 'h0;
quotient = 'h0;
if (divisor == 'h0) begin // {
quotient = 'h0;
remainder = divisor + 'h1; // error case
end // }
else if (divisor > dividend)
remainder = dividend;
else if (divisor == dividend)
quotient = 'h1;
else begin // {
num_bits = N;
while (remainder < divisor) begin // {
bit = dividend >> (N-1);
remainder = (remainder << 1) | bit;
d = dividend;
dividend = dividend << 1;
num_bits = num_bits - 1;
end // }
/* The loop, above, always goes one iteration too far.
To avoid inserting an "if" statement inside the loop
the last iteration is simply reversed. */
dividend = d;
remainder = remainder >> 1;
num_bits = num_bits + 1;
for (i = 0; i < num_bits; i = i + 1) begin // {
bit = dividend >> (N-1);
remainder = (remainder << 1) | bit;
t = remainder - divisor;
q = !(t >> (N-1));
dividend = dividend << 1;
quotient = (quotient << 1) | q;
if (q) remainder = t;
end // }
end // }
end //
endtask // unsigned_divide
endmodule // unsigned_div_module
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20761You need to use syn_keep along the path so that synplicity doesn't synthesize out any of the names. rotemg@mysticom.com wrote: > Hi, > > I am targeting a Verilog design to Xilinx Virtex xcv1000 device. > > The M1 (Xilinx P&R tool) allow me to define multi cycle timing > constrains for a path from specific FF (or PORT) to another FF (or > PORT) . > As far as I know Synplify supports only FROM FF (or PORT) TO FF (or > PORT) multi cycle timing constrains (NOT for specific path). > > When I tried to define the constrains in Synplify (using Synplifys > format) the M1 seemed to ignor them. > > Did anyone ever bumped into this problem ? > > Thanks in advance, > > ----------------------------------------------- > Rotem Gazit > mailto:rotemg@mysticom.com > MystiCom LTD. > http://www.mysticom.com > ----------------------------------------------- > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20762
> Since creating a completelly digital DPLL in an FPGA looks to be > quite difficult, what about creating a hybrid PLL where only the > voltage-controlled oscillator would be external (analog) and the rest > (phase detector, loop filter and divide-by-N) would be designed in the > FPGA? The output of the filter is an analog voltage that controls the VCO. I don't think that will be easy to generate in an FPGA. I suggest you get out some data sheets or surf the web and see what you can find. The PLL chips usually include the phase detector and directions for the filter. Doing the divide in an FPGA makes sense. Anything more seems like asking for trouble. -- These are my opinions, not necessarily my employers.Article: 20763
> Do you think external timing can produce this symmetric cases? Nothing > is impossibel, sure, but it doesn't strike me as the most likely > cause. I was just tossing an idea over the fence. I don't undersand you system well enough to make solid suggestions. I'm just hoping that something I say might trigger an idea. One suspicious area is the connections between the FPGA and the rest of the world. If you can make something that runs all of that logic just like the real system you will (probably) learn something. If that setup fails, then you don't have to look at any of the stuff you ripped out. If you have complicated logic inside the FPGA, say crossing timing domains, then I'd try ripping out all the "processing" type logic and see if it works or still fails. If it fails, you have lots of room to build bear traps. If it works, then you get to add back pieces until it breaks. -- These are my opinions, not necessarily my employers.Article: 20764
> I would like to hear from users who find Xilinx FPGA hardware documentation > difficult to understand or confusing. > We can fix that ! I didn't have much trouble with the configuration area. It is complicated and there are many details that all have to come together. But once you get the idea it all makes sense. Maybe there should be a warning so that people expect to read that area several times - and read the text in the pin descriptions a few times too. The simple case is loading from a serial ROM. Isn't there a picture for that? Loading from a uP isn't much different - you just have to make the clock signal too. > The uP: Xilinx config process turned out to be really clean and simple... > once we figured it out! We had to write a few of our own rom-build > utilities, which, in my opinion, Xilinx should have furnished. I was happy once I found the rbt (raw bits) format and noticed that it matched perfectly with one of the pictures in the book describing the format of bits that the chip expects. I have enough software background that writing that sort of code is not something I worry about. I'd rather have good documentation of the signals and data formats rather than code that I have to reverse engineer and/or debug. -- These are my opinions, not necessarily my employers.Article: 20765
Mark Summerfield wrote in message <38B05C41.1E926069@ieee.org>... >Ray, Mathew -- can I suggest a contest? It would settle the argument >(probably in fewer lines of text ;-), and be highly educational for the >rest of us! >Mark Could you also compare with the vendor optimised version e.g. LogiCore, because they should have sorted out all these issues. Also Synthesis tools (at least Leonardo) decodes 'c = a*b' and then several 'c' registers as a pipelined multiplier. They are said to insert the vendor optimised core if they cannot do a better job, so you have two large companies optimising the multiplier for the device and pick up the best solution automatically. Andrew InceArticle: 20766
You need to use "syn_keep" only if you use the "through" directive. I used only TO and FROM. Regards Rotem. In article <38B09A46.B9046F5C@ids.net>, Ray Andraka <randraka@ids.net> wrote: > You need to use syn_keep along the path so that synplicity doesn't > synthesize out any of the names. > > rotemg@mysticom.com wrote: > > > Hi, > > > > I am targeting a Verilog design to Xilinx Virtex xcv1000 device. > > > > The M1 (Xilinx P&R tool) allow me to define multi cycle timing > > constrains for a path from specific FF (or PORT) to another FF (or > > PORT) . > > As far as I know Synplify supports only FROM FF (or PORT) TO FF (or > > PORT) multi cycle timing constrains (NOT for specific path). > > > > When I tried to define the constrains in Synplify (using Synplifys > > format) the M1 seemed to ignor them. > > > > Did anyone ever bumped into this problem ? > > > > Thanks in advance, > > > > ----------------------------------------------- > > Rotem Gazit > > mailto:rotemg@mysticom.com > > MystiCom LTD. > > http://www.mysticom.com > > ----------------------------------------------- > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20767
In article <38A74BB5.39065BB7@earthlink.net>, palfke@earthlink.net wrote: > > > John Larkin wrote: > > > <snip>We did this work a couple of years ago, so we didn't have the 1999 > > book. Frankly, what we did have in the way of documentation was very > > badly written and quite confusing, both the databooks and appnotes. We > > spent a *lot* of hours getting everything to work. I hope things are > > better now. > > > > Ouch, that hurts, since I was the one writing most of this stuff. > Anyhow, I am a grown boy and can stand criticism. > But, to turn this into something positive: > I would like to hear from users who find Xilinx FPGA hardware documentation > difficult to understand or confusing. > We can fix that ! > > Peter Alfke, Xilinx Applications > e-mail: peter@xilinx.com > > Stop using that really, really slow dynatext system. I have no idea what value it EVER added to your documentation. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20768
Following the announcement of a new distribution agreement between Concept Engineering GmbH and EuroEDA Limited, the GateVision design visualization toolset is now available from EuroEDA. GateVision is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing and design documentation. GateVision produces easy-to-read schematics and fits seamlessly into any EDA design environment where data is stored in either Verilog or EDIF netlist format. GateVision is available for Win95/98/NT, Solaris, HP-UX or Linux. Email info@euro-eda.com for more information, or visit our web site at http://www.euro-eda.com to download an evaluation copy. -- EuroEDA Limited Phone: +44 (0)1933 676373 Fax: +44 (0)1933 676372 Email: info@euro-eda.com Web: http://www.euro-eda.comArticle: 20769
One would think the vendor supplied cores were optimal, but they are not always. That is beside the point of 'optimal for what'. For example, I know how to make the xilinx logiccore multiplier for 4K series about 20% faster at the cost of an additional column in the placed macro. The virtex multiplier is harder to speed up because of the way the special purpose hardware is connected (it can still be accelerated, but it takes more area, and has less of a return). Another point is that the cores don't always have all the flavors you might need in terms of signed vs unsigned on each input and bit widths. I guess the point is go ahead and use the cores, but if you are looking for maximum performance at least examine the core to see if it is really optimal for YOUR application. A contest? sounds intriguing, but I'd like to see some return on my time spent. Maybe if one of the magazines framed it as a feature. EDN, you out there? Andrew Ince wrote: > Mark Summerfield wrote in message <38B05C41.1E926069@ieee.org>... > >Ray, Mathew -- can I suggest a contest? It would settle the argument > >(probably in fewer lines of text ;-), and be highly educational for the > >rest of us! > >Mark > > Could you also compare with the vendor optimised version e.g. LogiCore, > because they should have sorted out all these issues. > Also Synthesis tools (at least Leonardo) decodes 'c = a*b' and then several > 'c' registers as a pipelined multiplier. They are said to insert the vendor > optimised core if they cannot do a better job, so you have two large > companies optimising the multiplier for the device and pick up the best > solution automatically. > > Andrew Ince -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20770
Ah, you are correct. My mistake. (Yuck, crow tastes kinda nasty). gazit@my-deja.com wrote: > You need to use "syn_keep" only if you use the "through" directive. > I used only TO and FROM. > Regards > > Rotem. > > In article <38B09A46.B9046F5C@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > You need to use syn_keep along the path so that synplicity doesn't > > synthesize out any of the names. > > > > rotemg@mysticom.com wrote: > > > > > Hi, > > > > > > I am targeting a Verilog design to Xilinx Virtex xcv1000 device. > > > > > > The M1 (Xilinx P&R tool) allow me to define multi cycle timing > > > constrains for a path from specific FF (or PORT) to another FF (or > > > PORT) . > > > As far as I know Synplify supports only FROM FF (or PORT) TO FF (or > > > PORT) multi cycle timing constrains (NOT for specific path). > > > > > > When I tried to define the constrains in Synplify (using Synplifys > > > format) the M1 seemed to ignor them. > > > > > > Did anyone ever bumped into this problem ? > > > > > > Thanks in advance, > > > > > > ----------------------------------------------- > > > Rotem Gazit > > > mailto:rotemg@mysticom.com > > > MystiCom LTD. > > > http://www.mysticom.com > > > ----------------------------------------------- > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20771
Ray Andraka wrote in message <38AF4D8A.8F9F0EF@ids.net>... >My understanding of the terminology is behavioral just emulates the function. >while RTL also carries some information about the structure (namely the >locations of the registers and the logic between them). For example, one could >do a behavioral model of a pipelined multiplier by using the * operator plus a >series of clock delays to match the pipeline length. I was taught that a Behavioral model did not normally include clocks. Instead it should work at the abstract function level, and hence be faster to design and simulate. This is not apropriate for most of our modeling, where like many others the behavior of delay and clocked interfaces also require to be modeled. > An RTL description would >describe, at least in high level terms, the logic between each of the pipeline >stages. But like most VHDL design techniques, your RTL code is almost obsolete. The Synthesis tools (e.g. Leonardo) now recognise the Behavioural Model' code you describe and infer an optimised multiplier design for your device. Device Vendors have spent far longer than most users optimising their multiplier cores for their device, and the Synthesis vendors replace them if they can do better. So for most users there is only one set of VHDL. Andrew InceArticle: 20772
Ray Andraka wrote: > > For all of you who have been asking, and those who wanted to know but > were afraid to ask, I have finally gotten a page explaining distributed > arithmetic up on my website. And for those who don't have a clue what > I'm talking about, distributed arithmetic is a hardware technique that > lets us hide lots of multipliers in an FPGA. Take a look and let me > know what y'all think. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka I'm working on it. Like a map in a dream, so far it seems to make sense but be just out of reach. I'll go back over it a few more times. Thanks for all the nice stuff. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20773
Andrew Ince wrote:
> I was taught that a Behavioral model did not normally include clocks.
> Instead it should work at the abstract function level, and hence be faster
> to design and simulate.
That is what I was aware of, too, although I have not used behavioral software.
For example, if one needed two numbers divided by a certain time, that was what
was input to the compiler and it figured out how to allocate the logic per clock
period, if multiple clock periods were used. The user did not have to maintain
the logic between clocks, it is automagically done, and hence the power of that
technology.
I have no hands on experience with this technology, perhaps some one else can
pipe in (John Cooley can perhaps provide some good perspective), but here's a
chart I found on Synopsys' www site, as I know that they have a behavioral
compiler product.
http://www.synopsys.com/products/beh_syn/what_is.gif
> >An RTL description would
> >describe, at least in high level terms, the logic between each of the
> pipeline
> >stages.
>
> But like most VHDL design techniques, your RTL code is almost obsolete.
> The Synthesis tools (e.g. Leonardo) now recognise the Behavioural Model'
> code you describe and infer an optimised multiplier design for your device.
>
> Device Vendors have spent far longer than most users optimising their
> multiplier cores for their device, and the Synthesis vendors replace them if
> they can do better.
> So for most users there is only one set of VHDL.
I have gone through a fair amount of vendor and synthesizer code and I would
hesitate in calling things (like schematics) obsolete (a general soap-box
argument here) or even RTL-level code. In some cases I have found that vendor
supplied or generated code is well-optimized and takes maximum advantage of the
architecture - a really good logic designer who knows the ins and outs of the
architecture was given enough time to do a good job. In those cases one just
presses the button and sits back, sips the Diet Coke, and watches the characters
scroll by on the screen. In other cases, the human designer can easily
outperform the machine generated version since the good human designer has an
expandable array of knowledge about architecture, algorithms, and techniques,
along with knowledge of the problem or the synthesis algorithms just do a poor
job. In some instances where a synthesizer can do a good job, a weak spot in
the synthesizer logic is hit and the size of the generated code grows rather
large. Synthesizers can be very sensitive to data input or other parameters,
for a fixed function (*). In other cases, the synthesizer may produce code that
is simply unacceptable, as the optimizations that the vendor uses produces poor
circuits (i.e., lockup states, flip-flop replication) (**) from the point of
view of the design engineer; they may be good results with respect to the
marketing and sales departments, however, as on the surface they appear good.
Sorry about the bit of a rant, but it is a bit scary when people call methods
"obsolete" or "almost obsolete" and more and more control is taken away from the
design engineer, giving him only an abstract method of accessing the hardware,
the current trend. I believe that that can be a mistake when a design needs to
be optimized, either for area, performance, or reliability.
Anyways,
Have a good day,
rk
Two papers from MAPLD 1999 cover these topics:
(*) "Reconfigurable, System-on-Chip, High-Speed Data Processing and Data
Handling Electronics"
(**) "Logic Design Pathology and Space Flight Electronics"
Article: 20774In article <88kd2t$iqc$1@nnrp1.deja.com>, Bill Kury <wjk@datum-telegraphic.com> wrote: > Hi! I am looking for a good reference book on advanced digital design. > The subjects that I am interested in are multiplier design, > asynchrounous state machines, etc. If anyone has any recommmendations, > please drop me a note. I too, am interested in a book like this. However, I've never seen any decent book, and no one I've talked to has mentioned one. We need something that is 'equivalent', to the various Engineering Handbooks available for Aerospace, Analog electronics (Art of Electronics, S&S), and even computer systems (Numerical Recipes). Isn't the IEEE a group that should be publishing something like this? SAE, AIAA and the Civil Societies produce handbooks and guides for their fields. Maybe I'm not looking in the right spot. Joshua Lamorie Systems Designer Sent via Deja.com http://www.deja.com/ Before you buy.
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