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hi, thanks, maybe I did not constraint the design correctly, I will check the constraint again. So I assumed that the timing Analyzer should be correct, it give the worst case timing. correct me if I am wrong, to me it seem impossible to find out which path have not meet timing once the design is downloaded, so all the timing violation have to be resolve before the it is download to the fpga. thanks. Sheau Pyng > ---------- > From: Ray Andraka[SMTP:randraka@ids.net] > Posted At: Wednesday, January 19, 2000 2:52 PM > Posted To: comp.arch.fpga > Conversation: Need advice on timing problem > Subject: Re: Need advice on timing problem > > Are you sure you got all the paths covered with the timing > constraints? Run > the timing analyzer and confirm you results there. Also, make sure > you are > meeting timing with the external interfaces. A common place to have > problems is in an FPGA to memory interface. The i/o timing isn't > covered by > a period constraint. > > Oh Sheau Pyng wrote: > > > hi, > > I have problem running a design at the max frequency recommended > in > > the Timing analyse report. > > the s/w is foundation series 2.1, target is Virtex -4 bg560, the > > function of the design is image processing > > > > The report give a min period of 29.222ns , but when i downed the > > design into the virtex and clock it at 33.33ns , 30 mhz > > some of the output image is wrong, ( white dot/pixel can be seen > at > > the resultant image). > > > > When i reduce the frequency to.. say 400K hz , the resultant image > is > > Ok. > > > > So i deduce that it must be because of timing violation. > > > > just like to know, how to you'll solve this ? > > at 30 mhz, it is already ~10% slower than the reported worst case. > but > > it still didn't work. > > is this normal, or i should have clock it at ~20% slower then > > reported, which is 36ns,27.7mhz? > > > > next, when the design have timing violation at run time, is there > any > > way to know which path is causing the problem by probing or some > > measure. or is it alway the path/paths reported by the timing > analyzer.? > > > > thanks > > Sheau Pyng > > > > Project Officer > > > > Center for High Performance Embedded System > > Nanyang Technological University, > > School Of Applied Science > > N4-B3b-06, Nanyang Avenue > > Singapore 639798 > > > > Tel : (65)-790 6967 > > Fax : (65)-7926559 > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > >Article: 19951
> agreed, a random number generator certainly isn't cryptographically, or even > statistically, secure simply because it's confusing to the designer. People > have lost wars making that assumption. But as a source of truly random > addresses for, say, networking applications, something like this is useful > without the hassle of zener noise-diode things and such. Stirring an async > clock into a pseudorandom shift register can be a nice way to 'spread out' > the available randomness, and viewed as random state jumps in the PRN > sequence, is not totally idiotic. I didn't mean to use a word like "idiotic" - appologies if what I said came across that way. I can't think of a case where I would want to stir things up. Do you have a good example? I think I'm asking for a problem with the following properties: You need some random numbers. An LFSR isn't good enough. An LFSR with stirring (via async clock) helps significnatly. -- These are my opinions, not necessarily my employers.Article: 19952
I'm having a problem in Modelsim PE 5.3c with a signal not taking an
assignment inside a generate statement. I see the signal (dini(*))
passed into generate_S0 and generate_S1 if I assign dummy signals IN02
and IN13, however, the value is not transferred to DQ(0) and DQ(1).
Those are stuck with 'U' values. As an interesting aside, I noticed
that the lines that should be assigning DQ(0) and DQ(1) are not
highlighted as executable lines in the modelsim source code listing,
which I though was a little strange.
This part of the code simulates fine in Aldec's Active VHDL, and
synthesizes to what I expect under synplicity. (Unfortunately, I can't
use Aldec for the whole project because the target has extensive
testbenches and scripts that would take to long to modify to run under
Aldec).
I've attached a snippet of the offending code. Any clues to workarounds
would be greatly appreciated. I'm hoping it is just late and I missed
something obvious, but it sure isn't being obvious to me. I've also
contacted modelsim tech support, but have not heard back from them.
Dini is toggling, as is in02 and in 13, but dq(0) and dq(1) are stuck at
'U'.
dini(0)<=din(0); -- +I input
dini(1)<=din(1) xor cyq(channels); -- -Q input
dini(2)<=din(2) xor cyi(channels); -- -I input
dini(3)<=din(3); -- +Q input
--
--
--
S:for filt in 0 to 1 generate --0 for I filter, 1 for Q filter
constant ntaps: natural:=(coefs'length+1)/2-filt;--filt=0 for I, 1 for
Q
constant last: natural:= ((ntaps-1)mod 8)+1;--number of taps in last
section
constant dqlen: natural:=((ntaps+7)/8)*8;--length of delay queue (taps
rounded up to multiple of 8+2)
constant luts: natural:= dqlen/8;
signal dq:std_logic_vector(0 to dqlen+3); --internal delay queue
connections
signal ps:ps_type(0 to luts);--filter partial sums
signal in02:std_logic;
signal in13:std_logic;
begin
------------------------------------------------------------------------------------------------------------------------------------------------------------------
--dq(0) and dq(1) are retaining the 'U' value, even though in02 and in13
successfully take on the values of dini(*).
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
in02<= dini(filt); --connect inputs off commutator
in13<= dini(2+filt);
dq(0)<= in02;
dq(1)<= in13;
-- dq(0)<= dini(filt); --connect inputs off commutator
-- dq(1)<= dini(2+filt);
dq(dqlen/2+2)<=dq(dqlen/2 + (ntaps mod 2)); --loop back connection
:twist if ntaps odd
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 19953For someone new to Xilinx. I am planning to use a XC9572 PLD using the online Web compiler and fitter - using VHDL source code. Does anyone know how to embedd my pin allocation details into the VHDL source. Thanks AnthonyArticle: 19954
I guess one always needs some hardware - either in an FPGA or external. But essentially the cheapest (although the component count is up) is to externally loop back the FIFO output to the input when ever the FIFO is not being re-loaded with a new pattern. For an 8 bit FIFO this is a single tristate buffer or a mux. Austin Franklin wrote in message <01bf62cc$88db5830$207079c0@drt1>... >I know this isn't REALLY an FPGA question, but there are a LOT of bright >people here..so I figured I'd ask. > >I am looking for an 8k x 32 FIFO (minimum) that I can load up with data of >arbitrary length, then free-run it so it just keeps outputting data, >looping on the data that is in it, without having to re-load it. > >Any ideas? >Article: 19955
Gee, A quick search of support.xilinx.com found: Xilinx Answer #6136 : 1.5i: 5200/Spartan/4000E/4000XL/4000EX/4000/4000L Registers are not working properly when device is configured through JTAG http://support.xilinx.com/techdocs/6136.htmArticle: 19956
i'm looking for a PLD which can support Hot-swap. It'll be used in a CPCI board, and should not disrupt the system when plugging it in a working system. I'm now using Alters's 7128AETC100, who can tell me what is the proper choice? Please send the answer to me directly 'cos i don't access the newsgroup often.Article: 19957
Austin Franklin (austin@da33rkroom.com) wrote: : Be aware that copyright is entirely different than patent. If you find a : copy of my schematic, and decide to re-enter it, and use it, with no or : 'little' change, you are violating my copyright (assume the original was : properly marked as such). This has been the subject of several threads in discussions of extending free software licenses to hardware designs. There seems to be a lot of uncertainty about what a 'little' change is. I realise this is another 'how long is a piece of string question' - but is the feeling that the amount of work needed to make more than a 'little' change is fundamentally different from the amount of work needed to make more than a 'little' change in software? People have suggested in the past that it is, making copyright on schematics an extremely weak instrument, but I'm not sure on what grounds. Is there any relevant case law? GrahamArticle: 19958
Hi,
I am interested in the implementation of indexing memory in hardware
(custom or FPGA).
The problem is the following:
say we have inputs a0,a1
and a0 (a 5-bit-vector) can have 19 different values and
a1 (also 5-bit) can have 21 different values.
We need to address a memory with binary addresses.
Hence we could concatenate both vectors and needed 1K memory words.
However we also could combine both inputs to a 9-bit-vector
and save half of the memory.
Of course we can compute the index to the memory as
21*(a0)+a1 or something like that.
Since it is irrelevant how the values are aranged in the memory (we only
address via the indexing funtion), there might be something much
smaller.
Another frequent situation is where
a0 takes values from 1 to some m-1
and a1 0 to a0-1 (a1 is always smaller than a0).
In SW one could use a1+(a0*(a0+1)/2).
But in HW the sqaring might not be worth the saving of memory.
Are there any general techniques for this kind problems?
Publications?
Andreas
-----------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 19959Hi, Actel SX-A is hot swappable. See http://www.actel.com/products/antifuse/sx-apib.html#hot-swapping I don't know about any other models but am interested in that feature. Additionally, there are a number of buffers that are designed for this purpose. I'm sorry that you don't access the newsgroup often, it is sort of a nice crowd. The message traffic is fairly moderate, so I will post the reponse here, as it's a relevant topic. Since you are asking people to do some work for you, I don't think it's that much trouble for you to read in 20 or so headers a day for a few days. Have a nice day, ---------------------------------------------------------------------- rk The world of space holds vast promise stellar engineering, ltd. for the service of man, and it is a stellare@erols.com.NOSPAM world we have only begun to explore. Hi-Rel Digital Systems Design -- James E. Webb, 1968 ============================================ Steele Chen wrote: > i'm looking for a PLD which can support Hot-swap. It'll be used in a CPCI > board, and should not disrupt the system when plugging it in a working > system. I'm now using Alters's 7128AETC100, who can tell me what is the > proper choice? > Please send the answer to me directly 'cos i don't access the newsgroup > often.Article: 19960
Ray Andraka wrote: > If you are looking for a FIFO device to do that, use the retransmit feature > that is present on many FIFOs. You do have to do a reset of the FIFO before > you load your data so that the retransmit starts at the right place. > > If this is to go with an FPGA, then it would be cheaper and easier to use an > SRAM with the FPGA and have the FPGA take care of loading then 'looping' on > the data in it. > > Austin Franklin wrote: > > > I know this isn't REALLY an FPGA question, but there are a LOT of bright > > people here..so I figured I'd ask. > > > > I am looking for an 8k x 32 FIFO (minimum) that I can load up with data of > > arbitrary length, then free-run it so it just keeps outputting data, > > looping on the data that is in it, without having to re-load it. > > > > Any ideas? Hi, I've done this application before and the method I used was to use a Read-Donotmodify-Write operation. That is, first reset and load up the FIFO with the pattern you want. Then, after each read operation, just write it back in on the other side. When using the re-transmit feature, I have found it simplest to make use of the extra bit often present to act as a sentinel. With the first method, you can still program in a '1' in any extra bits that you have which give you a nice test/monitor point. I've also used the discrete SRAM (actually it took 176 of them!) technique, which was a bit more work, and prior to the invention of FPGAs and VHDL. For the geezer crowd, that was for a total of 88 kbytes. ---------------------------------------------------------------------- rk The world of space holds vast promise stellar engineering, ltd. for the service of man, and it is a stellare@erols.com.NOSPAM world we have only begun to explore. Hi-Rel Digital Systems Design -- James E. Webb, 1968Article: 19961
Hey people, does somebody of you has any experience in describing a Correlator with VHDL. I want to generate the clock from a FSK demodulated signal. I think, the first step should be to carry the signal through a Correlator. Jens Sent via Deja.com http://www.deja.com/ Before you buy.Article: 19962
"giuseppe giachella" <il_templare@hotmail.com> wrote in message news:20000119235730.1309.qmail@hotmail.com... > I fear I'm only wasting my time: this Quartus release seems to be full of > bugs and > I'm planning to abandon Altera in favour of Xilinx Virtex. > But what about Xilinx place and route tools? Are they so buggy ? > Should I expect the same neverending fitting loops using Xilinx tools > (Alliance or > Foundation) ? Well, I have used both these tools in the last 4 months rather extensively, and I can say that I have had the exact same problems you have had with Quartus. And, to make matters worse for Altera, I have had no problems, and have been pleased thus far, with the latest and greatest version of Alliance. (2.1i, SP3/4). My personal impression is that Altera woke up one day, looked at the Virtex devices, and then put out the APEX devices waaay to fast without really doing a good job on the software. I can offer a few tips for you to see if you can fix your Quartus problems. Watch out for what synthesis tool you use. You haven't said it here, but try using Synplify instead, or use Quartus for synthesis if you are allready using Synplify. The other thing I found that was causing the infinite loops was bugs in the design, not the program. I'm not sure of your design stage, but Quartus is poor at the early stage of designs. The culprit was Resets. You may want to add a "reset" block which metastable hardens the resets, etc, then fans the resets out to the rest of the design. If the fanout limit is set accordingly, then Quartus will buffer them properly (or so I've seen). I can't help but think there was some other problem that I has having with loops that I solved....but it was before Xmas....and I can't remember off the top of my head. I guess that is what those little lab books are for! Xantos.Article: 19963
Andreas Doering wrote:
>
> Hi,
> I am interested in the implementation of indexing memory in hardware
> (custom or FPGA).
> The problem is the following:
> say we have inputs a0,a1
> and a0 (a 5-bit-vector) can have 19 different values and
> a1 (also 5-bit) can have 21 different values.
> We need to address a memory with binary addresses.
> Hence we could concatenate both vectors and needed 1K memory words.
> However we also could combine both inputs to a 9-bit-vector
> and save half of the memory.
> Of course we can compute the index to the memory as
> 21*(a0)+a1 or something like that.
> Since it is irrelevant how the values are aranged in the memory (we only
> address via the indexing funtion), there might be something much
> smaller.
> Another frequent situation is where
> a0 takes values from 1 to some m-1
> and a1 0 to a0-1 (a1 is always smaller than a0).
> In SW one could use a1+(a0*(a0+1)/2).
> But in HW the sqaring might not be worth the saving of memory.
>
> Are there any general techniques for this kind problems?
> Publications?
>
> Andreas
> -----------------------------------------------------------------
> Andreas C. Doering
> Medizinische Universitaet zu Luebeck
> Institut fuer Technische Informatik
> Email: doering@iti.mu-luebeck.de
> Home: http://www.iti.mu-luebeck.de/~doering
> quiz, papers, VHDL, music
> "The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
> ----------------------------------------------------------------
General purpose solutions usually are expensive.
For your specific case, the following function should do it:
-- maps a=0...23,b=0...19 to a 9-bit vector
-- (left most index assumed as MSB)
function index24x20(a: std_logic_vector(4 downto 0);
b: std_logic_vector(4 downto 0)
) return std_logic_vector is
begin
if to_X01(b(4)) = '1' then
return "11" & a(4 downto 0) & b(1 downto 0);
else
return a(4 downto 0) & b(3 downto 0);
end if;
end;
The trick is to analyze the upper boundary of the ranges and
map some MSB bits of both vectors into a code of less bits.
a b
00000 00000
00001 00001
... ...
01111 01111
10000 10000
10001 10001
10010 10010
10011
10100
So the codes a=11xxx never appear where b=11xxx and b=101xx never
appear.
The function above takes advantage of this and creates unique codes
for all combinations of 0...20 x 0...18 (or even 0...23 x 0...19).
--
_/_/_/_/ _/_/_/ Andreas Gieriet, VP R&D
_/ _/ _/ DS Diagonal Systems
_/ _/ _/_/ phone:+41-1-905-6060
_/ _/ _/ mailto:andi@diagonal.ch
_/_/_/_/ _/_/_/ http://www.diagonal.com/
Article: 19964One of the projects I worked on used a video scaler that required the input line to be repeated when the output image size was larger than the input image size (scale factor > 1). Since the incoming data was live video, we used a FIFO along with the retransmit feature, and everything worked just fine. As was pointed out earlier, make sure that you reset the FIFO properly or things won't work so well. Hal Murray wrote: > > In article <01bf62f0$415d2640$207079c0@drt1>, > "Austin Franklin" <austin@darkroom88.com> writes: > > > Thanks Ray. I looked at that re-transmit feature, but it isn't really > > explained well (on the spec I have)...it eludes that it is only the > > 'current' 'word' that is re-transmitted, not the entire FIFO...but, if you > > say it works, I'll check into it further... > > I've never used that feature on a FIFO, but the data sheet seems > as though it was describing what you would want if you were > going to "retransmit" a packet after an Ethernet collision. > > [A comment about the "current" word may be telling you something > about a pipeline stage that you have to flush.] > -- > These are my opinions, not necessarily my employers. Paul Urbanus ** Never wrestle with a pig - you get dirty and the pig likes it! **Article: 19965
Hi Folks, Which is the best FPGA chip for Digital Signal Processing? In my opinion Xilinx latest VIRTEX FPGAs seem to be the best. These FPGAs features: - Fast carry logic for fast addition and thus multiplication. - Fast synchronous distributed RAMs. These can implment very quick shift registers. - Large and very fast on chip RAMs (BlockRAMs). these can implement real dual port RAM, very usefull for FIFO design. - DLLs for clock deskew --> System design These are very important features in DSP applications. I had a look at other FPGA manufactures, a lot of them offer similar features but either not all of them or with some limitation. The closest is Altera in my opinion. So from a pure performance point of view, Xilinx seems to be the best, is not it? However, I noticed a considerable number of people using Altera devices. I do not want to advertise for Xilinx, but I cannot see why some people perfer other parts, is there a cost factor? a support one? Any comments?Article: 19966
Xilinx Virtex and Spartan-II devices support 5 V CPCI Hot-swap. I can't speak for other PLD vendors, but the key issue for Xilinx was the leakage current specification. In our older devices that support PCI, such as the 4000 series (E, XLT, XLA) and Spartan/XL, there is a default pull-up that exists prior to configuration. This can be removed with the appropriate bitstream, but you have no guarantee that the device will be configured fast enough. As you insert the CPCI Hot-swap card, the time between touching the early power pins and touching the signal pins can be as low as 4 ms. These devices will leak close to 100 uA prior to configuration and the Hot-swap spec calls for less than 10 uA. This will obviously upset the precharge voltage scheme that hot-swap depends on. For Virtex and Spartan-II, we decided to eliminate the default pull-ups prior to configuration. This eliminates the leakage current and allows the precharge voltage to settle at the desired 1 V. Jim McManus Xilinx PCI Applications Engineer Steele Chen wrote: > > i'm looking for a PLD which can support Hot-swap. It'll be used in a CPCI > board, and should not disrupt the system when plugging it in a working > system. I'm now using Alters's 7128AETC100, who can tell me what is the > proper choice? > Please send the answer to me directly 'cos i don't access the newsgroup > often.Article: 19967
On 20 Jan 2000 05:02:08 GMT, murray@pa.dec.com (Hal Murray) wrote: > >> agreed, a random number generator certainly isn't cryptographically, or even >> statistically, secure simply because it's confusing to the designer. People >> have lost wars making that assumption. But as a source of truly random >> addresses for, say, networking applications, something like this is useful >> without the hassle of zener noise-diode things and such. Stirring an async >> clock into a pseudorandom shift register can be a nice way to 'spread out' >> the available randomness, and viewed as random state jumps in the PRN >> sequence, is not totally idiotic. > >I didn't mean to use a word like "idiotic" - appologies if what I said >came across that way. > >I can't think of a case where I would want to stir things up. Do you >have a good example? > >I think I'm asking for a problem with the following properties: > > You need some random numbers. > An LFSR isn't good enough. > An LFSR with stirring (via async clock) helps significnatly. Hal, someone asked (in another ng) for a way to assign different LAN node addresses, or something like that, in an FPGA, and couldn't think of any way that a proper synchronous design would ever do anything different from node to node; all the 'random' numbers would inevitably be the same. After all, if a synchronous digital system wasn't absolutely repeatable, we couldn't use it. So some recourse to an external event is needed; I suggested measuring the time delay of a slow, very bad external RC, and then somebody else suggested using the free-running clock in a Xilinx chip. The 'stirring' is just an easy way to get a simple, maybe low-frequency async clock, to generate a many-bit random number. Stirring into a PRN register is also a good way to remove residual errors (bit bias, autocorrelations, the very fact that PRN sequences are predictable) from a pretty good random bitstream, as you might get from a zener diode noise source. I'm still kinda fond of my chaos-theory RC charge/discharge idea, but, alas, it does fall into the category of 'confusing to the designer'... JohnArticle: 19968
On Thu, 20 Jan 2000 08:20:35 +0200, "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za> wrote: >For someone new to Xilinx. >I am planning to use a XC9572 PLD using the online Web compiler and fitter - >using VHDL source code. >Does anyone know how to embedd my pin allocation details into the VHDL >source. > >Thanks Anthony > One scairy thought: if we use web-based design tools, how do we know they'll still be available a year or three from now if we want to do a revision? It's clearly in the interest of the vendors that old tools NOT be available! JohnArticle: 19969
Frankly, I don't get it either. I've remarked many times on the shortcomings of the Altera acrhitectures with respect to DSP applications here in this newsgroup (you can search deja-news if you are curious). I've also found the Xilinx support hotline infinitely more responsive than Altera's help line (it could still use quite a bit of help though), so it's not that. Altera has been a little more synthesis friendly, mostly because of the global routing structure, but I think virtex has closed that gap somewhat. I think a large part of it may be 1) what users are used to, and 2) percieved ease of use. Altera has a very aggressive university program which puts the altera devices and tools into student's hands at virtually no cost. Xilinx isn't nearly so forthcoming on that front. Altera's tools are more 'push the big green button and let it go' than xilinx, which is fine when you are doing designs that don't effectively use the FPGA's capability. Altera tools lack the controllability needed to tweak the design compilation, which may make the tool less onerous to learn but more frustrating for the accomplished user. For DSP, you really need an effective carry chain architecture, and the ability to efficiently realize delay queues. Altera's carry chain structure is crippled for all but the most basic arithmetic functions, and delay queues chew up an awful lot of resource. George wrote: > Hi Folks, > > Which is the best FPGA chip for Digital Signal Processing? > > In my opinion Xilinx latest VIRTEX FPGAs seem to be the best. > > These FPGAs features: > > - Fast carry logic for fast addition and thus multiplication. > - Fast synchronous distributed RAMs. These can implment very quick shift > registers. > - Large and very fast on chip RAMs (BlockRAMs). these can implement real > dual port RAM, very usefull for FIFO design. > - DLLs for clock deskew --> System design > > These are very important features in DSP applications. I had a look at other > FPGA manufactures, a lot of them offer similar features but either not all > of them or with some limitation. The closest is Altera in my opinion. > So from a pure performance point of view, Xilinx seems to be the best, is > not it? > However, I noticed a considerable number of people using Altera devices. I > do not want to advertise for Xilinx, but I cannot see why some people perfer > other parts, is there a cost factor? a support one? > > Any comments? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19970
Dear all, I was wondering if others have noticed any strange results from the *functional* simulation of VHDL design using the Virtex SelectRAM Block model from the UNISIM library (I'm using Synopsys). First, I get warnings about setup time violations and I don't see why since I'm doing a functional simulation: "*/RAMB4_S2_S4 HOLD Low VIOLATION ON WEB WITH RESPECT TO CLKB; Expected := 0.01 NS; Observed := 0 NS; At : 146575.1 NS" Assertion WARNING at 146575100 PS in design unit VITAL_TIMING from process /BENCH/U1/U2/BRAM1/VITALBEHAVIOR: A quick fix of course is delaying the signal WEB with respect to CLKB by 10ps with an after clause in the signal assignment, but I should not get this worning at all I think. I also noticed that the DOA (port A outputs) go active as soon as ENA goes from 0 to 1 instead of going active with the transition of the clock from 0 to 1. Any ideas? Thanks in advance, -Arrigo -- Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 phone: (626) 395-3695 Pasadena, CA 91125 fax: (626) 795-8649Article: 19971
Andreas Doering wrote: > I am interested in the implementation of indexing memory in hardware > (custom or FPGA). > The problem is the following: > say we have inputs a0,a1 > and a0 (a 5-bit-vector) can have 19 different values and > a1 (also 5-bit) can have 21 different values. > We need to address a memory with binary addresses. > Hence we could concatenate both vectors and needed 1K memory words. Have you considered commercially-available content-addressable memory (CAM)? I don't have any experience actually using it myself, but it seems to me that it could be used to do what you describe. A quick web search turned up a number of manufacturers, or which Quality Semiconductor (www.qualitysemi.com) is just one -- their data sheets look pretty comprehensive. I don't know anything about the cost of such parts, and of course I have no idea about the requirements of your application -- this is just a thought. MarkArticle: 19972
Paul Walker wrote: > > It is obvious that if company A makes a UART chip say, and company B has > a patent on the generic features of a UART, then Company A is liable to > have to pay a licence and/or royalty to company B. The "generic features of a UART" are well-established. They are well- known to anyone "skilled in the art", they are widely published, they are not patented, and they cannot be patented. However techniques (either algorithms or specific novel circuit designs and methods) for improving the performance, reducing the cost or otherwise resulting in specific enhancements are patentable. I can't believe that you picked this example at random -- I'm sure you're aware that National Semiconductor has patents covering aspects of the 16550 and 16552 UARTs. You have asked a generic question, but there is no generic answer -- whether or not a competing (or complementary) design or implementation infringes an existing patent is specific to every case. It depends what the patent covers (i.e. what claims have been allowed by the patents office), what the new design involves, and how it relates to existing patents and/or published works. Note also that not all patents are valid! You may, for example, be able to show that there was prior art that the patent examiner did not discover, which means that the patent should never have been granted. (Of course, making this kind of challenge generally means going to court, and usually gets expensive). > Does anyone know of any case history or legal advice concerning company > C who sells an FPGA containing said UART function? No one in Company B > can point to circuitry in the FPGA that embodies the patented > intellectual property. It is possible, I suppose, that if the patent > includes method claims, then it might be possible to use these against a > soft emulation of the patented invention. You are asking in the wrong group. You need specific legal advice -- as I said above, I doubt very much that there is a generic answer. > 1: every company who owns an FPGA that is downloaded with a "UART" > program is liable to pay a licence > > 2: every company that sells design IP of a "UART" is liable to pay a > licence Assuming that a patented technique was used in the design of the UART IP, an agreement would have to be made with the patent holder. Most license agreements are similar to this case -- a royalty is paid for each instance sold. But the final licensing agreement is again case-specific -- it would most likely only be resolved after much negotiation between the parties involved. In most cases the outcome would probably work a lot like case 2, because this is the most practical in terms of the cost of actually collecting royalties. However, obviously these costs are passed on to the end user in some way, so case 2 is in practice an indirect version of case 1. > 3: if an FPGA vendor pays a licence, then any customer can use that > vendor's chips to implement the "UART" function This would never work -- there are millions of pieces of patented, patentable and copyright IP, and no FPGA manufacturer is in a position to pay for them all! They would argue (rightly) that managing such a portfolio of licensed IP is outside their core business, and would result in them having to pass the increased costs on to all their customers -- even those who never need to use any of the licensed IP. > 4: no licence is payable at all. Oh... it is to laugh ;-) Disclaimer: I am NOT a patent attorney (although I have dealt with some). This opinion comes with absolutely no warranty, and is worth exactly what you paid for it! MarkArticle: 19973
Austin Franklin wrote: > Problem with using SRAM, is I am pinbound at this point...8k is another 14 > pins...don't think I can do it...but that would be my first choice....if I > had the pins... You could use an external counter with your SRAM -- then you'd only need enough FPGA pinouts to connect to the control/status pins of the counter. Maybe implement an application-specific counter in a small PLD? MarkArticle: 19974
> > Problem with using SRAM, is I am pinbound at this point...8k is another 14 > > pins...don't think I can do it...but that would be my first choice....if I > > had the pins... > > You could use an external counter with your SRAM -- then you'd only need > enough FPGA pinouts to connect to the control/status pins of the > counter. Maybe implement an application-specific counter in a small > PLD? I thought about that, but it ended up getting all too complicated...it became easier to just bump up the FPGA pinout from a PQ240 to a BGA352... That gives me all the pins I need to make my own FIFO of VERY high depth (256k) and control it any way I need to... A much more elegant solution. Thanks, everyone, for your opinions and help!
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