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Threads Starting Jun 2000
22908: 00/06/01: Domagoj: Microprocessors in FPGA
22911: 00/06/01: Ray Andraka: Re: Microprocessors in FPGA
22927: 00/06/03: Domagoj: Re: Microprocessors in FPGA
22928: 00/06/02: Dave Vanden Bout: Re: Microprocessors in FPGA
22929: 00/06/03: Bob Perlman: Re: Microprocessors in FPGA
22930: 00/06/03: Domagoj: Re: Microprocessors in FPGA
23046: 00/06/10: Lasse Langwadt Christensen: Re: Microprocessors in FPGA
22912: 00/06/01: Nicholas C. Weaver: Re: Microprocessors in FPGA
22953: 00/06/05: <kayrock@geocities.com>: Re: Microprocessors in FPGA
24203: 00/07/29: <nospam@lizard.net>: Re: Microprocessors in FPGA
22913: 00/06/01: Christian Habermann: Virtual Workbench VW-300, verify
22914: 00/06/02: <ramesh_z@my-deja.com>: view synthesis 7.0
22915: 00/06/02: Aditya: Altera
22917: 00/06/02: NgKH: university graduate seeking IT position
22918: 00/06/02: hal: Foundation problem with verilog & Xilinx 5200
22919: 00/06/02: Bob Perlman: Where's OptiMagic?
22933: 00/06/04: Alex P.Martin: Re: Where's OptiMagic?
22982: 00/06/07: Philip Freidin: Re: Where's OptiMagic?
22990: 00/06/07: Patrick Schulz: Re: Where's OptiMagic?
23001: 00/06/08: Charles: Re: Where's OptiMagic?
22920: 00/06/02: <jthioude@my-deja.com>: to make few modifications on a design
22931: 00/06/03: llandre: Re: to make few modifications on a design
22981: 00/06/07: disk: Re: to make few modifications on a design
22921: 00/06/02: Joe Wetstein: SPICE simulation of circuit board design
22923: 00/06/02: Eirik Esp: Virtex Block Select RAM Timing Problem
22924: 00/06/02: Eirik Esp: Re: Virtex Block Select RAM Timing Problem
22926: 00/06/02: Rick Filipkiewicz: Re: Virtex Block Select RAM Timing Problem
22925: 00/06/02: Steve Holle: Convert Xilinx Foundation ourput to C/C++ compatible file.
22935: 00/06/04: Christian Mautner: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
22944: 00/06/05: Steve Holle: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
22952: 00/06/05: Christian Mautner: Re: Convert Xilinx Foundation ourput to C/C++ compatible file.
22932: 00/06/03: llandre: Free sources on the net
22936: 00/06/04: <lone_traveler@my-deja.com>: Altera FPGA/CPLD in-system-programmer
22937: 00/06/05: Willy_Tsai: Altera and Atmel FPGA/CPLD in-system-programmer from SmartChip
22938: 00/06/05: Patrick Schulz: Synopsis DesignWare PCI-Core (DWPCI) implemented on FPGA?
22939: 00/06/05: Leinonen Mika: PLA to ABEL converter?
22946: 00/06/05: Austin Franklin: Re: PLA to ABEL converter?
22954: 00/06/06: Jim Granville: Re: PLA to ABEL converter?
22940: 00/06/05: Ulrich Seidl: Virtex: How to Map 2 Functions to one Slice
22942: 00/06/05: Russell Tessier: Call for Papers: FPGA'2001
22945: 00/06/05: Hans Kester: Re: CPLD: gang programming
22947: 00/06/05: Dan Kuechle: Virtex-E and SCSI
22967: 00/06/06: Gary Watson: Re: Virtex-E and SCSI
22948: 00/06/05: Joe Wetstein: SPICE help
22951: 00/06/05: John E. Kuslich: Re: SPICE help
22959: 00/06/06: Olaf Birkeland: Re: SPICE help
22949: 00/06/05: myself: 3.3V I/O TO 5V LOGIC?
22950: 00/06/05: Dalip K. Singh: Re: 3.3V I/O TO 5V LOGIC?
22958: 00/06/06: Peter Alfke: Re: 3.3V I/O TO 5V LOGIC?
22969: 00/06/06: Rickman: Re: 3.3V I/O TO 5V LOGIC?
22972: 00/06/06: Andy Peters: Re: 3.3V I/O TO 5V LOGIC?
22975: 00/06/06: Dalip K. Singh: Re: 3.3V I/O TO 5V LOGIC?
22955: 00/06/05: Rickman: Re: 3.3V I/O TO 5V LOGIC?
22957: 00/06/06: Peter Alfke: Re: 3.3V I/O TO 5V LOGIC?
22956: 00/06/06: Peter Alfke: Re: 3.3V I/O TO 5V LOGIC?
22965: 00/06/06: myself: Re: 3.3V I/O TO 5V LOGIC?
22970: 00/06/06: Peter Alfke: Re: 3.3V I/O TO 5V LOGIC?
22973: 00/06/07: Jim Granville: Re: 3.3V I/O TO 5V LOGIC?
22976: 00/06/07: Peter Alfke: Re: 3.3V I/O TO 5V LOGIC?
22966: 00/06/06: Marc Battyani: Re: 3.3V I/O TO 5V LOGIC?
22960: 00/06/06: <bear5@my-deja.com>: [JOB] Engineering Director for FPGA/ASIC Design Company
22964: 00/06/06: Jamil Khatib: Free tools "OpenTech cdrom"
22974: 00/06/06: <iglasner@my-deja.com>: Re: Free tools "OpenTech cdrom"
22980: 00/06/07: Andrew MacCormack: Re: Free tools "OpenTech cdrom"
23085: 00/06/14: Domagoj: Re: Free tools "OpenTech cdrom"
23095: 00/06/14: Patrick Schulz: Re: Free tools "OpenTech cdrom"
22977: 00/06/07: James Kennedy: VHDL code works in foundation 1.5, dosen't work in 2.1?
22984: 00/06/07: Joshua Lamorie: Re: VHDL code works in foundation 1.5, dosen't work in 2.1?
22978: 00/06/07: Jukka Pöppönen: Xilinx Spartan; CLB's run out
22992: 00/06/08: Ray Andraka: Re: Xilinx Spartan; CLB's run out
22979: 00/06/07: Giuseppe Baruffa: Info on Ballynuey 2
22983: 00/06/07: <bkk411@my-deja.com>: FC2 v3.4 & Selcet Block RAM in Virtex(E)
22985: 00/06/07: Seiya: Xilinx foundation Student Edition problem.
22986: 00/06/07: disk: Re: Xilinx foundation Student Edition problem.
22995: 00/06/08: Klaus Falser: Re: Xilinx foundation Student Edition problem.
23009: 00/06/08: R. T. Finch: Re: Xilinx foundation Student Edition problem.
22987: 00/06/07: Domagoj: XCV vs. XCV-E ?
22988: 00/06/07: Nicholas C. Weaver: Re: XCV vs. XCV-E ?
22991: 00/06/08: Domagoj: Re: XCV vs. XCV-E ?
22996: 00/06/08: Olaf Birkeland: Re: XCV vs. XCV-E ?
23004: 00/06/08: Peter Alfke: Re: XCV vs. XCV-E ?
23005: 00/06/08: Domagoj: Re: XCV vs. XCV-E ?
23006: 00/06/08: Peter Alfke: Re: XCV vs. XCV-E ?
23041: 00/06/10: Tom Burgess: Re: XCV vs. XCV-E ?
22989: 00/06/07: John Smithhhhh: Synplify constrains
22993: 00/06/08: Jim Granville: TTL device Libraries
23007: 00/06/09: Ray Andraka: Re: TTL device Libraries
23012: 00/06/09: Jim Granville: Re: TTL device Libraries
23018: 00/06/09: <rob_dickinson@my-deja.com>: Re: TTL device Libraries
23021: 00/06/09: Jim Granville: Re: TTL device Libraries
23024: 00/06/09: <rob_dickinson@my-deja.com>: Re: TTL device Libraries
23040: 00/06/09: Elftmann: Re: TTL device Libraries
23020: 00/06/09: Kim Carter: Re: TTL device Libraries
23033: 00/06/09: Steve Dewey: Re: TTL device Libraries
22994: 00/06/08: John Smith: difference between fpga and epld
23119: 00/06/14: <kayrock@geocities.com>: Re: difference between fpga and epld
23147: 00/06/15: Chris Foran: Re: difference between fpga and epld
23162: 00/06/16: <rob_dickinson@my-deja.com>: Re: difference between fpga and epld
157460: 14/12/11: Nicolas Matringe: Re: difference between fpga and epld
157457: 14/12/11: <gentrysm1@gmail.com>: Re: difference between fpga and epld
157470: 14/12/11: Tim Wescott: Re: difference between fpga and epld
22997: 00/06/08: Frank Madison: Deficiencies in Actel 40mx tools?
22998: 00/06/08: rk: Re: Deficiencies in Actel 40mx tools?
23002: 00/06/08: Kate Atkins: Re: Deficiencies in Actel 40mx tools?
22999: 00/06/08: IPSIS.news: [JOB] Designer / FPGA
23000: 00/06/08: LIM JAE-HWAN: I don't know "simulator mode"
23003: 00/06/08: <mcoyle5605@my-deja.com>: data communication
23008: 00/06/09: =?EUC-KR?B?wNPA58iv?=: Please,give me solution for "serious pad to pad delay" in Xilinx.
23011: 00/06/09: Rickman: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23019: 00/06/09: Chris Shenton: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23057: 00/06/12: <brian_boorman@my-deja.com>: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23062: 00/06/12: Rickman: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23069: 00/06/12: Peter Alfke: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23082: 00/06/13: <kayrock@geocities.com>: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23010: 00/06/09: Sherdyn: Problem with state machine
23058: 00/06/12: <kayrock@geocities.com>: Re: Problem with state machine
23013: 00/06/09: William LenihanIii: Synopsys FPGA Compiler
23014: 00/06/09: <bkk411@my-deja.com>: XILINX RAM Useless
23023: 00/06/09: Andrew Ince: Re: XILINX RAM Useless
23028: 00/06/09: <bkk411@my-deja.com>: Re: XILINX RAM Useless
23031: 00/06/09: B. Joshua Rosen: Re: XILINX RAM Useless
23032: 00/06/09: B. Joshua Rosen: Re: XILINX RAM Useless
23042: 00/06/10: Austin Franklin: Re: XILINX RAM Useless
23037: 00/06/10: Ray Andraka: Re: XILINX RAM Useless
23038: 00/06/10: <bkk411@my-deja.com>: Re: XILINX RAM Useless
23045: 00/06/10: Magnus Homann: Re: XILINX RAM Useless
23048: 00/06/10: Ray Andraka: Re: XILINX RAM Useless
23137: 00/06/15: Andrew Ince: Re: XILINX RAM Useless
23043: 00/06/10: eugenir: Re: XILINX RAM Useless
23250: 00/06/19: David Hawke: Re: XILINX RAM Useless
23015: 00/06/09: P Little: Simulation of VIRTEX BLOCKRAM
23026: 00/06/09: Ray Andraka: Re: Simulation of VIRTEX BLOCKRAM
23029: 00/06/09: <bkk411@my-deja.com>: Re: Simulation of VIRTEX BLOCKRAM
23016: 00/06/09: Christophe Heyert: using DDL in virtex FPGA
23022: 00/06/09: Rémi SEGLIE: Re: using DDL in virtex FPGA
23053: 00/06/11: Mark Harvey: Re: using DDL in virtex FPGA
23017: 00/06/09: Tim Forcer: ANNOUNCE: Call for Contributions
23025: 00/06/09: <jnewton@embeddedsol.com>: VirtexE Readback Parameters
23027: 00/06/09: Cser Laszlo: Readout of an FPGA?
23039: 00/06/09: Elftmann: Re: Readout of an FPGA?
23056: 00/06/12: Eric Pearson: Re: Readout of an FPGA?
23030: 00/06/09: Lars: Virtex-EM and F2.1
23078: 00/06/13: Scott: Re: Virtex-EM and F2.1
23034: 00/06/09: Anthony Rowe: Fast Fourier Transform Processors
23054: 00/06/11: Bill Flannery: Re: Fast Fourier Transform Processors
23035: 00/06/09: Jonathan Zingman: Too many unbeffered connections in Foundation
23036: 00/06/09: Simon Ramirez: Re: WIDESPREAD INCOMPETENCE AT BELL ATLANTIC
23044: 00/06/10: John Larkin: math help needed
23047: 00/06/10: Magnus Homann: Re: math help needed
23049: 00/06/11: Tom Burgess: Re: math help needed
23050: 00/06/11: Frank Madison: Re: math help needed
23051: 00/06/11: Jamil Khatib: Virtex questions
23083: 00/06/13: Utku Ozcan: Re: Virtex questions
23087: 00/06/14: Domagoj: Re: Virtex questions
23105: 00/06/14: Brian Philofsky: Re: Virtex questions
23151: 00/06/15: <erika_uk@my-deja.com>: 3.1i
23165: 00/06/16: Utku Ozcan: Re: 3.1i
23216: 00/06/18: Brian Drummond: Re: 3.1i
23253: 00/06/19: Andy Peters: Re: 3.1i
23055: 00/06/12: Dave: Back annotated timing in FPGA Advantage
23059: 00/06/12: Seiya: Xilinx Project manager 1.5
23068: 00/06/12: Dave Vanden Bout: Re: Xilinx Project manager 1.5
23060: 00/06/12: <swfpga@my-deja.com>: Altera vs Xilinx
23063: 00/06/12: <phil_jackson@my-deja.com>: Re: Altera vs Xilinx
23066: 00/06/12: <iglasner@my-deja.com>: Re: Altera vs Xilinx
23070: 00/06/13: Ray Andraka: Re: Altera vs Xilinx
23064: 00/06/12: Rickman: Re: Altera vs Xilinx
23067: 00/06/12: Bob Perlman: Re: Altera vs Xilinx
23071: 00/06/13: Ray Andraka: Re: Altera vs Xilinx
23065: 00/06/12: Ray Andraka: Re: Altera vs Xilinx
23074: 00/06/13: Lance Dannan Bresee: Re: Altera vs Xilinx
23075: 00/06/13: Dan: Re: Altera vs Xilinx
23081: 00/06/13: <kayrock@geocities.com>: Re: Altera vs Xilinx
23084: 00/06/13: Steve Dewey: Re: Altera vs Xilinx
23061: 00/06/12: <swfpga@my-deja.com>: Altera vs Xilinx
23072: 00/06/13: David Brown: Virtex IRDY and TRDY
23077: 00/06/13: Scott: Re: Virtex IRDY and TRDY
23080: 00/06/13: Brian Boorman: Re: Virtex IRDY and TRDY
23168: 00/06/16: Tom Fischaber: Re: Virtex IRDY and TRDY
23073: 00/06/13: Kenneth Porter: Simple JTAG programmer for Altera MAX 7128A?
23124: 00/06/15: Steve Rencontre: Re: Simple JTAG programmer for Altera MAX 7128A?
23298: 00/06/21: Kenneth Porter: Re: Simple JTAG programmer for Altera MAX 7128A?
23351: 00/06/23: Steve Rencontre: Re: Simple JTAG programmer for Altera MAX 7128A?
23076: 00/06/13: Christophe Heyert: DLL in virtex fpga
23098: 00/06/14: B. Joshua Rosen: Re: DLL in virtex fpga
23079: 00/06/13: Claas Richter: Harddisk <--> FPGA <--> PC
23086: 00/06/14: <ramesh_z@my-deja.com>: ASIC DESIGN
23088: 00/06/14: <baneshwar_s@my-deja.com>: delay variation
23103: 00/06/14: David Gilchrist: Re: delay variation
23089: 00/06/13: Robert L. Metcalf: FS: AsicGuru.com DOMAIN on EBAY
23090: 00/06/13: Robert L. Metcalf: FS: FpgaGuru.com DOMAIN
23091: 00/06/14: Bob Perlman: Re: FS: FpgaGuru.com DOMAIN
23092: 00/06/13: Phil Hays: Re: FS: FpgaGuru.com DOMAIN
23104: 00/06/14: Andy Peters: Re: FS: FpgaGuru.com DOMAIN
23108: 00/06/14: Ray Andraka: Re: FS: FpgaGuru.com DOMAIN
23093: 00/06/14: À̺´¿í: FPGA Express & MAX+PLUS II Using ?
23094: 00/06/14: Heinrich Fonfara: Req: Source for Filter Design
23101: 00/06/14: Craig Slorach: Re: Source for Filter Design
23096: 00/06/14: laurent: for my students
23109: 00/06/14: Ray Andraka: Re: for my students
23097: 00/06/14: laurent: for my students + my E-mail
23099: 00/06/14: <swally4771@my-deja.com>: aeos - ebusiness
23100: 00/06/14: Steven Derrien: PCI for a fpga board
23102: 00/06/14: Austin Franklin: Re: PCI for a fpga board
23106: 00/06/14: Steven Derrien: Re: PCI for a fpga board
23114: 00/06/14: Austin Franklin: Re: PCI for a fpga board
23116: 00/06/14: david garnett: Re: PCI for a fpga board
23142: 00/06/15: Austin Franklin: Re: PCI for a fpga board
23211: 00/06/17: Phil Logan: PCI for a fpga board
23131: 00/06/15: Gary Watson: Re: PCI for a fpga board
23132: 00/06/15: Steven Derrien: Re: PCI for a fpga board
23167: 00/06/16: Martin Heimlicher: Re: PCI for a fpga board
23208: 00/06/17: Austin Franklin: Re: PCI for a fpga board
23107: 00/06/14: Gary Cook: Altera Output Timing Question
23117: 00/06/14: <kayrock@geocities.com>: Re: Altera Output Timing Question
23146: 00/06/15: Peter Alfke: Re: Altera Output Timing Question
23148: 00/06/15: bob elkind: Re: Altera Output Timing Question
23110: 00/06/14: Alex Carreira: Mutating Virtex FPGA
23111: 00/06/14: Nicholas C. Weaver: Re: Mutating Virtex FPGA
23133: 00/06/15: <rickballantyne@home.com>: Re: Mutating Virtex FPGA
23112: 00/06/14: James Young: Question: Xilinx FPGA PROGRAM pin
23113: 00/06/14: Peter Alfke: Re: Question: Xilinx FPGA PROGRAM pin
23169: 00/06/16: Rickman: Re: Question: Xilinx FPGA PROGRAM pin
23115: 00/06/14: Abdar Kerpal: PAR Times for XILINX Foundation Express Student Edition 1.5
23118: 00/06/15: Goulas George: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23123: 00/06/15: Jim Granville: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23120: 00/06/15: Goulas George: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23122: 00/06/14: Abdar Kerpal: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23125: 00/06/15: Philip Freidin: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23138: 00/06/15: Abdar Kerpal: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23121: 00/06/14: <dave_admin@my-deja.com>: FIFO design
23127: 00/06/15: Peter Alfke: Re: FIFO design
23129: 00/06/15: Jamil Khatib: Re: FIFO design
23172: 00/06/16: <dave_admin@my-deja.com>: Re: FIFO design
23269: 00/06/20: Jamil Khatib: Re: FIFO design
23139: 00/06/15: David Kessner: Re: FIFO design
23126: 00/06/15: MK Yap: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23350: 00/06/23: Jamie Lokier: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23356: 00/06/23: MK Yap: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23928: 00/07/15: Eric Vannerson: Re: Error: Clock skew plus hold time of destination register exceeds
23929: 00/07/16: Hal Murray: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23937: 00/07/16: taniwha: Re: Error: Clock skew plus hold time of destination register exceeds
23382: 00/06/23: <iglasner@my-deja.com>: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23816: 00/07/11: <khanzode@my-deja.com>: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23128: 00/06/15: <shahzad2512@my-deja.com>: Reed Solomon in Xilinx FPGA?
23233: 00/06/18: Mark Aaldering: Re: Reed Solomon in Xilinx FPGA?
23130: 00/06/15: Steven Derrien: FPGA board, PCI PLX bridge, DMA and Linux ..
23134: 00/06/15: Michael Barr: ANNOUNCE: Embedded Systems Glossary and Bibliography
23136: 00/06/15: Lars Lotzenburger: CoreGenerator and VHDL
23140: 00/06/15: Nicolas Matringe: Re: CoreGenerator and VHDL
23144: 00/06/15: Scott: Re: CoreGenerator and VHDL
23141: 00/06/15: =?iso-8859-1?Q?=C1ngel=20Guti=E9rrez?=: PWM
23150: 00/06/15: David Kessner: Re: PWM
23143: 00/06/15: <abp_00@my-deja.com>: Work as a freelance FPGA engineer
23149: 00/06/15: Brent: VHDL synthesis.
23153: 00/06/15: Xilinx CAE Cory: Re: VHDL synthesis.
23160: 00/06/16: Leon Heller: Re: VHDL synthesis.
23292: 00/06/21: Peter Mason: Re: VHDL synthesis.
23152: 00/06/16: Nestor C.: Designing a narrowband bandpass filter to pass a tone (analog domain)
23156: 00/06/16: Dominique SZYMIK: Re: Designing a narrowband bandpass filter to pass a tone (analog
23158: 00/06/16: Radboud Verberne: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23161: 00/06/16: Tom Burgess: Re: Designing a narrowband bandpass filter to pass a tone (analog
23163: 00/06/16: Jan Panteltje: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23164: 00/06/16: Reg Edwards: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23176: 00/06/16: Nestor: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23187: 00/06/16: Ray Andraka: Re: Designing a narrowband bandpass filter to pass a tone (analog
23210: 00/06/17: Mark Zenier: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23268: 00/06/20: Dominique SZYMIK: Re: Designing a narrowband bandpass filter to pass a tone (analog
23308: 00/06/21: John E. Perry: Re: Designing a narrowband bandpass filter to pass a tone (analog
23184: 00/06/16: John Woodgate: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
23155: 00/06/16: sceloporus occidentalis: Xilinx config over parallel port ?
23159: 00/06/16: Leon Heller: Re: Xilinx config over parallel port ?
23180: 00/06/16: sceloporus occidentalis: Re: Xilinx config over parallel port ?
23218: 00/06/17: Rickman: Re: Xilinx config over parallel port ?
23224: 00/06/18: Ray Andraka: Re: Xilinx config over parallel port ?
23225: 00/06/18: Rickman: Re: Xilinx config over parallel port ?
23236: 00/06/18: Ray Andraka: Re: Xilinx config over parallel port ?
23178: 00/06/16: Björn Lindegren: SV: Xilinx config over parallel port ?
23189: 00/06/16: Ray Andraka: Re: SV: Xilinx config over parallel port ?
23222: 00/06/17: GB: Re: Xilinx config over parallel port ?
23267: 00/06/19: Robert Binkley: Re: Xilinx config over parallel port ?
23297: 00/06/21: Juan-Luis Lopez: RE: Xilinx config over parallel port ?
23302: 00/06/21: sceloporus occidentalis: RE: Xilinx config over parallel port ?
23305: 00/06/21: Rickman: Re: Xilinx config over parallel port ?
23360: 00/06/23: Juan-Luis Lopez: RE: Xilinx config over parallel port ?
23157: 00/06/16: Brent: XC4005XL OTP?
23171: 00/06/16: Rickman: Re: XC4005XL OTP?
23173: 00/06/16: Peter Alfke: Re: XC4005XL OTP?
23170: 00/06/16: <russojl@my-deja.com>: Virtex ".FFX" contraint???
23175: 00/06/16: Bret Wade: Re: Virtex ".FFX" contraint???
23183: 00/06/16: Philip Freidin: Re: Virtex ".FFX" contraint???
23203: 00/06/17: <russojl@my-deja.com>: Re: Virtex ".FFX" contraint???
23205: 00/06/17: Bret Wade: Re: Virtex ".FFX" contraint???
23213: 00/06/17: Ray Andraka: Re: Virtex ".FFX" contraint???
23186: 00/06/16: Ray Andraka: Re: Virtex ".FFX" contraint???
23174: 00/06/16: Abdul S Khan: 386 Chipset Example
23177: 00/06/16: Arrigo Benedetti: Block level incremental synthesis (?)
23188: 00/06/16: Ray Andraka: Re: Block level incremental synthesis (?)
23181: 00/06/16: Dan: Hand soldering a PQ208 - It looks tough to do.
23185: 00/06/16: Greg Neff: Re: Hand soldering a PQ208 - It looks tough to do.
23194: 00/06/16: Rick Filipkiewicz: Re: Hand soldering a PQ208 - It looks tough to do.
23240: 00/06/19: Greg Neff: Re: Hand soldering a PQ208 - It looks tough to do.
23249: 00/06/19: eng: Re: Hand soldering a PQ208 - It looks tough to do.
23197: 00/06/17: peter dudley: Re: Hand soldering a PQ208 - It looks tough to do.
23200: 00/06/17: Joel Kolstad: Re: Hand soldering a PQ208 - It looks tough to do.
23241: 00/06/19: Greg Neff: Re: Hand soldering a PQ208 - It looks tough to do.
23191: 00/06/16: Ray Andraka: Re: Hand soldering a PQ208 - It looks tough to do.
23221: 00/06/17: Larry Edington: Re: Hand soldering a PQ208 - It looks tough to do.
23254: 00/06/19: Terry Harris: Re: Hand soldering a PQ208 - It looks tough to do.
23242: 00/06/18: Elftmann: Re: Hand soldering a PQ208 - It looks tough to do.
23182: 00/06/16: rajesh52: Verilog FAQ
23190: 00/06/16: Muzaffer Kal: spartan and virtex on the same board ?
23192: 00/06/16: Peter Alfke: Re: spartan and virtex on the same board ?
23193: 00/06/16: Domagoj: Re: spartan and virtex on the same board ?
23195: 00/06/16: Muzaffer Kal: Re: spartan and virtex on the same board ?
23199: 00/06/17: Rick Collins: Re: spartan and virtex on the same board ?
23201: 00/06/17: Bob Perlman: Re: spartan and virtex on the same board ?
23219: 00/06/17: Rickman: Re: spartan and virtex on the same board ?
23196: 00/06/17: Zoltan Kocsi: Two questions
23202: 00/06/17: Simon: Re: Two questions
23204: 00/06/17: B. Joshua Rosen: Request for experiences with Linux CAE tools
23220: 00/06/17: Duane: Re: Request for experiences with Linux CAE tools
23206: 00/06/17: <locate@locate-now.com>: Internet and scripting
23207: 00/06/17: Rick Collins: Problem copying text from the Spartan II data sheet
23214: 00/06/17: Ray Andraka: Re: Problem copying text from the Spartan II data sheet
23223: 00/06/17: Rickman: Re: Problem copying text from the Spartan II data sheet
23215: 00/06/17: John Larkin: Re: Problem copying text from the Spartan II data sheet
23217: 00/06/18: Ray Andraka: Re: Problem copying text from the Spartan II data sheet
23226: 00/06/18: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23227: 00/06/18: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23229: 00/06/17: John Larkin: Re: Problem copying text from the Spartan II data sheet
23231: 00/06/18: Rickman: Re: Problem copying text from the Spartan II data sheet
23232: 00/06/18: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23245: 00/06/19: Rickman: Re: Problem copying text from the Spartan II data sheet
23293: 00/06/21: Theron Hicks: Re: Problem copying text from the Spartan II data sheet
23228: 00/06/18: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23230: 00/06/18: eng: Re: Problem copying text from the Spartan II data sheet
23234: 00/06/19: Jim Granville: Re: Problem copying text from the Spartan II data sheet
23235: 00/06/18: Nicholas C. Weaver: Re: Problem copying text from the Spartan II data sheet
23237: 00/06/18: John Larkin: Re: Problem copying text from the Spartan II data sheet
23246: 00/06/19: Rickman: Re: Problem copying text from the Spartan II data sheet
23248: 00/06/19: Nicolas Matringe: Re: Problem copying text from the Spartan II data sheet
23256: 00/06/19: Rick Filipkiewicz: Re: Problem copying text from the Spartan II data sheet
23263: 00/06/19: John Larkin: Re: Problem copying text from the Spartan II data sheet
23265: 00/06/19: Rickman: Re: Problem copying text from the Spartan II data sheet
23266: 00/06/20: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23278: 00/06/20: Peter Alfke: Re: Problem copying text from the Spartan II data sheet
23279: 00/06/20: Robert Binkley: Re: Problem copying text from the Spartan II data sheet
23282: 00/06/20: Tom Burgess: Re: Problem copying text from the Spartan II data sheet
23283: 00/06/21: Jim Granville: Re: Problem copying text from the Spartan II data sheet
23296: 00/06/21: Robert Binkley: Re: Problem copying text from the Spartan II data sheet
23317: 00/06/22: Simon: Re: Problem copying text from the Spartan II data sheet
23331: 00/06/22: Marc Klingelhofer: Re: Problem copying text from the Spartan II data sheet
23409: 00/06/24: Rick Filipkiewicz: Re: Problem copying text from the Spartan II data sheet
23417: 00/06/24: Brian Drummond: Re: Problem copying text from the Spartan II data sheet
23482: 00/06/27: Rick Filipkiewicz: Re: Problem copying text from the Spartan II data sheet
23423: 00/06/24: Rickman: Re: Problem copying text from the Spartan II data sheet
23289: 00/06/21: dmac: Re: Problem copying text from the Spartan II data sheet
23209: 00/06/17: Eric: Battery backup for 5V Xilinx Spartan devices
23280: 00/06/20: richm: Re: Battery backup for 5V Xilinx Spartan devices
23212: 00/06/17: Bob Warnke: Control System Engineering Jobs
23238: 00/06/19: Domagoj: How to cut the power disipation down ?
23243: 00/06/18: Stephen: Re: How to cut the power disipation down ?
23244: 00/06/19: Peter Alfke: Re: How to cut the power disipation down ?
23247: 00/06/19: Rickman: Re: How to cut the power disipation down ?
23264: 00/06/19: Rickman: Re: How to cut the power disipation down ?
23276: 00/06/20: Andy Peters: Re: How to cut the power disipation down ?
23285: 00/06/21: Rickman: Re: How to cut the power disipation down ?
23295: 00/06/21: Andy Peters: Re: How to cut the power disipation down ?
23306: 00/06/21: Rickman: Re: How to cut the power disipation down ?
23277: 00/06/20: <iglasner@my-deja.com>: Re: How to cut the power disipation down ?
23287: 00/06/21: Rickman: Re: How to cut the power disipation down ?
23294: 00/06/21: <iglasner@my-deja.com>: Re: How to cut the power disipation down ?
23307: 00/06/21: Rickman: Re: How to cut the power disipation down ?
23314: 00/06/22: Hal Murray: Re: How to cut the power disipation down ?
23320: 00/06/22: Domagoj: Re: How to cut the power disipation down ?
23324: 00/06/22: Peter Alfke: Re: How to cut the power disipation down ?
23337: 00/06/22: Alex Carreira: Re: How to cut the power disipation down ?
23413: 00/06/24: Hal Murray: Re: How to cut the power disipation down ?
23329: 00/06/22: <iglasner@my-deja.com>: Re: How to cut the power disipation down ?
23255: 00/06/19: Domagoj: Re: How to cut the power disipation down ?
23260: 00/06/19: Peter Alfke: Re: How to cut the power disipation down ?
23281: 00/06/21: Harald Vefling: Re: How to cut the power disipation down ?
23284: 00/06/21: Peter Alfke: Re: How to cut the power disipation down ?
23239: 00/06/18: B. Joshua Rosen: XilinxOnLinux Howto update
23251: 00/06/19: francois.hamon: Recherche =?iso-8859-1?Q?ing=E9nieur?= telecom/FPGA
23252: 00/06/19: Jim: Does anyone know of a PC Card macro for Xilinx Spartan series?
23257: 00/06/19: Younes Leroul: Wanted: Xilinx VirtexE
23271: 00/06/20: Ray Andraka: Re: Wanted: Xilinx VirtexE
23290: 00/06/21: Lars: Re: Wanted: Xilinx VirtexE
23300: 00/06/21: Younes Leroul: Re: Wanted: Xilinx VirtexE
23258: 00/06/19: zee: cpld
23259: 00/06/19: Alun: Re: cpld
23262: 00/06/20: Jim Granville: Re: cpld
23270: 00/06/20: Steven Sanders: library not found in Foundation 2.1
23311: 00/06/21: Vikram: Re: library not found in Foundation 2.1
23312: 00/06/21: Vikram: Re: library not found in Foundation 2.1
23272: 00/06/20: Steven Derrien: Single Floating point adder ansd multiplier core
23274: 00/06/20: Eirik Esp: Powerup problem to 9500XL part @ -40 deg
23424: 00/06/24: Elftmann: Re: Powerup problem to 9500XL part @ -40 deg
23504: 00/06/27: rk: Re: Powerup problem to 9500XL part @ -40 deg
23275: 00/06/20: =?iso-8859-1?Q?=C1ngel=20Guti=E9rrez?=: PWM
23286: 00/06/21: <simonray@hotmail.com>: FFT/IFFT for FPGA
23707: 00/07/06: Ray Andraka: Re: FFT/IFFT for FPGA
23829: 00/07/12: <jadey@my-deja.com>: Re: FFT/IFFT for FPGA
23288: 00/06/21: Lars Rzymianowicz: Anyone tried the Virtex dev. board from Avnet?
23591: 00/07/02: Jiri Gaisler: Re: Anyone tried the Virtex dev. board from Avnet?
23879: 00/07/13: fred_best: Re: Anyone tried the Virtex dev. board from Avnet?
23890: 00/07/14: Lars Rzymianowicz: Re: Anyone tried the Virtex dev. board from Avnet?
23291: 00/06/21: Lars: Distributed RAM and VHDL
23335: 00/06/22: Andy Krumel: Re: Distributed RAM and VHDL
23299: 00/06/21: Xanatos: Leonardo 2000 Comments?
23310: 00/06/22: <bkk411@hotmail.com>: Re: Leonardo 2000 Comments?
23301: 00/06/21: EKC: 500 million transistor FPGA's
23303: 00/06/21: Peter Alfke: Re: 500 million transistor FPGA's
23323: 00/06/22: Austin Lesea: Re: 500 million transistor FPGA's
23332: 00/06/22: <iglasner@my-deja.com>: Re: 500 million transistor FPGA's
23339: 00/06/22: Austin Lesea: Re: 500 million transistor FPGA's
23352: 00/06/22: Rickman: Re: 500 million transistor FPGA's
23357: 00/06/23: Peter Alfke: Re: 500 million transistor FPGA's
23380: 00/06/23: Rickman: Re: 500 million transistor FPGA's
23414: 00/06/24: Hal Murray: Re: 500 million transistor FPGA's
23386: 00/06/23: <iglasner@my-deja.com>: Re: 500 million transistor FPGA's
23457: 00/06/26: Austin Lesea: Re: 500 million transistor FPGA's
23366: 00/06/23: Andrew Ince: Re: 500 million transistor FPGA's
23368: 00/06/23: <bkk411@hotmail.com>: Re: 500 million transistor FPGA's
23538: 00/06/29: Emil Blaschek: Re: 500 million transistor FPGA's
23304: 00/06/22: EKC: FPGAs for Bioinformatics accelerators
23313: 00/06/22: Christof Teuscher: Re: FPGAs for Bioinformatics accelerators
23315: 00/06/22: Steven Derrien: Re: FPGAs for Bioinformatics accelerators
23336: 00/06/22: Alex Carreira: Re: FPGAs for Bioinformatics accelerators
23338: 00/06/22: Nicholas C. Weaver: Re: FPGAs for Bioinformatics accelerators
23316: 00/06/22: Steven Sanders: JTAG for debugging on Xilinx devices?
23319: 00/06/22: Etienne Racine: Re: JTAG for debugging on Xilinx devices?
23318: 00/06/22: Phil Endecott: Xilinx PAR & Tristate busses
23334: 00/06/22: Andy Peters: Re: Xilinx PAR & Tristate busses
23321: 00/06/22: Dan Kuechle: dual processor PC for PPR - are they worth the extra cost?
23322: 00/06/22: B. Joshua Rosen: Re: dual processor PC for PPR - are they worth the extra cost?
23347: 00/06/22: Philip Freidin: Re: dual processor PC for PPR - are they worth the extra cost?
23375: 00/06/23: Bob Perlman: Re: dual processor PC for PPR - are they worth the extra cost?
23434: 00/06/25: Steve Rencontre: Re: dual processor PC for PPR - are they worth the extra cost?
23355: 00/06/23: Ray Andraka: Re: dual processor PC for PPR - are they worth the extra cost?
23385: 00/06/23: Andy Peters: Re: dual processor PC for PPR - are they worth the extra cost?
23399: 00/06/24: Steve Rencontre: Re: dual processor PC for PPR - are they worth the extra cost?
23325: 00/06/22: Peter Elliot: Looking for 'FREE' FPGA software
23326: 00/06/22: Nicholas C. Weaver: Re: Looking for 'FREE' FPGA software
23327: 00/06/22: Peter Alfke: Re: Looking for 'FREE' FPGA software
23343: 00/06/22: Carlhermann Schlehaus: Re: Looking for 'FREE' FPGA software
23348: 00/06/22: Peter Alfke: Re: Looking for 'FREE' FPGA software
23353: 00/06/22: Rickman: Re: Looking for 'FREE' FPGA software
23354: 00/06/23: Nicholas C. Weaver: Re: Looking for 'FREE' FPGA software
23571: 00/07/01: Luis Yanes: Re: Looking for 'FREE' FPGA software
23576: 00/06/30: Rickman: Re: Looking for 'FREE' FPGA software
23618: 00/07/03: Luis Yanes: Re: Looking for 'FREE' FPGA software
23365: 00/06/23: Tim Courtney: Re: Looking for 'FREE' FPGA software
23372: 00/06/23: Nicholas C. Weaver: Re: Looking for 'FREE' FPGA software
23453: 00/06/26: Tim Courtney: Re: Looking for 'FREE' FPGA software
23400: 00/06/24: Steve Rencontre: Re: Looking for 'FREE' FPGA software
23349: 00/06/23: Ulf Samuelsson: Re: Looking for 'FREE' FPGA software
23363: 00/06/23: <nodrog2@my-deja.com>: Re: Looking for 'FREE' FPGA software
23934: 00/07/16: <theidel@my-deja.com>: Re: Looking for 'FREE' FPGA software
23936: 00/07/16: rickman: Re: Looking for 'FREE' FPGA software
23945: 00/07/17: <theidel@my-deja.com>: Re: Looking for 'FREE' FPGA software
23935: 00/07/16: <theidel@advis.de>: Re: Looking for 'FREE' FPGA software
23328: 00/06/22: Peter Elliot: Looking for 'FREE' FPGA software
23330: 00/06/22: myself: Re: Looking for 'FREE' FPGA software
23333: 00/06/22: Kresten Nørgaard: VHDL - ripple carry counter
23340: 00/06/22: Peter Alfke: Re: VHDL - ripple carry counter
23342: 00/06/22: Peter Alfke: Re: VHDL - ripple carry counter
23341: 00/06/22: Asher Martin-CRAY: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23344: 00/06/22: Asher Martin-CRAY: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23733: 00/07/06: Asher Martin-CRAY: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23753: 00/07/07: Simmler Harald: Re: HOW DO YOU MANUALLY CONFIGURE AND READ CLB's ON A RUNNING FPGA???
23345: 00/06/22: <erika_uk@my-deja.com>: how to lock the lut inputs
23346: 00/06/22: <erika_uk@my-deja.com>: Re: how to lock the lut inputs
23358: 00/06/23: James Kennedy: What tools do people use for Xilinx FPGAs?
23362: 00/06/23: Nicolas Matringe: Re: What tools do people use for Xilinx FPGAs?
23367: 00/06/23: <bkk411@hotmail.com>: Re: What tools do people use for Xilinx FPGAs?
23369: 00/06/23: myself: What tools do people use for Xilinx FPGAs?
23371: 00/06/23: Nicolas Matringe: Re: What tools do people use for Xilinx FPGAs?
23370: 00/06/23: Leon Heller: Re: What tools do people use for Xilinx FPGAs?
23373: 00/06/23: Laurent Gauch: Re: What tools do people use for Xilinx FPGAs?
23377: 00/06/23: B. Joshua Rosen: Re: What tools do people use for Xilinx FPGAs?
23420: 00/06/24: <bkk411@hotmail.com>: Re: What tools do people use for Xilinx FPGAs?
23428: 00/06/24: Phil Hays: Re: What tools do people use for Xilinx FPGAs?
23379: 00/06/23: John Larkin: Re: What tools do people use for Xilinx FPGAs?
23388: 00/06/23: Muzaffer Kal: Re: What tools do people use for Xilinx FPGAs?
23395: 00/06/23: Philip Freidin: Re: What tools do people use for Xilinx FPGAs?
23405: 00/06/23: Phil Hays: Re: What tools do people use for Xilinx FPGAs?
23359: 00/06/23: Christof Paar: CHES 2000 accepted papers
23397: 00/06/24: Paul Rubin: Re: CHES 2000 accepted papers
23361: 00/06/23: <derekwallace1@my-deja.com>: Defining a reset concept for VirtexE
23378: 00/06/23: Rickman: Re: Defining a reset concept for VirtexE
23432: 00/06/25: Austin Franklin: Re: Defining a reset concept for VirtexE
23439: 00/06/25: Rickman: Re: Defining a reset concept for VirtexE
23449: 00/06/26: Austin Franklin: Re: Defining a reset concept for VirtexE
23458: 00/06/26: Rickman: Re: Defining a reset concept for VirtexE
23476: 00/06/27: Austin Franklin: Re: Defining a reset concept for VirtexE
23507: 00/06/28: Austin Franklin: Re: Defining a reset concept for VirtexE
23435: 00/06/24: Ken McElvain: Re: Defining a reset concept for VirtexE
23364: 00/06/23: <gordon.haddow@eev.com>: Atmel bidirectional pins problem
23374: 00/06/23: Rickman: Re: Atmel bidirectional pins problem
23383: 00/06/23: Andy Peters: Re: Atmel bidirectional pins problem
23376: 00/06/23: Sebastien Favard: lGen - Synthesis Library [Help manufacturer]
23381: 00/06/23: <sierratech@my-deja.com>: Looking for old Altera Application Brief Designs ab 84?
23384: 00/06/23: WU Chi Hang FOX: Xilinx xc4000
23387: 00/06/23: Peter Alfke: Re: Xilinx xc4000
23392: 00/06/23: Philip Freidin: Re: Xilinx xc4000
23411: 00/06/24: Hal Murray: Re: Xilinx xc4000
23389: 00/06/23: Rickman: Re: Xilinx xc4000
23390: 00/06/23: Peter Alfke: Re: Xilinx xc4000
23403: 00/06/24: WU Chi Hang FOX: Re: Xilinx xc4000
23406: 00/06/24: Rickman: Re: Xilinx xc4000
23391: 00/06/23: Bob Perlman: Re: Xilinx xc4000
23393: 00/06/23: Eric L: a lot of basic questions - where's the FAQ?
23394: 00/06/23: Peter Alfke: Re: a lot of basic questions - where's the FAQ?
23398: 00/06/24: Eric L: Re: a lot of basic questions - where's the FAQ?
23402: 00/06/23: B. Joshua Rosen: Re: a lot of basic questions - where's the FAQ?
23407: 00/06/24: Rickman: Re: a lot of basic questions - where's the FAQ?
23429: 00/06/24: Eric L: Re: a lot of basic questions - where's the FAQ?
23437: 00/06/25: Rickman: Re: a lot of basic questions - where's the FAQ?
23447: 00/06/25: Eric L: Re: a lot of basic questions - where's the FAQ?
23448: 00/06/25: Rickman: Re: a lot of basic questions - where's the FAQ?
23412: 00/06/24: Hal Murray: Re: a lot of basic questions - where's the FAQ?
23461: 00/06/26: Andy Peters: Re: a lot of basic questions - where's the FAQ?
23410: 00/06/24: Philip Freidin: Re: a lot of basic questions - where's the FAQ?
23430: 00/06/24: Eric L: Re: a lot of basic questions - where's the FAQ?
23396: 00/06/23: <erika_uk@my-deja.com>: F2.1i
23415: 00/06/24: <erika_uk@my-deja.com>: Re: F2.1i
23418: 00/06/24: <bkk411@hotmail.com>: Re: F2.1i
23419: 00/06/24: <erika_uk@my-deja.com>: Re: F2.1i
23421: 00/06/24: Rickman: Re: F2.1i
23451: 00/06/26: Leisure: Re: F2.1i
23401: 00/06/23: rk: CAE Software and Internet Access
23436: 00/06/24: Ken McElvain: Re: CAE Software and Internet Access
23404: 00/06/24: WU Chi Hang FOX: Different ?
23408: 00/06/24: Rickman: Re: Different ?
23416: 00/06/24: WU Chi Hang FOX: Re: Different ?
23422: 00/06/24: Rickman: Re: Different ?
23426: 00/06/24: WU Chi Hang FOX: Re: Different ?
23438: 00/06/25: Rickman: Re: Different ?
23427: 00/06/24: Philip Freidin: Re: Different ?
23431: 00/06/25: Tom Burgess: Re: Different ?
23433: 00/06/25: Tom Burgess: Re: Different ?
23473: 00/06/26: R. T. Finch: Re: Different ?
23477: 00/06/27: Rickman: Re: Different ?
23478: 00/06/27: Peter Alfke: Re: Different ?
23501: 00/06/27: R. T. Finch: Re: Different ?
23498: 00/06/27: Tom Burgess: Re: Different ?
23506: 00/06/28: Philip Freidin: I cant stand it any more.
23508: 00/06/28: Jim Granville: Re: I cant stand it any more.
23518: 00/06/28: Rick Filipkiewicz: Re: I cant stand it any more.
23521: 00/06/28: Peter Alfke: Re: I cant stand it any more.
23523: 00/06/28: R. T. Finch: Re: I cant stand it any more.
23524: 00/06/28: Tom Burgess: Re: I cant stand it any more.
23425: 00/06/24: Cory Rauch: Computer Resource
23440: 00/06/24: Shoran: How to speed it up?
23515: 00/06/28: Phil Endecott: Re: How to speed it up? :-)
23441: 00/06/25: Shoran: How to speed it up?
23450: 00/06/26: Ray Andraka: Re: How to speed it up?
23455: 00/06/26: Jerry English: Re: How to speed it up?
23442: 00/06/25: Domagoj: Amba/Daytona/PCI
23443: 00/06/25: Claas Richter: IDE-Interface for FPGA
23444: 00/06/25: Rickman: Re: IDE-Interface for FPGA
23475: 00/06/26: Bryan Williams: Re: IDE-Interface for FPGA
23534: 00/06/28: glen herrmannsfeldt: Re: IDE-Interface for FPGA
23484: 00/06/27: Rick Filipkiewicz: Re: IDE-Interface for FPGA
23445: 00/06/25: Björn Lindegren: Fpga in tristate?
23446: 00/06/25: Rickman: Re: Fpga in tristate?
23460: 00/06/26: Asher Martin-CRAY: Re: Fpga in tristate?
23452: 00/06/26: Jamil Khatib: Canadian University
23472: 00/06/26: Vikram Pasham: Re: Canadian University
23562: 00/06/30: Jamie Neilson: Re: Canadian University
23630: 00/07/03: Alan Hu: Re: Canadian University
23782: 00/07/07: Steve Oldridge: Re: Canadian University
23456: 00/06/26: Rascal: Xilinx XC5200 implementation with F2.1i
23536: 00/06/29: Jeff Graham: Re: Xilinx XC5200 implementation with F2.1i
23543: 00/06/29: Rascal: Re: Xilinx XC5200 implementation with F2.1i
23459: 00/06/26: Asher Martin-CRAY: BOUNDARY-SCAN OF INTERNAL LOGIC INSIDE A VIRTEX FPGA?
23462: 00/06/26: <erika_uk@my-deja.com>: serial 2's C add/substractor msb first
23465: 00/06/26: Peter Alfke: Re: serial 2's C add/substractor msb first
23463: 00/06/26: <louis_reginaldjean@my-deja.com>: FPGA and ASIC
23467: 00/06/26: Peter Alfke: Re: FPGA and ASIC
23481: 00/06/27: Alan Fitch: Re: FPGA and ASIC
23470: 00/06/26: Carlhermann Schlehaus: Re: FPGA and ASIC
23496: 00/06/27: Jason T. Wright: Re: FPGA and ASIC
23464: 00/06/26: Matt Gavin: inferring global buffers in Leonardo?
23471: 00/06/26: Mike Johnson: Re: inferring global buffers in Leonardo?
23497: 00/06/27: Jason T. Wright: Re: inferring global buffers in Leonardo?
23466: 00/06/26: Lars: Dual Port BlockRAM Timing (Write-Read)
23468: 00/06/26: Peter Alfke: Re: Dual Port BlockRAM Timing (Write-Read)
23469: 00/06/26: John Fielden: Virtex Demo Board
23479: 00/06/27: Tony Burch: Re: Virtex Demo Board
23516: 00/06/28: Mark Bowlby: Re: Virtex Demo Board
23756: 00/07/07: David Gilchrist: Re: Virtex Demo Board
23480: 00/06/27: Rickman: JTAG emulation of TI DSPs
23487: 00/06/27: Etienne Racine: Re: JTAG emulation of TI DSPs
23510: 00/06/28: Rickman: Re: JTAG emulation of TI DSPs
23488: 00/06/27: Eric Pearson: Re: JTAG emulation of TI DSPs
23503: 00/06/27: Mark: Re: JTAG emulation of TI DSPs
23509: 00/06/28: Rickman: Re: JTAG emulation of TI DSPs
23483: 00/06/27: DHULST: Electronic Drivers for Brushless D C Motors
23495: 00/06/27: <iglasner@my-deja.com>: Re: Electronic Drivers for Brushless D C Motors
23485: 00/06/27: Charles Brain: First time user Spartan problem
23490: 00/06/27: Rascal: Re: First time user Spartan problem
23491: 00/06/27: Charles Brain: Re: First time user Spartan problem
23492: 00/06/27: Rickman: Re: First time user Spartan problem
23494: 00/06/27: Charles Brain: Re: First time user Spartan problem
23512: 00/06/28: Charles Brain: Re: First time user Spartan problem (Panic over)
23486: 00/06/27: Christophe Heyert: configuration of RAM created with coregen
23493: 00/06/27: Andy Peters: Re: configuration of RAM created with coregen
23489: 00/06/27: Dave Vanden Bout: tutorial on configurable system-on-chip design is available
23499: 00/06/27: Eliot Friedman: Porting C to FPGA
23500: 00/06/27: Alex Carreira: Re: Porting C to FPGA
23502: 00/06/28: sriley: digital phase lock loop
23519: 00/06/28: dmac: Re: digital phase lock loop
23526: 00/06/28: sriley: Re: digital phase lock loop
23520: 00/06/28: Peter Alfke: Re: digital phase lock loop
23525: 00/06/28: sriley: Re: digital phase lock loop
23505: 00/06/27: Richard B. Katz: MAPLD 1999 Conference Proceedings
23511: 00/06/28: Dominique SZYMIK: Hanging PCI interrupt
23513: 00/06/28: SteVe: Virtex power estimation
23527: 00/06/28: Austin Lesea: Re: Virtex power estimation
23514: 00/06/28: Dominique SZYMIK: PLXMon sources
23589: 00/07/01: Joel Kolstad: Re: PLXMon sources
23766: 00/07/07: Dominique SZYMIK: Re: PLXMon sources
23517: 00/06/28: =?iso-8859-1?Q?=C1ngel=20Guti=E9rrez?=: How to do ...?
23528: 00/06/29: Jim Granville: Re: How to do ...?
23529: 00/06/28: <qianz@my-deja.com>: Xilinx Foundation Macro creation problem
23530: 00/06/28: Xanatos: PSN Generator
23531: 00/06/28: Juan-Luis L¢pez Rodr¡guez: Re: PSN Generator
23533: 00/06/28: Xanatos: Re: PSN Generator
23539: 00/06/29: Juan-Luis Lopez: RE: PSN Generator
23540: 00/06/29: Juan-Luis Lopez: RE: PSN Generator
23551: 00/06/29: Juan-Luis L¢pez Rodr¡guez: [REPOST] Bit error rate
23532: 00/06/28: Philip Freidin: Re: PSN Generator
23535: 00/06/29: Hal Murray: Re: PSN Generator
23544: 00/06/29: Xanatos: Re: PSN Generator
23537: 00/06/29: Armin Mueller: Free PCI core
23541: 00/06/29: strez: Re: Free PCI core
23547: 00/06/29: <bkk411@hotmail.com>: Re: Free PCI core
23574: 00/07/01: Steve Rencontre: Re: Free PCI core
23583: 00/07/01: Mark Aaldering: Re: Free PCI core
23542: 00/06/29: Jimmy: Maximum Speed on obtainable on FPGAs?
23546: 00/06/29: Pete Dudley: Re: Maximum Speed on obtainable on FPGAs?
23548: 00/06/29: Rickman: Re: Maximum Speed on obtainable on FPGAs?
23560: 00/06/30: <erika_uk@my-deja.com>: Re: Maximum Speed on obtainable on FPGAs?
23549: 00/06/29: <bkk411@hotmail.com>: Re: Maximum Speed on obtainable on FPGAs?
23577: 00/07/01: Hal Murray: Re: Maximum Speed on obtainable on FPGAs?
23581: 00/07/01: B. Joshua Rosen: Re: Maximum Speed on obtainable on FPGAs?
23584: 00/07/01: Peter Alfke: Re: Maximum Speed on obtainable on FPGAs?
23587: 00/07/01: Rickman: Re: Maximum Speed on obtainable on FPGAs?
23592: 00/07/02: Hal Murray: Re: Maximum Speed on obtainable on FPGAs?
23545: 00/06/29: Dan: PCI with Xilinx controller
23550: 00/06/29: <bkk411@hotmail.com>: Re: PCI with Xilinx controller
23559: 00/06/30: Olaf Birkeland: Re: PCI with Xilinx controller
23575: 00/07/01: Steve Rencontre: Re: PCI with Xilinx controller
23552: 00/06/29: Eric L: Buying Xilinx Chips online?
23564: 00/06/30: Pete Dudley: Re: Buying Xilinx Chips online?
23553: 00/06/29: gary: MPEG audio questions...
23613: 00/07/02: Lars: Re: MPEG audio questions...
23661: 00/07/04: gary: Re: MPEG audio questions...
23673: 00/07/05: Bernhard Josef Rieder: Re: MPEG audio questions...
23825: 00/07/11: gary: Re: MPEG audio questions...
23675: 00/07/05: Savekar Santosh: Re: MPEG audio questions...
23826: 00/07/11: gary: Re: MPEG audio questions...
23554: 00/06/30: <baneshwar_s@my-deja.com>: delta in timing report
23555: 00/06/30: Simon Zhang: Who to synthesis?
23556: 00/06/30: Andreas C. Doering: RE: Simulating Coregen AsyncFifo with Synopsys VSS
23557: 00/06/30: Steve: Re: Which notebook is for you?
23567: 00/06/30: Don: Re: Which notebook is for you?
23578: 00/06/30: Branko Badrljica: Re: Which notebook is for you?
23585: 00/07/01: John Larkin: Re: Which notebook is for you?
23580: 00/07/01: Steve: Re: Which notebook is for you?
23586: 00/07/01: ~Mike Turco: Re: Which notebook is for you?
23588: 00/07/01: John Larkin: Re: Which notebook is for you?
23632: 00/07/04: Gregg C Levine: Re: Which notebook is for you?
23558: 00/06/30: Andreas Wstefeld: There is no output on pins
23561: 00/06/30: Steven Derrien: Re: There is no output on pins
23563: 00/06/30: Simon Bilodeau: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23565: 00/06/30: Simon Bilodeau: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23568: 00/06/30: Andy Peters: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23566: 00/06/30: Alun: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23573: 00/06/30: G. Hobson Frater: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23660: 00/07/04: Simon Bilodeau: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23741: 00/07/06: <channing@my-deja.com>: Re: Problem with uploading in XC95288 using ISP with HW-JTAG-PC
23569: 00/06/30: Pete Dudley: Viewlogic schematic from Synplify edif output?
23570: 00/06/30: Rickman: Re: Viewlogic schematic from Synplify edif output?
23572: 00/07/01: Simon: Re: Viewlogic schematic from Synplify edif output?
23582: 00/07/01: Rickman: Re: Viewlogic schematic from Synplify edif output?
23593: 00/07/02: Philip Freidin: Re: Viewlogic schematic from Synplify edif output?
23594: 00/07/02: Philip Freidin: Re: Viewlogic schematic from Synplify edif output?
23595: 00/07/02: Rickman: Re: Viewlogic schematic from Synplify edif output?
23599: 00/07/02: Simon: Re: Viewlogic schematic from Synplify edif output?
23610: 00/07/02: Rickman: Re: Viewlogic schematic from Synplify edif output?
23692: 00/07/05: Andy Peters: Re: Viewlogic schematic from Synplify edif output?
23695: 00/07/05: Rickman: Re: Viewlogic schematic from Synplify edif output?
23705: 00/07/06: Ray Andraka: Re: Viewlogic schematic from Synplify edif output?
23714: 00/07/05: Rickman: Re: Viewlogic schematic from Synplify edif output?
23691: 00/07/05: Pete Dudley: Thanks for the tip
23723: 00/07/06: Philip Freidin: Using LUTs in Virtex with ViewDraw and ViewSim
23730: 00/07/06: Pete Dudley: Re: Using LUTs in Virtex with ViewDraw and ViewSim
23731: 00/07/06: Rickman: Re: Using LUTs in Virtex with ViewDraw and ViewSim
23772: 00/07/07: Philip Freidin: Re: Using LUTs in Virtex with ViewDraw and ViewSim
23743: 00/07/06: Don Husby: Re: Using LUTs in Virtex with ViewDraw and ViewSim
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