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Hi everyone! I have a problem for using Logic Simulator in Xilinix Foundation F.2.1i. I don't know what is "simulator Mode". The option of "simulator Mode" is following. "Chip Controlled, Override, Disconnected, Connected" How do these mode operate? Thank you for reading my question!Article: 23001
optimagic is back! Patrick Schulz <schulz@rumms.uni-mannheim.de> wrote in message news:393E6BF8.E7E93EBE@rumms.uni-mannheim.de... > Philip Freidin wrote: > > > > I had the honor of talking to Mr. Optimagic today, and asked if he was > > aware that his web presence was sub-optimal. He told me that he was aware > > of the problem (incompetence at network solutions), and that he hoped > > that things would be restored in a day or two. > > > > Ping early, and Ping often: www.optimagic.com > > > > Philip Freidin > > Why didn't you post the resurrection of optimagic? > I think thats more efficient than polling ;-) > > > Patrick > -- > Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org) > University of Mannheim - Dep. of Computer Architecture > 68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de > Phone: +49-621-181-2720 Fax: +49-621-181-2713Article: 23002
rk <stellare@nospamplease.erols.com> wrote in message news:393F7C9A.543D9409@nospamplease.erols.com... > Frank Madison wrote: > > > I hope that this situation seems familiar to someone with more vhdl/fpga > > experience than I. If it does, I would be interesting in seeing your opinion > > or advice. > > Not too familiar with this exact problem but interesting trouble you have. :-) > > ================================= > > > I have just completed the design of a data acquisition system that > > incorporates two Actel parts: a 40mx04 and a 42mx09. The development tools > > that I used are the "Actel DeskTop". They include a subset of Synplicity. I > > have found that Synplicity makes only limited use of the library macros in > > 40mx compilation as compared to 42mx compilations. > > Remember that the 40mx is really an Act 1 architecture and a 42mx is an Act 2 > architecture. The 40mx, for combinational logic, has a slightly different logic > element than the 42mx. (the two muxes up front have separate selects in Act 1; > in Act 2, they give you an extra AND gate on one of the mux selects, making it a > bit better for up and down counters. Often, the Act 1 element seems to be more > useful and powerful). > > ====================================== > > > A specific example is that 42mx outputs will include and2, and2a, and and2b > > while the 40mx output will contain only and2. and2a and and2b are both > > available in the 40mx macro library, and they are implemented in a single > > cell. An and2a is a 2-input and gate with one of the inputs inverted; the > > and2b has both inputs inverted. To implement the equivalent of an and2a > > in 40mx, Synplicity creates an inverter and an and2. The problem here is, > > of course, that 2 cells instead of 1 are needed, and there is a greater > > propogation delay. > > > > The back-end Actel "place and route" tools evidently take care of some, but > > not all, of this problem in post-systhesis optimization. I have verified this > > by synthesizing the same behavioral VHDL code using both 40mx and 42mx > > compilers. In instances where the 42mx compiler has output macros that are > > not available in the 40mx library, I edited the structural output by > > instantiating equivalent 40mx macros or macro combinations. I then > > processed both structural outputs through the Actel back-end tools. The code > > that was processed with the 42mx Synplicity compiler produced smaller and > > faster outputs. The performance was verified under simulation > > (in ModelSim) and in actual hardware implementation. > > There is an optimizer in the Combiner which tries to eliminate logic that is not > necessary and will handle a bunch of these things. Another trick is to take the > output of the VHDL synthesizer and then run it through Actmap, in netlist > optimizer mode. It has been shown for some VHDL synthesizers that this will > produce very large performance gains; for others, it has almost no effect. It > depends on the structure of the logic generated by the synthesizer. > > ============================================== > > > Being relatively new to fpga design, I initially suspected that deficiencies > > in the size and performance of my designs were due to my limited experience > > with and knowledge of the process. I scrutinized my work thoroughly before > > looking at the perfomance of my tools. Does my assesment seem to be valid? > > Have any of you had these experiences? And, if so, what approach enabled you > > to overcome the problems? > > It seems that you have looked at this carefully and it does seem to be valid. > If you have some free time on your hands, you can try running the code using Act > 3 and SX technologies. Act 3 is the same as Act 2 with the addition of > another input to the S-module so that the clear signal isn't shared, helping > combinability. The SX does have a more powerful logic module. > > In one test that was run with a particular version of software, it was found > that setting the target to Act 3, with the less powerful logic module, got > better results, for a purely combinational design, than SX. Why was this? SX > was new and all the algorithms were not yet implemented in that version of the > software. I suspect, but have no evidence, that this may be the source of your > problem. Act 1/40MX are relatively small devices and as such have the least > suitability for HDL synthesis. Also, the Act 1 module is different, by a bunch, > from Act 2 and Act 3. So, given limited resources, one can suspect that > Synplicity, at least for the version that you have, simply did not put much time > in developing and optimizing their synthesis engine for Act 1 technology. Did > the Synplicity folks have anything else to say about this? > Way back at Synplify version 3.0 Act2 and Act3 were supported but not Act1. At the time the Actel place and route would convert between Act2 and Act1 so it was not a big hurdle. (Does it still do that?). Perhaps this indicates the algorithms for Act1/40MX have had less time to mature (less effort put into them). Did Act1 support only turn up with 40MX support? I didn't notice. > Here are some options that may enable you to eliminate your problem. > > 1. Like the old joke with the doctor, how to fix the problem when your > arm hurts when you lift it funny, don't do that. How about using the > A1225A (or whatever the 42MX equivalent is) instead of the 40MX > device, as these are comparable device densities. This will actually > help you out in board level simulations since they will both reference > the same Actel models. > > 2. Design with schematics. > > 3. If you did not update to the latest version of software, use the > freebie Actel VHDL synthesizer, Actmap. For combinational logic, this > seems to be the best tool for synthesis (although I most use it for > Act 2/3/SX). > > > Thanks for looking this over, > > No problem, interesting story. > > Have a good day, > > ---------------------------------------------------------------------- > rk But Mother Nature, unlike Congress > stellar engineering, ltd. and the press and even the space > stellare@erols.com.NOSPAM workers, can't be bluffed. > Hi-Rel Digital Systems Design -- James Oberg, 2000 > >Article: 23003
I'm looking for someone with experience in FPGA design and familiarity with data communication protocols. I have a job in California that I need to fill ASAP. Does anyone know someone like this? I appreciate any help! Also, if anyone can tell me a little bit about some of the different FPGA design tools, I'd appreciate that, too. Thanks, Michelle Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23004
Domagoj wrote: > > I've assumed that , but it still doesn't make sense to me. Xilinx probably > wants to squeeze every last drop of juice from plain old Virtex , so why > would they sell better chips cheaper. This doesn't help them selling > plain Virtex , except if someone needs 5V tolerant IOs. > Some people are never happy! Here we offer better parts at a lower price, and there still are complaints. This industry believes in rapid price reduction ( while maintaining reasonable margins). We are not entirely altruistic; we know that lower prices expand our market, not only against the direct competitors, but more importantly against the big ASIC market. We want to reduce prices, so we can sell more parts, since the FPGA market is very price-elastic. In order to lower the price, we have to lower our cost, and we do that by redesigning to smaller geometries, which today means to a lower supply voltage. And we then offer these smaller, faster, "better" parts at a lower price. But nobody can expect us to lower the price on the older, bigger, more-expensive to manufacture parts at the same rate. In the past, we could redesign for smaller geometries and thus lower cost, without affecting the basic device parameters, like Vcc. That is no longer possible, and it leads to the accelerated rate of introduction of new device types and even families. It also leads to better and faster devices being cheaper than their 1-year-old ancestors. Blame the laws of physics if you feel like blaming something. Just my $0.02 worth. Peter AlfkeArticle: 23005
Peter Alfke <peter@xilinx.com> wrote in message
news:393FDC6E.D345CCC0@xilinx.com...
> Some people are never happy!
> Here we offer better parts at a lower price, and there still are
complaints.
No, it's not a matter of happiness , I'm just curious . This is not a
complaint .
> In order to lower the price, we have to lower our cost, and we do that by
> redesigning to smaller geometries, which today means to a lower supply
> voltage. And we then offer these smaller, faster, "better" parts at a
lower
> price. But nobody can expect us to lower the price on the older, bigger,
> more-expensive to manufacture parts at the same rate.
That's true . But then XCV family might have a very short living cycle .
> In the past, we could redesign for smaller geometries and thus lower cost,
> without affecting the basic device parameters, like Vcc. That is no longer
> possible, and it leads to the accelerated rate of introduction of new
device
> types and even families.
> It also leads to better and faster devices being cheaper than their
> 1-year-old ancestors.
Recently the prices of XCV-E devices came down a little bit.
So , how much cheaper could become XCV-E devices in a year ?
> Blame the laws of physics if you feel like blaming something.
:-)
regards,
Domagoj
Domagoj@engineer.com
Article: 23006Domagoj wrote: > But then XCV family might have a very short living cycle . Let me assure you that this has nothing to do with the length of time that the parts will be available. We keep devices available for a very long time. (XC6200 was the exception, since it was a commercial flop). > Recently the prices of XCV-E devices came down a little bit. > So , how much cheaper could become XCV-E devices in a year ? Well, you already indicated the direction. Ask your sales channel. I am willing to stick my head out on technical matters, but not on pricing. Life is too precious! :-) Peter Alfke, Xilinx ApplicationsArticle: 23007
The question would be...WHY? TTL functionality is based largely on the pin count of available packaging. TTL functions map pretty poorly into high density devices such as FPGAs and ASICs. You might recall when FPGAs first came out, most of the vendors offered libraries that consisted largely of TTL functions. That went a long way toward the attitude that FPGAs were too slow for many applications and were hard use. As with any good design, you really should be designing to the architecture to get reasonable densities and speeds. Certainly, you should not be using the functionality dictated in large part by very limited pin counts. Jim Granville wrote: > Hello, > I am looking for TTL device libraries (macros), ideally in CUPL, but > other HDL's would do.. > There must be dusty archives of these things somewhere.. > CUPL comes with only about 30 TTL equiv macros, other systems > may come with more.. > TIA - Jim G. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23008
Hi everyone!
I have problem for serious pad to pad delay in Virtex.
My development environment is following.
software: Foundation 2.1i
device : Virtex
language : VHDL
In my design, there is a part which only receive the external clock and
bypass to output pad.
In vhdl source, it appears like a following.
ENTITY MyDesign IS
PORT(
ClkIn: IN STD_LOGIC;
ClkOut : Out STD_LOGIC;
.
.
.
);
END ;
ARCHITECTURE arch_MyDesign OF MyDesign IS
BEGIN
Clkout <= Clkin;
.
.
.
END;
In timing simulator, Clkout appears as delayed Clkin.
But Delay is 15ns ,although My Clkin is 25MHz.
So My Design does not operate properly.
Why does this serious pad delay occur?
How can I reduce this pad delay?
Article: 23009Make sure the path environment variable isn't too long (128 chars max). "Seiya" <valid@email.address.com> wrote in message news:OYVt$EJ0$GA.311@cpmsnbbsa07... > Hey, I bought a copy of Xilinx Foundation Student Ed. > and went through the registration process, received the stuff > for license.dat. I then plugged it into the path it should be by the command > line parameter, and I am not able to run anything other than Xilinx Design > manager. (Even then, when it starts to init, it gives errors) Generally the > error is that there are no "server" lines in my license.dat however, this > means very little to me other than "no im not going to work." > Any ideas on what I might have missed? > > (I've done the web-support, but have yet to get a response) > _seiya_ @ nergal.org (just remove spaces) > > for the spam bots, try abuse@fbi.gov > > >Article: 23010
I have a design problem right now concerning the state machine. I am using synplicity and target to Altera Flex10K30E device. My problem is, if I were to pull the state bits out to observe which state I am stuck at, then the whole thing is running. But if I do not pull the state bits out, the circuit just won't work at all. I am guessing it is timing problem but do not know how to solve this. Can someone help? SherdynArticle: 23011
I guess the question is, what are you trying to accomplish by passing the clock through the chip? Unless you are tying to compensate for an asynchronous delay there is no reason to do this, and trying to compensate for an asynchronous delay will not really work the way you would like it to. So the solution to your problem is to just feed one clock (the one being input to your FPGA) to all of the circuits on your board and clocking the inputs and outputs of the FPGA from this clock. ÀÓÀçȯ wrote: > > Hi everyone! > > I have problem for serious pad to pad delay in Virtex. > > My development environment is following. > > software: Foundation 2.1i > device : Virtex > language : VHDL > > In my design, there is a part which only receive the external clock and > bypass to output pad. > > In vhdl source, it appears like a following. > > ENTITY MyDesign IS > PORT( > ClkIn: IN STD_LOGIC; > ClkOut : Out STD_LOGIC; > . > . > . > ); > END ; > > ARCHITECTURE arch_MyDesign OF MyDesign IS > BEGIN > Clkout <= Clkin; > . > . > . > END; > > In timing simulator, Clkout appears as delayed Clkin. > But Delay is 15ns ,although My Clkin is 25MHz. > So My Design does not operate properly. > > Why does this serious pad delay occur? > How can I reduce this pad delay? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23012
Ray Andraka wrote: > > The question would be...WHY? I knew someone would ask that :-) It's for training purposes, rather than real coal face design. It allows beginners to hold a given TTL device in their hands, and then see the same functional logic in HDL form. If they already know Gates/Muxs/Ctrs by number, it can be a faster way to ramp up than a HDL manual. They also make a good worked example/lesson. > TTL functionality is based largely on the pin count of available > packaging. TTL functions map pretty poorly into high density devices > such as FPGAs and ASICs. You might recall when FPGAs first came out, > most of the vendors offered libraries that consisted largely of TTL > functions. That's what I'm after - something that might have come with PALASM, AMAZE, SNAP, Slice or others... Even finding these older packages is not easy. I found one link to PALASM, but it went to a dead end. As you say, out of fashion these days.... - Jim G.Article: 23013
This is a question for anyone who has experience rolling a Synopsys'
FPGA Compiler (FC) license into one for FPGA Compiler II (FCII):
A few years ago, we bought FC. This tool looks & feels like Design
Compiler (DC, for ASICs), but w/ special FPGA synthesis algorithms. When
we bought it, the 'bill of sale' actually breaks it down into multiple
components:
1) FPGA VHDL package
(1a) FPGA Compiler [actual synthesis engine?]
(1b) VHDL Compiler [HDL to Synopsys internal format converter]
(1c) Design Analyzer [GUI]
2) HDL Advisor [is my code synthesis friendly, efficient?]
3) Designware Foundation Library [datapath, module generator?]
..... for which the bill of sale itemized purchase cost seperate from
annual maintenance cost, for each component. Presently, annual
maintenance for all this costs $33k for 1 license. To make a long story
less long, we are now trying to roll this license into FCII, a tool that
is based on FPGA Express (but with DC scripting compatibility added). It
appears that FCII has all of the components listed above, except HDL
Advisor (now RTL Analyzer), built-in "under the hood", not broken out
seperately as FC did. This raises issues/questions that I'm having a
hard time getting confident answers from Synopsys on:
-- Does FCII really have all of the FC components built-in under the
hood (including designware), or is it, too, a bare-bones product for
which you have to buy lots of 'bolt-ons' to turn it into the deluxe
model? The $5k maintenance cost of FCII sure looks more attractive than
the $33k maintenance cost of FC (63% of which is for Designware) .....
we could buy more licenses w/ the savings. Is this really the same
value? (i.e., if it looks too good to be true, it probably is)
-- Is Designware Foundation Library a requirement to do module
generation (adders, multipliers, etc.,) or does it just give you more
efficient implementations of datapath components? How necessary is it?
--
========================
William Lenihan
lenihan3we@earthlink.net
========================
Article: 23014Well, thats the sad conclusion I came to. Please help and proove me wrong. Here is why I made the above statement: Having a large design (about 50K gates) and trying to use the SelectRam blocks (or any other coregen IP blocks) makes it impossible to synthesise the design with 'FPGA Compiler II' from synopsys, as all timing requirements of those blocks are ignored. All nets connecting to such a black box are not optimized (or very poorley optimized). So, that makes the RAMs useless, as I can not meet timing using them them. Perhapst I'm doing something wrong, may be there is a "trick" how to get FPGA compiler to consider timing contrains on those "black boxes" ??? Any help appreciated ! bkk Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23015
Hello, I have tried to simulate dual port BLOCKRAM (VIRTEX) in ModelSim 5.4a. I am experiencing problems with the write operation. It appears that the write data has to delayed by 1 cycle compared to the address and control signals. This seems very odd. I have contacted Xilinx and they claim this should not be happening. Has anyone had similar problems? Thanks Pete Little.Article: 23016
Hi everybody, I was wondering if anyone has ever used the DLL's in the virtex FPGA. I can't find the solution of how to code a divider in VHDL. I have only found multiplications. Does someone ever tried this before, and if so, can you give an example Thanks ChristopheArticle: 23017
The UK's Educational Electronics CAD User Group (EEUG) is holding a workshop in September titled "Embedded Systems and Hardware/Software co-design". The workshop will address experience of embedded systems teaching in higher education, and related matters. For the purposes of the workshop, "Embedded Systems" is taken in its widest sense, including programmable logic systems as well as microcomputer and microprocessor systems. EEUG particularly hopes to include coverage of hardware/software co-design issues in the workshop. Contributions of around 20 minutes in length, and informal in nature, are sought. Please see <http://www.eeug.ecs.soton.ac.uk/sep00/cfc.htm> for further details. -- Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UKArticle: 23018
About 7 years ago I worked in a large english electric company which was very general. We had a standard board with a clock some monostables , some drivers and a MAX5128 which ran the show. I found myself debugging the crappiest EPLD design the world has ever seen because a guy in a slightly remote office chose to spend 30 seconds learning about max plus 2 and the 5128 architecture and three months putting about 30 ttl macros onto a single enormous sheet of "paper". He was counting to 12 using a 4 bit counter some and gates and asynchronously resetting the counter! etc etc. I really, really think that you are making a mistake to go down this road, your students will not learn how do do design properly at all. LOGIC - not recommended for new designs :) Rob Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23019
It is a bit of a pointless thing to do, but if you must... why not use a DLL, you you should be able to lock the clocks together pretty closely. Check out the Xilinx web site for an apps note on clock distribution using DLL's Cheers Chris Rickman wrote: > I guess the question is, what are you trying to accomplish by passing > the clock through the chip? Unless you are tying to compensate for an > asynchronous delay there is no reason to do this, and trying to > compensate for an asynchronous delay will not really work the way you > would like it to. > > So the solution to your problem is to just feed one clock (the one being > input to your FPGA) to all of the circuits on your board and clocking > the inputs and outputs of the FPGA from this clock. > > ÀÓÀçȯ wrote: > > > > Hi everyone! > > > > I have problem for serious pad to pad delay in Virtex. > > > > My development environment is following. > > > > software: Foundation 2.1i > > device : Virtex > > language : VHDL > > > > In my design, there is a part which only receive the external clock and > > bypass to output pad. > > > > In vhdl source, it appears like a following. > > > > ENTITY MyDesign IS > > PORT( > > ClkIn: IN STD_LOGIC; > > ClkOut : Out STD_LOGIC; > > . > > . > > . > > ); > > END ; > > > > ARCHITECTURE arch_MyDesign OF MyDesign IS > > BEGIN > > Clkout <= Clkin; > > . > > . > > . > > END; > > > > In timing simulator, Clkout appears as delayed Clkin. > > But Delay is 15ns ,although My Clkin is 25MHz. > > So My Design does not operate properly. > > > > Why does this serious pad delay occur? > > How can I reduce this pad delay? > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23020
In article <39407293.69C7@designtools.co.nz>, Jim Granville <jim.granville@designtools.co.nz> writes: > Ray Andraka wrote: >> >> The question would be...WHY? > > I knew someone would ask that :-) > > It's for training purposes, rather than real coal face design. > It allows beginners to hold a given TTL device in their hands, and > then see the same functional logic in HDL form. > > If they already know Gates/Muxs/Ctrs by number, it can be a faster > way to ramp up than a HDL manual. > > They also make a good worked example/lesson. > >> TTL functionality is based largely on the pin count of available >> packaging. TTL functions map pretty poorly into high density devices >> such as FPGAs and ASICs. You might recall when FPGAs first came out, >> most of the vendors offered libraries that consisted largely of TTL >> functions. > > That's what I'm after - something that might have come with PALASM, > AMAZE, SNAP, Slice or others... > Even finding these older packages is not easy. > I found one link to PALASM, but it went to a dead end. > > As you say, out of fashion these days.... > > - Jim G. Don't know if this is quite suitable, but the Free model Foundation has VHDL/VITAL models of a lot of logic devices, presumably for board rather than FPGA representation. (http://www.vhdl.org/fmf/wwwpages/fmf_models.html) However the VITAL rather obscures the VHDL ... HTH Kim CarterArticle: 23021
rob_dickinson@my-deja.com wrote: > > About 7 years ago I worked in a large english electric company which > was very general. We had a standard board with a clock some > monostables , some drivers and a MAX5128 which ran the show. I found > myself debugging the crappiest EPLD design the world has ever seen > because a guy in a slightly remote office chose to spend 30 seconds > learning about max plus 2 and the 5128 architecture and three months > putting about 30 ttl macros onto a single enormous sheet of "paper". > He was counting to 12 using a 4 bit counter some and gates and > asynchronously resetting the counter! etc etc. > > I really, really think that you are making a mistake to go down this > road, your students will not learn how do do design properly at all. > > LOGIC - not recommended for new designs :) Sounds, in fact, like your 'guy' would have benefited from what we are trying to do. We do not want Schematic symbols, but TTL Macros, and these are used as training examples - so that TTL users get familar with HDL syntax as fast as possible, otherwise there is a very real temptation to do exactly what occured above. It is very hard to change a way of thinking overnight, and rather than throw away their experience, we prefer to 'steer' it towards HDL/PLD. Schematics are OK for system flow, but can get very clumsy at lower levels, and have poor revision audit features. ( not to mention encouraging the instance above :-) - Jim G.Article: 23022
Hi, Go to http://www.xilinx.com/apps/virtexapp.htm#appnotes and look at xapp132. "Christophe Heyert" <heyertc@rsd.bel.alcatel.be> a écrit dans le message news: 3940AEC9.8073F9CC@rsd.bel.alcatel.be... > Hi everybody, > > I was wondering if anyone has ever used the DLL's in the virtex FPGA. > I can't find the solution of how to code a divider in VHDL. > I have only found multiplications. > Does someone ever tried this before, and if so, can you give an example > Thanks > > ChristopheArticle: 23023
<bkk411@my-deja.com> wrote in message news:8hq4vm$cal$1@nnrp1.deja.com... > Having a large design (about 50K gates) and trying to use > the SelectRam blocks (or any other coregen IP blocks) > makes it impossible to synthesise the design with > 'FPGA Compiler II' from synopsys, as all timing requirements > of those blocks are ignored. All nets connecting to such a > black box are not optimized (or very poorly optimized). > So, that makes the RAMs useless, as I can not meet timing > using them. Same with Leonardo > Perhaps I'm doing something wrong, may be there is a "trick" > how to get FPGA compiler to consider timing contrains on those > "black boxes" ??? You should be able to read the EDIF for the Coregen RAM into the Synthesis tool to fill in the black box (but keep it in 'do not touch' mode), but this had problems due to be cured with the new Spectrum version. Mentor alternatively suggested constraining internal signals to my multiple black box Coregen RAMs to prevent poor optimisation. Andrew InceArticle: 23024
In article <3940C675.5157@designtools.co.nz>, jim.granville@designtools.co.nz wrote: > rob_dickinson@my-deja.com wrote: > > > > About 7 years ago I worked in a large english electric company which > > was very general. We had a standard board with a clock some > > monostables , some drivers and a MAX5128 which ran the show. I found > > myself debugging the crappiest EPLD design the world has ever seen > > because a guy in a slightly remote office chose to spend 30 seconds > > learning about max plus 2 and the 5128 architecture and three months > > putting about 30 ttl macros onto a single enormous sheet of "paper". > > He was counting to 12 using a 4 bit counter some and gates and > > asynchronously resetting the counter! etc etc. > > > > I really, really think that you are making a mistake to go down this > > road, your students will not learn how do do design properly at all. > > > > LOGIC - not recommended for new designs :) > > Sounds, in fact, like your 'guy' would have benefited from what we > are trying to do. > > We do not want Schematic symbols, but TTL Macros, and these are used > as training examples - so that TTL users get familar with HDL syntax > as fast as possible, otherwise there is a very real temptation to > do exactly what occured above. > > It is very hard to change a way of thinking overnight, and rather than > throw away their experience, we prefer to 'steer' it towards HDL/PLD. > > Schematics are OK for system flow, but can get very clumsy at lower > levels, > and have poor revision audit features. > ( not to mention encouraging the instance above :-) > > - Jim G. Maybe the best way forward is to write the macro's yourself in vhdl. This will take no time at all and would then allow you to show examples of making minor changes to counters etc as an incremental way of getting them to do pld design "properly", I assume that you will have moved away from ttl equivalence before introducing state machines anyway. Rob Sent via Deja.com http://www.deja.com/ Before you buy.
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