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Hi All! I want to make my own xchecker cable. Is it possible ? Can I copy an original cable? Thanks, Arnold /Electrical Engineer Student/Article: 20801
Hi Folks, Can Virtex BlockRAMs be configured as asynchronous RAMs??? I have an application with big LUT (10-16 Input). For internal reasons, this LUT has to be asynchronous. Using XC4000 (I have XC4010E chip) for that would simply not give me the proper speed. I am thinking about using Virtex BlockRAMs for that. However, it seems it is synchronous?! Please help!Article: 20802
What the heck is bit serial arithmetic?Article: 20803
"J.R." wrote: > > Hi Folks, > > Can Virtex BlockRAMs be configured as asynchronous RAMs??? > I have an application with big LUT (10-16 Input). For internal reasons, this > LUT has to be asynchronous. Using XC4000 (I have XC4010E chip) for that > would simply not give me the proper speed. I am thinking about using Virtex > BlockRAMs for that. However, it seems it is synchronous?! > > Please help! I don't think you can use the block rams as async rams. In fact I believe that Peter Alfke said they are sync on both the write and the reads. The LUT rams in the older families can be async, but some of the newer families such as the Spartan can't use the LUTs as async rams. But the LUT are async on the reads in all families. Only the write is synchronous. You might try to look at your problem again. See if you can find a way to decompose the solution so that it can be made of smaller rams that can be cascaded. Or can you use an external SRAM? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20804
Rickman wrote: > "J.R." wrote: > > > > Hi Folks, > > > > Can Virtex BlockRAMs be configured as asynchronous RAMs??? > > I have an application with big LUT (10-16 Input). For internal reasons, this > > LUT has to be asynchronous. Using XC4000 (I have XC4010E chip) for that > > would simply not give me the proper speed. I am thinking about using Virtex > > BlockRAMs for that. However, it seems it is synchronous?! > > > > Please help! > > I don't think you can use the block rams as async rams. In fact I > believe that Peter Alfke said they are sync on both the write and the > reads. Correct, synchronous only > > > The LUT rams in the older families can be async, but some of the newer > families such as the Spartan can't use the LUTs as async rams. for writing. Read in LUT-RAM is always, in all families, asynchronous=combinatorial. Peter Alfke > But the > LUT are async on the reads in all families. Only the write is > synchronous. > > You might try to look at your problem again. See if you can find a way > to decompose the solution so that it can be made of smaller rams that > can be cascaded. Or can you use an external SRAM? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 20805
It, the heck, is when you perform arithmetic serially, one bit at a time, LSB first, instead of on parallel words. Got it ? B-I-T--S-E-R-I-A-L Peter Alfke "E. Robert Tisdale" wrote: > What the heck is bit serial arithmetic?Article: 20806
This on-line document from the FAA is a decent primer on good design practices and testing of FPGAs and ASICs: http://av-info.faa.gov/software/Cmplx_Hdwr/DOT_Report.pdf "DESIGN, TEST, AND CERTIFICATION ISSUES FOR COMPLEX INTEGRATED CIRCUITS" (DOT/FAA/AR-95/31) -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20807
Uhh, I suppose you gave this answer simply because it was E.Bob who asked, but have never dunnit either. Except of course things like LFSRs, encryption and error correction algorithms, which are bit serial to some extent. Care to give an example? Cheers, Herman http://www.AerospaceSoftware.com Peter Alfke wrote: > > It, the heck, is when you perform arithmetic serially, one bit at a > time, LSB first, instead of on parallel words. > Got it ? B-I-T--S-E-R-I-A-L > > Peter Alfke > > "E. Robert Tisdale" wrote: > > > What the heck is bit serial arithmetic?Article: 20808
It's not a trivial design. It's got an XC3042 FPGA in it among other things. Fuzesi Arnold wrote: > Hi All! > > I want to make my own xchecker cable. > > Is it possible ? > > Can I copy an original cable? > > Thanks, > Arnold > /Electrical Engineer Student/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20809
The arithmetic is performed one bit per clock cycle, so that it takes N clock cycles to perform an N bit wide operation. For straight arithmetic operations, it is usually done LSB first since arithmetic operations are left transitive. Occasionally there are times when an MSB first bit serial operation is desirable, such as priority encodes, compares and first one's detections. e-bob, I bet you are thinking, well geez, that's pretty inefficient. True it takes more clock cycles to perform an operation, but you get the advantage of a much smaller circuit (1/Nth the size in the general case, and often even smaller). For example, a bit-serial adder is a 3 input XOR gate, a majority-3 gate and two flip-flops. That can be done in a pair of FPGA logic elements. Since you don't have wide fanout controls or long carries, the clock rate can be quite a bit higher than the clock for more conventional bit-parallel arithmetic. In many cases, the time-hardware product for a bit serial design is smaller than the equivalent bit-parallel design (meaning you get the same performance in a smaller area). Modern FPGAs are capable of clock rates of well over 100MHz, which is much higher than the data rates on typical applications slated for FPGAs in today's market. If you do a parallel design for a relatively low data rate, say 10 MHz, you leave alot of the FPGA's capability on the table so you might be passing up an opportunity for a much smaller device. "E. Robert Tisdale" wrote: > What the heck is bit serial arithmetic? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20810
Rickman, Saying QuickBooks (which is what I use) and MRP / integrated capabilities seems quite a stretch when you consider the price of the packages. If you're just starting out, what's really wrong with simply buying in two categories: 1) reeled parts that come in relatively large quantities but aren't cost drivers. 2) all the others that you'll probably buy for each production lot. Just buy them off the BOM. It's not that big a deal. If you really want to be prepared to be a much bigger company then you'll probably be investing in all sorts of infrastructure around the MRP system. It all revolves around how much you're willing to invest in software and infrastructure. I'll be interested to see if someone recommends an inexpensive MRP package here as well. I had a survey article that I may be able to retrieve. email me if you're interested. Regards, -- Fred Marshall Mission Systems, Inc. http://fcmarshall.home.mindspring.com http://www.pengroup.com/affiliates/missionsystems/ Rickman <spamgoeshere4@yahoo.com> wrote in message news:38B2F23D.C424DE1E@yahoo.com... > I have started a company to make several DSP boards and I am looking for > a program to manage the parts procurement and tracking for manufacturing > these boards. As it turns out, I am spending more time dealing with the > management of the process than I am the engineering. A good MRP program > would help me enormously. > > It would also be good if it included or interfaced to an accounting > package. I have considered using Quick Books for accounting simply > because that is recommended by my accountant. > > Anyone involved in the support of manufacturing that can offer some > advice? > > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 20811
Pity! May be I can clock the BlockRAM in the falling edge of the clock. I need a speed of 70MHz (T~14ns). If I clock the BlockRAM at the falling edge, that gives me 7ns for the set-up time. I think this is sufficient. What do you reckon? I cannot use any external logic (e.g. SRAM) to implement this a LUT. Everything has to be on-chip.... Cheers.Article: 20812
"E. Robert Tisdale" wrote: > > What the heck is bit serial arithmetic? Try to find documentation on the PDP8S. That was a bit serial machine. Some old IC logic books have spec sheets for bit serial adders. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20813
Herman wrote: > > Uhh, I suppose you gave this answer simply because it was E.Bob who > asked, but have never dunnit either. Except of course things like > LFSRs, encryption and error correction algorithms, which are bit serial > to some extent. Care to give an example? > > Cheers, > > Herman > http://www.AerospaceSoftware.com > > Peter Alfke wrote: > > > > It, the heck, is when you perform arithmetic serially, one bit at a > > time, LSB first, instead of on parallel words. > > Got it ? B-I-T--S-E-R-I-A-L > > > > Peter Alfke > > > > "E. Robert Tisdale" wrote: > > > > > What the heck is bit serial arithmetic? An adder has three inputs - addend.1, addend.2, and carry -- and two outputs -- sum and carry. The combinatorial logic consists of two XORs, aka half adders. To do a parallel addition, you use one of these per bit, and the carry out from one bit becomes the carry in to the next higher bit. (How carry is treated for the MSB and LSB is left as an exercise for the student's imagination.) To do a serial addition, the addends are in shift registers, and the carry out of the single adder is recycled through a flip-flop. Usually, the sum is shifted into one of the addend registers. The longer the word, the more clock cycles an addition takes, but there's no carry propagation time to worry about of look-ahead logic to build. (And double-precision arithmetic can take only twice as long, which isn't usually the case with parallel circuits. The treatment of carry for LSB and MSB is the same as for parallel. The classical software division routine is mostly bit serial (only the subtracts are parallel), with the quotient shifted into the register that the dividend is coming ut of. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 20814
Dear All Why do we have noise in the bus between FPGA to RAM(external )? I tested with my design synthesize with RAM onto FPGA , the result hasn't have noise. Why is it like that? Best Regard. -- Wannarat Suntiamorntut Computer System Design Laboratory (CSDL) Computer Engineering Department Prince of Songkla University, Hatyai, Songkla 90112 Thailand Tel. 66-074-212895 ext.311 Fax. 66-074-212895Article: 20815
Fabrice Hoffmann <Fabrice.Hoffmann@Topmail.de> schrieb in im Newsbeitrag: 88upo3$58i$1@news04.btx.dtag.de... > Hi everybody, > > i want to load an ALTERA EPC2 configuration Eeperom from an embedded > controller which has an RS232. I plan to use the free ALTERA Jam Player > running on a PC. So i have to emulate the BitBlaster functionality in my > controller firmware. Does anybody have information about the bitblaster > (schematics !!! ...). Should it be the BitBlaster ? What's about the ByteBlaster ? The BitBlaster contains a ALTERA device inside, the programming file is not public (as far as I know). The ByteBlaster schematic is free, we have build our own ByteBlasters and they work (up to now only for 5V supply). If the ByteBlaster schematic is ok, please let me know. AndreasArticle: 20816
2.1 Meter Observer <apeters@noao.edu> schrieb in im Newsbeitrag: 38B319B3.DBF5CAF9@noao.edu... > Holger Kleinert wrote: > > > > > ************* > > library IEEE; > > use IEEE.std_logic_1164.all; > > use IEEE.STD_LOGIC_UNSIGNED.all; > > use IEEE.STD_LOGIC_ARITH.all; > > > > ENTITY count1 is > > PORT > > ( > > clock : IN STD_LOGIC; > > enable : IN STD_LOGIC; > > qa : OUT STD_LOGIC_VECTOR (0 to 7) > > ); > > END count1; > > > > ARCHITECTURE Count1Arch of count1 is > > BEGIN > > VAR: PROCESS (clock) > > VARIABLE count : INTEGER RANGE 0 TO 255; > > > > BEGIN > > IF (clock'EVENT AND clock = '1') THEN > > IF enable = '1' THEN > > count := count + 1; > > END IF; > > END IF; > > qa <= CONV_STD_LOGIC_VECTOR(count,8); -- This line produces an error > > message on synthesis > > END PROCESS; > > END Count1Arch; > > Question: What was the exact error? ************ Error L34/C0 : #0 Error: Tried to use a synchronized value in routine SYN_INTEGER_TO_SIGNED called from count1 line 34 in file 'T:/S_VHDL/KLEINERT/VHDL1/CNT8.vhd' (HDL-107) 1 error(s) 0 warning(s) found ************ This is the exact error...Article: 20817
S Lam <simpsonlam@yahoo.com> schrieb in im Newsbeitrag: 6Vzs4.10612$Jz3.77031@nnrp1.uunet.ca... > I have not run your code myself. But I think the problem is in variable, > which usually don't synthesize well. > > I have rewritten your code. Give it a try. > > (Note that the increment is on std_logic_vector + integer. I think one of > the library takes care of the > conversion so you don't need to worry about it.) Well that works fine .... at least it is able to synthesize.... Thanks a lot. I still worry about all the examples which do not run with my tool .... It seems that I have to live with a syntax limited software .... this may become funny for the future..grrrrrrrrr... Thanks again ! -- Holger Kleinert Development / Support IBP Instruments GmbH Sutelstrasse 7a D-30659 Hannover, Germany http://www.ibpmt.com Fon : +49-511-651647 Fax : +49-511-652283 > > ************* > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > use IEEE.STD_LOGIC_ARITH.all; > > ENTITY count1 is > PORT > ( > clock : IN STD_LOGIC; > enable : IN STD_LOGIC; > qa : OUT STD_LOGIC_VECTOR (7 downto 0) > ); > END count1; > > ARCHITECTURE Count1Arch of count1 is > > SIGNAL CNT: std_logic_vector (7 downto 0); > > BEGIN > process (clock, enable, CNT) > BEGIN > IF (clock'EVENT AND clock = '1') THEN > IF enable = '1' THEN > CNT <= CNT + 1; > END IF; > END IF; > qa <= CNT; > END PROCESS; > > END Count1Arch;Article: 20818
Hi all there !! I know that this is not the perfect forum to raise this issue, but there may be people who worked on th esame problem and who can help me. BTW I posted same to PCISIG mailing list but could not get much. I am facing one problem in PCI based NIC card. Settings -------- The machine used is Genius Wipro 8000 A . BIOS is Award PCI/PNP 686 BIOS -> PnP/PCI Configuration In the Option PNP OS Installed I set -> NO for Linux and Yes of NT Because the OS want to change the PCI mapping if you have set the PNP OS Installed to YES !! In case of NT it will not boot so I set Yes. Procedure followed ----------------- The procedure I follow is 1) As a NIC card, I ask 1 K memory from Bios for my registers. All space is memory mapped. I also ask for 256 K expansion ROM space , though at present the ROM is not present on the card as well as no provision for IO space is provided in the config space (which is wrong, but for time being ,as I will not be using Remote booting, it seems OK ). 2) The BIOS write the Base address of the memory allocated in the PCI Config space.( Base address 0 ) 3) My card driver reads the config space and come to know the memory region of interest. 4) Using ioremap_nocache in Linux and NdisMMapIoSpace in NDIS 3.0, I remap the memory into another region ( physical to virtual memory mapping, as they call it in NDIS) 5) I acess the memory address from the remapped locations thereonwords. Problem faced ---------------- Now the problem faced many times in Linux and sometimes in WinNT is that the base address is found to be changed in the middle of operation.( randomly , sometimes after half hour run and sometimes even in minutes ). When the driver reads any register from the remapped location , it finds all "FFFFF... ". Upon this when I read the PCI space for base address 0 , I found it changed. Am I doing anything wrong ? Is it possible for any system to change this before reboot ? Is Any OS specific issue involved ? Please guide ----Ajit Madhekar ajit@n2.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20819
Holger Kleinert wrote: > ************* > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > use IEEE.STD_LOGIC_ARITH.all; > > ENTITY count1 is > PORT > ( > clock : IN STD_LOGIC; > enable : IN STD_LOGIC; > qa : OUT STD_LOGIC_VECTOR (0 to 7) > ); > END count1; > > ARCHITECTURE Count1Arch of count1 is > BEGIN > VAR: PROCESS (clock) > VARIABLE count : INTEGER RANGE 0 TO 255; > > BEGIN > IF (clock'EVENT AND clock = '1') THEN > IF enable = '1' THEN > count := count + 1; > END IF; > END IF; > qa <= CONV_STD_LOGIC_VECTOR(count,8); -- This line produces an error > message on synthesis > END PROCESS; > END Count1Arch; This is what the Synopsys Online Docu says: HDL-107 (error) Tried to use a synchronized value "This error occurs when you assign a value to a variable inside an if(clock'event) block, and then attempt to read it after the end if statement. Move the statement that reads the value into the if block, or change the variable into a signal and read the signal outside the process." Hope this could help you, Frank -- Dipl. Inform. Frank Poppen We use the freshest handpicked electrons Tel.:0441/9722230 \!!!!!/ VLSI Design at OFFIS Research Institute Fax.:0441/7982145 ( 0 0 ) D-26121 Oldenburg/Germany, Escherweg 2 -----------------oOOo-( )-oOOo--------------------------------------Article: 20820
"Jaime Andrés Aranguren Cardona" a écrit : > > Hi, guys. > > I hope you help me with this. I am trying to install Xilinx Foundation 2.1i > on my PC, but a message wich stands it can not "inflate PCFJars" appears on > the screen, and cancells the installation. Looks like you don't have enough space in your temporary directory. Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 20821
Hi Andreas, thanks for answering. The design of our device is finished. So the only way to communicate with the device is an RS232. While the the device is manufactured, we use the ByteBlaster. But for field-programming we need the posibility to program the EPC2 via the RS232. What type of ALTERA device is it. A classic type, i presume. Do you have ever lookedo the signals the BitBlaster produce depend on the RS232 data stream ? Fabrice Andreas Heiner <Andreas.Heiner@de.bosch.com> schrieb in im Newsbeitrag: 89056d$jtq$1@proxy.fe.internet.bosch.de... > Fabrice Hoffmann <Fabrice.Hoffmann@Topmail.de> schrieb in im Newsbeitrag: > 88upo3$58i$1@news04.btx.dtag.de... > > Hi everybody, > > > > i want to load an ALTERA EPC2 configuration Eeperom from an embedded > > controller which has an RS232. I plan to use the free ALTERA Jam Player > > running on a PC. So i have to emulate the BitBlaster functionality in my > > controller firmware. Does anybody have information about the bitblaster > > (schematics !!! ...). > Should it be the BitBlaster ? What's about the ByteBlaster ? > > The BitBlaster contains a ALTERA device inside, the programming file is not > public (as far as I know). The ByteBlaster schematic is free, we have build > our own ByteBlasters and they work (up to now only for 5V supply). If the > ByteBlaster schematic is ok, please let me know. > > Andreas > >Article: 20822
In article <38B34BEC.56A0A769@netwood.net>, "E. Robert Tisdale" <edwin@netwood.net> wrote: > What the heck is bit serial arithmetic? > > it is doing a calculation one bit at a time. It's more less the same as doing e.g. a 32 bit addition on an 8 bit cpu, using 4, 8 bit adds (with a carry in and out), it's just done with 1 bit adds, it can save HW but will cost on clockcycles needed to do a calculation. -Lasse Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20823
Yes, Synplify has a bug in passing multi-cycle timing constrains to the M1(M2). Here is the answer I finally got from their support: > I have filed two bugs for the multicycle path issue. >#15285 : When the -to constraint is applied to the "out" > register the critical path is reported wrong. > It is still from the FDR flop out to the OBUG > and the frequency should be around 117 MHz >#15287 : When you apply the -from constraints to the in1 and in2 flops, > the invertor out_ininv gets a delay of -997!!!! FYI ----------------------------------------------- Rotem Gazit mailto:rotemg@mysticom.com MystiCom LTD. http://www.mysticom.com ----------------------------------------------- > Hi, > > I am targeting a Verilog design to Xilinx Virtex xcv1000 device. > > The M1 (Xilinx P&R tool) allow me to define multi cycle timing > constrains for a path from specific FF (or PORT) to another FF (or > PORT) . > As far as I know Synplify supports only FROM FF (or PORT) TO FF (or > PORT) multi cycle timing constrains (NOT for specific path). > > When I tried to define the constrains in Synplify (using Synplifys > format) the M1 seemed to ignor them. > > Did anyone ever bumped into this problem ? > > Thanks in advance, > > ----------------------------------------------- > Rotem Gazit > mailto:rotemg@mysticom.com > MystiCom LTD. > http://www.mysticom.com > ----------------------------------------------- > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20824
> Hi Andreas, > > thanks for answering. The design of our device is finished. So the only way > to communicate with the device is an RS232. While the the device is > manufactured, we use the ByteBlaster. But for field-programming we need the > posibility to program the EPC2 via the RS232. What type of ALTERA device is > it. A classic type, i presume. Do you have ever lookedo the signals the > BitBlaster produce depend on the RS232 data stream ? > > Fabrice Hi Fabrice, I don't know this exactly because it was in the past and I don't have any BitBlaster here anymore. But I think it was a 7000 device (such device with copy protection mechanism !). I don't have any information about the protocol for the RS232. Do you have contacted ALTERA directly ? We currently have nearly no contact because we had switched completely to XILINX. Andreas
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z