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Looks like Norton Utilities got some of the Foundation files by accident. > -NickArticle: 21351
"Dennis Krupp" <lone-traveler@usa.net> wrote in message news:sd3snkb59n45@corp.supernews.com... > Does anyone know if and where I can get a ByteblasterMV for less than the > bloody $150 that Altera charges short of having to build it myself? There's another clone out there besides the one that John Renvar posted a link to. I'll look for it at work on Monday. We used this particular clone because it was cheaper than a ByteBlaster and works done to 1.8V. Alterantively, the Altera guys gave us a free one when they came to visit once (and try to talk us away from Xilinx). Invite them in and tell them the ByteBlaster's the price of admission. :-) ---Joel KolstadArticle: 21352
Please visit and comment on my Electronics and Electrical Engineering pages located at: http://www.scottj.f9.co.uk/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes In addition my homepage (http://www.scottj.f9.co.uk/) contains: A section about me My CV A James Bond Section A guestbook Humour 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Internet Resources Psychology Resources Student Resources Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.scottj.f9.co.uk/. Thanks Scott Johnston me@scottj.f9.co.ukArticle: 21353
Dennis Krupp wrote: > > Does anyone know if and where I can get a ByteblasterMV for less than the > bloody $150 that Altera charges short of having to build it myself? > Thanks The German branch of EBV Elektronik sells a clone for DM100, around $50. I got one and it works fine. Certainly beats making one myself. John Kortink That you're paranoid doesn't mean they're not out to get you Email : kortink@inter.nl.net Homepage : http://www.inter.nl.net/users/J.KortinkArticle: 21354
Please cut the music. Scott Paul Johnston wrote: > Please visit and comment on my Electronics and Electrical Engineering > pages located at: > > http://www.scottj.f9.co.uk/eee.htm > > Containing: > Introduction to EEE > Resources (over 100 web links) > Employment Statistics and newspaper excerpts > Engineering Poems, Quotations and Jokes > > In addition my homepage (http://www.scottj.f9.co.uk/) > contains: > > A section about me > My CV > A James Bond Section > A guestbook > Humour > 500+ cool links in the "new look" bookpage > Cool background MIDI and graphics > Literary quotations > Photo Album > Internet Resources > Psychology Resources > Student Resources > Awards Page > Poems... > > Basically, something for everyone! > > PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! > > Please send you comments via the guestbook or by Email (containing > your full name and Email and webpage addresses) and visit via > http://www.scottj.f9.co.uk/. > > Thanks > Scott Johnston > me@scottj.f9.co.ukArticle: 21355
On Fri, 17 Mar 2000 13:31:57 +0000, "Stewart, Nial [HAL02:HH00:EXCH]" <stewartn@europem01.nt.com> wrote: >Keith R. Williams wrote: >> >> (yellow-wires are a part of the job). > >I've always wondered why someone doesn't produce cut and >strap wire in "PCB Green with a hint of white solder >mask and a touch of solder colour". It would be alot less >noticeable on boards :-). > >Nial. I've seen it ... well actually a somewhat lighter green. But there _is_ a conflict between "vanity re-works" and easy visibility of changes... personally I'd rather the reworks stood out so they can be more easily checked. - BrianArticle: 21356
Any opinions on Actel's SX-A (.22/.25µ) FPGAs? or is Xilinx the way to go? tiaArticle: 21357
On behalf of Gray Research LLC, I am pleased to announce that the first of three articles in the series "Building a RISC System in an FPGA" is now on newsstands, in the March 2000 issue (#116) of Circuit Cellar magazine. This series shows how to design and implement practical processors and integrated systems-on-a-chip in small FPGAs. In Part 1, "Tools, Instruction Set, and Datapath", we introduce the XSOC System-on-a-Chip project and the xr16 16-bit pipelined RISC processor core, retarget the LCC 4.1 C compiler, write an assembler and simulator, and design and implement the datapath. In Part 2, "Pipeline and Control Unit Design", we explore the processor pipeline and design its control unit. In Part 3, "System-on-a-Chip Design", we design and implement the on-chip bus, memory controller, and peripherals, including a bilevel VGA display. The project was designed to be accessible to students and hobbyists. It fits in a Xilinx XC4005XL, targets an XESS (www.xess.com) XS40 (v1.2 or later) prototyping board, and can be rebuilt with Xilinx Student Edition 1.5. A beta test of the accompanying XSOC Project on-line materials is now underway. These materials include the documentation, specifications, source code, and schematics needed to build the XSOC Project featured in the magazine articles, although they do not include the text of the articles themselves. HDL and 32-bit register versions will follow shortly. If you would like to learn more about XSOC/xr16 and/or participate in the beta test, please visit www.fpgacpu.org/xsoc and follow the instructions, and/or subscribe to the new FPGA CPU / XSOC mailing list, fpga-cpu@egroups.com, by mailing fpga-cpu-subscribe@egroups.com. Thank you, Jan Gray President, Gray Research LLC jan@fpgacpu.org (for FPGA CPU issues) [reposted sans comp.arch.hobbyist]Article: 21358
Hi! I' m a student in Signal Processing and I' m currently working on a project involving an Atmel's AT40k series FPGA. I have downloaded all the datasheets I need but I can' t find anything explaining in detail how to use Mode 4 configuration download, which is the mode I need to use. The data sheet say you need to contact your local sales office to obtain detailed information ( they say that's for protecting users, I can' t understand why ... ) on Mode 4 ( synchronous RAM configuration download ). I was wondering if any of you had a datasheet explaining this or could possibly give me a few details on this. Your help would be greatly appreciated ! Thanks. Lorcan Mc Donagh E-mail: lorcan.mcdonagh@free.frArticle: 21359
On Sat, 18 Mar 2000 19:32:45, Brian Drummond <brian@shapes.demon.co.uk> wrote: > On Fri, 17 Mar 2000 13:31:57 +0000, "Stewart, Nial [HAL02:HH00:EXCH]" > <stewartn@europem01.nt.com> wrote: > > >Keith R. Williams wrote: > >> > >> (yellow-wires are a part of the job). > > > >I've always wondered why someone doesn't produce cut and > >strap wire in "PCB Green with a hint of white solder > >mask and a touch of solder colour". It would be alot less > >noticeable on boards :-). > > > >Nial. > > I've seen it ... well actually a somewhat lighter green. > > But there _is_ a conflict between "vanity re-works" and easy visibility of > changes... personally I'd rather the reworks stood out so they can be more > easily checked. Sure. I've even used different colors to denote different "levels" of re-work or different power zones (classial red/black, etc). Fortunately, so far this time I only have a few trivial stupid miss-steaks and the poorly documented Express mode stuff to clean up. I haven't gotten to the Virtex yet, but it's configuration is max-wired into the Spartan so yellow wires are *reall* hidden ;-). I also have another turn on the board coming up so I can make it pretty then. This thing will never go into production, so it wouldn't be a big problem with a few wires here or there. ---- Keith Reply-To: "Sherdyn" <sherdyn@yahoo.com>Article: 21360
Can anyone tell me how to simulate a weak pull-up in VHDL testbench? SherdynArticle: 21361
Hi! Does anybody know how to eliminate high fan-out in Xilinx Virtex devices? I tried to brake nets using BUF buffers, but they are always eliminated by synthesis or implementation tools. My entire project is described in VHDL. I use FPGA Express 3.3 for synthesis and Foundation Series 2.1i for implementation. PawelArticle: 21362
In article <38D58E9D.71BE2598@gmu.edu>, Pawel Chodowiec <pchodowi@gmu.edu> wrote: > Hi! Does anybody know how to eliminate high fan-out in Xilinx Virtex > devices? I tried to brake nets using BUF buffers, but they are always > eliminated by synthesis or implementation tools. My entire project is > described in VHDL. I use FPGA Express 3.3 for synthesis and Foundation > Series 2.1i for implementation. > > Pawel > If you are using Foundation 2.1i you can use the MAXSKEW constraint using the Constraints Editor to tag nets to use the secondary global routing resources in Virtex. (See solution 6198 at http://support.xilinx.com/techdocs/6198.htm). Fred Laboratoire Signaux et Système CNAM Paris Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21363
Hi, If you use Xilinx, you can use the "pullup" component from the "unisim" library and write : " C_PULLUP: pullup port map(O => signal_Pull); signal_Pull <= I_signal;" An use "I_signal" normally. If you don't use Xilinx a simple way to simulate a pull up is : "entity PULLUP is port(O : out STD_ULOGIC := 'H'); end PULLUP; architecture PULLUP_V of PULLUP is begin O <= 'H'; end PULLUP_V"; "Sherdyn" <sherdyn@yahoo.com> a écrit dans le message news: 38d58e3c.0@news.cyberway.com.sg... > Can anyone tell me how to simulate a weak pull-up in VHDL testbench? > > Sherdyn > >Article: 21364
I got an XSK40 and an XSK95 board along with Foundation 1.5 student edition from Xess. The boards have an 8051/8031 as well. See http://www.xess.com -Nick MegaBolt wrote: > Hi, > > Advice for beginner. > Web sites, book ref...any thing to get started in VHDL, FPGAs > > Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at > Xilinx wed site. Not supported most likely. > > Thanks. > > CHLArticle: 21365
Also check out http://www.optimagic.com Nick wrote: > I got an XSK40 and an XSK95 board along with Foundation 1.5 student > edition from Xess. The boards have an 8051/8031 as well. See > http://www.xess.com > -Nick > > MegaBolt wrote: > > > Hi, > > > > Advice for beginner. > > Web sites, book ref...any thing to get started in VHDL, FPGAs > > > > Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at > > Xilinx wed site. Not supported most likely. > > > > Thanks. > > > > CHLArticle: 21366
Hi all I am working on a design which may be used in two products, one of which won't need some functions of the design. I don't want to have 2 designs (we won't make 2 ASICs). I was wondering if it was possible to have 2 clock domains (same frequency) with the possibility to turn one of them off to reduce power consumption (this would be done by pulling a pin high or low for example) -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 21367
Hi. Can anybody clear for me the relationship of gates quantity for the same design in FPGA (Virtex) and ASIC. (I'm not sure if it is correct question or it depends from ASIC technology and other factors) May be you have prototyped your ASIC in FPGA and have an example of values of quantity in the both technologies. with best regards, Bonio Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21368
Pawel,
I'm guessing you mean fan out.... If that's the case, one effective way is
to create multiple source ffs for the signal. All your (high load) sources
are from ffs right <smile>? This gives you the added benefit of giving
(generally) higher performance because the placer can locate co-locate the
sources with the loads.
--
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (908) 996-0817
FAX: (908) 996-0787
See us on the Web at:
The Bottom Line Technologies Home Page
http://www.bltinc.com
The Xilinx XPERTS - U.S Partners Page
http://www.xilinx.com/company/consultants/us_consultants.htm
The Programmable Logic Jump Station
http://www.optimagic.com/consultants.html
Pawel Chodowiec <pchodowi@gmu.edu> wrote in message
news:38D58E9D.71BE2598@gmu.edu...
> Hi! Does anybody know how to eliminate high fan-out in Xilinx Virtex
> devices? I tried to brake nets using BUF buffers, but they are always
> eliminated by synthesis or implementation tools. My entire project is
> described in VHDL. I use FPGA Express 3.3 for synthesis and Foundation
> Series 2.1i for implementation.
>
> Pawel
Article: 21369you can by it via amazon ff Nick schrieb: > Also check out http://www.optimagic.com > > Nick wrote: > > > I got an XSK40 and an XSK95 board along with Foundation 1.5 student > > edition from Xess. The boards have an 8051/8031 as well. See > > http://www.xess.com > > -Nick > > > > MegaBolt wrote: > > > > > Hi, > > > > > > Advice for beginner. > > > Web sites, book ref...any thing to get started in VHDL, FPGAs > > > > > > Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at > > > Xilinx wed site. Not supported most likely. > > > > > > Thanks. > > > > > > CHLArticle: 21370
Hi all, I'm not very new in FPGA design but I can't find the issue of following problem: WARNING:Timing:33 - Clock nets using non-dedicated resources were found in this design. Clock skew on these resources will not be automatically addressed during path analysis. To create a timing report that analyzes clock skew for these paths, run trce with the '-skew' option. I'm quite sure to use in my design the deducted clock resources only (and connected to BufG or Buf GP). I think the syntheses tool can' recognise some part in my design and form it so, that clock some FF with the gated signal. But I cant find where. THE QUESTION: How I can find out where the Alliance 2.1i found the non- dedicated resources(which signal is such clock)? Any help will be appreciated, Bonio Remove_this_Bonio.lopez@gmx.ch_remove_this Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21371
Im Artikel <38D0E9E8.CAC88D25@NOSPAM.com>, David Gilchrist <david.gilchrist@NOSPAM.com> schreibt: >It turned out to be a problem with the place and route tool (Service >Pack 3 surprisingly enough). The P & R tool was corrupting the bits >during BitGen. When this was updated the problem magically disappeared. This gives me the opportunity to ask Xilinx to be more open with information about problems. I'm a regular reader of the Xilinx web page, but when we had problems with the DLL I didn't found any hint to this problem. It does not take much imagination to guess about my feelings, when I found out, that this problem (which cost us three days and ended in not using the DLL) was known to Xilinx at that time. We all make mistakes, but please admit them. It helps us customers. Regards, Marco Liesegang electronics GmbH, Germany As always, speaking only for myself.Article: 21372
The suggestions I've for you are the following books: -Brown, Stephen; Vranesic, Zvonko; "Fundamentals of Digital Logic with VHDL design". Very good one for those interested in specifically VDHL. Altera's MAX+plus II software included (CD). -Bolton, Martin; "Digital Systems Design with Programmable Logic". For those interested in general digital systems theory with PLD. Best wishes, Marcio Longaray MegaBolt <MegaBolt@mbox5.singnet.com.sg> escreveu nas notícias de mensagem:8b4i7r$6fd$1@mawar.singnet.com.sg... > Hi, > > Advice for beginner. > Web sites, book ref...any thing to get started in VHDL, FPGAs > > Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at > Xilinx wed site. Not supported most likely. > > Thanks. > > CHL > > >Article: 21373
Hi, Advice for beginner. Web sites, book ref...any thing to get started in VHDL, FPGAs Heard of Xilinx Foundation Series 1.5 (Student Edition) but no info at Xilinx wed site. Not supported most likely. Thanks. CHLArticle: 21374
Hi, I was attempting to synthesize a VHDL design for a Xilinx SpartanXL FPGA to get some timing and usage statistics and received the following LeonardoSpectrum error message: ERROR: a gnd net is driven by primitive gate(s) -- NET: GND0 DRIVING GATE: i6_i2_i4_i2_reg_s_active_0 optimize: view can not be optimized because of electrical problems Using wire table: s10xl-3_avg I understand what the i6...s_active_0 are but what does NET: GND0 DRIVING GATE mean and is there a method for finding/fixing such problems. Many thanks, Andy
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