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John Huang ¼¶¼g©ó¤å³¹ ... >Hi: > I am looking for a good VHDL synthesis and simulation tool, >I hope it has fine timing simulation function, and price is lower >than 6000 dollars, it must do multi-vendor FPGAs, >please tell me which is the best fit for me > > >Thanks > >John Huang > >Article: 12426
FOCUS FOCUS FOCUS The title of the thread is (was till I started this one): "Xilinx may not support schematics for Virtex?????" It's a real BIG issue for some of us. And this might be the forum to find out how many people it is an issue for. This could then lead (assuming there is sufficient outcry) to a vendor or two fixing the problem. This has NOTHING to do with the VHDL vs Schematic debate, which is as pointless big endian vs small endian. Here are the FACTs (1) Here is an OPINION (2) Here is my input to some of the stuff already on the thread (3) Here is a CALL to action (4) If this article is starting to make your eyes glaze over, please jump to section (4) (1) The FACTs Xilinx has a new product family called Virtex. It has many neat new features that many of us would like to use. Support for this family is included in the new A1.5/F1.5 release, which Xilinx has been shipping for a few weeks. It has gates, it has flip flops, it has carry chains, it has various RAM capabilities in the CLBs, it has larger blocks of RAM on the sides of the chip, it has a bunch of new I/O types (mostly new I/O standards support), it has DLL clock adjustment, and probably some other things I've missed. In the A1.5 release there IS a library for use with Viewlogic ViewDraw. I haven't bothered checking the situation for Aldec in F1.5 , but I assume there is a schematic library there too. What is different about the ViewDraw schematic library for Virtex is that unlike EVERY other library that Xilinx has released for use with ViewDraw, The new Virtex library is missing the simulation models below the Xilinx primitives. There has always been a few primitives in each library which have been problematic for simulation. In the various 4k libraries, the ROM primitives, and RAMs with initialization have required extra stuff to be done to use them correctly. In ViewSim parlance, the solution involved LOADM statements in a command file. Messy but a sufficient work around for the times when these elements were used. If this article is starting to make your eyes glaze over, please jump to section (4) (2) OPINION The only thing that matters to ME is that I have a highly effective design flow that allows me to be extremely productive in creating bullet proof production designs for my clients. This flow is based on totally synchronous design (including multiple domains if necessary), full time-spec coverage of the design, extensive functional simulation, and static timing analysis (based on the time-specs). It works 100% of the time. I do my designs using ViewDraw for schematic entry and ViewSim for functional simulation. The rest is Xilinx CAE sw. The lack of the simulation models in the new Virtex library makes this flow impossible. What used to be a simple mouse click away to create a functional simulation netlist is now impossible. Telling me that there is a solution that involves using additional VHDL simulations is pointless. I have the tools that work for every other device family, ViewDraw and ViewSim. I don't care about timing simulation. (It is pointless anyway, but I wont clutter up this article with explaining why). It appears that the timing simulation model that Xilinx is planning for Virtex is based on the post routed design being modeled by these new LUT primitives, plus FFs, RAMs, etc, but no gates. Therefore, the timing simulation will be littered with these LUT primitives and wont be simulateable with ViewSim without a lot of effort. Since this is timing simulation, I don't care. It appears that Xilinx has decided that because the timing simulation is "too hard to make work" with ViewSim, there is no point in supporting functional simulation. Clearly, I disagree. Since the LUT primitives are basically no different from ROM primitives, this is an issue that already exists, and there are known workarounds. For people doing schematic design, there would be NO need or requirement to use these LUT primitives, since from a design entry point of view they add NOTHING to what you can design. They even need the same INIT string that you place on ROMS, and this is an issue that is already known to have a work around. I believe that what's needed to fix this problem is to create the functional simulation models for the Xilinx primitives in the Virtex schematic library. This isn't even a hard project for Xilinx, since 90% of the library already exists in the XC4000XL library. What would of course be even better is to have Viewlogic join in and add one more thing to ViewSim: When It sees an INIT=.... attribute on a symbol in the VSM file, do a LOADM type operation on the underlying ROM with the init value. This would allow fixing things even for the existing libraries. I believe that Xilinx has mistakenly (this is the nicest way I can put it) convinced themselves that 100% of all new designs are (will be) done in HDL That only HDL designers will want to use Virtex That nobody does schematic design over 5K gates That schematic has no advantages over HDL That requiring customers to change their design flow is no big deal That large designs can't be simulated in ViewSim If this article is starting to make your eyes glaze over, please jump to section (4) (3) Responses to items in this thread so far When I saw the first post from Ray and Austin, on Friday night, I thought I would think about it a bit over the weekend. By Sunday night there are 30+ articles on the thread, and they have explored lots of interesting stuff, almost none of it on-topic. I was going to use this section to answer some of it, but you will be glad to know that I came to my senses. (4) CALL to action If you are one of the thousands of Xilinx customers that bought OEM ViewDraw and ViewSim, or you have a full function license from Viewlogic for these tools, this affects YOU. You can add to this thread, but please keep it on topic and either agree or disagree with me. You can contact you FAE or sales person and let them know that this situation is an issue for you. If you are a Xilinx FAE reading this, you can email me and I'll let you know what I really think about this. If you are an Altera FAE, you can stop laughing now. This is not an HDL vs Sch debate. If HDL works for you, great ! You are not affected by this situation. Go and do your designs. Thank you for your interest Philip Freidin fliptron@netcom.com ( I read through this 3 or 4 times, my finger hovers over the send key, I pause, I read it once more, The key is pressed.)Article: 12427
Philip Freidin has posted an article to this thread, but changed the title to "Focus Focus Focus" Philip FreidinArticle: 12428
Ingo Froehlich wrote: > Hello, > > I am using F1.4 Xilinx Foundation Software to programm a XC95216 CPLD. > The abel code has a pin assignment like > > name pin #; > > but the fitter report tells me a different assignment then I have > written it down in the code. In the design manager, the option "Use > Design Location Constrains" is ON (At the end, it is same assignment if > its OFF). The edif-file look correct. > > It is like this option has no effect. > > Do anyone know this problem and how to solve it? > > Regards, Ingo Froehlich This can be use in a vhdl file, can you try it in a ucf or ctr file ? attribute pinnum of xxxx : signal is "Pxx";Article: 12429
EUR 712 Hardware Design & Development Engineers SOUTH-WEST ENGLAND Salary £ 25-30,000 Negotiable + Benefits Our client is involved in design, development and manufacture of equipment for the satellite communications industry. As part of their business development plan, they are expanding their team to add more hardware design and development resources. Role We require a flexible and capable individual to support activity in introducing not just new, highly integrated and innovative test solutions for existing systems, but also solutions for the burgeoning satellite telecommunications market. This position fits into a small existing team, which works closely with an associated software team. An appreciation of the implications of any design activity, which may influence software implementations, is considered very important. Experience required Hardware Design & Development experience : digital design (preferably including programmable arrays), some analogue design, an appreciation of RF components and their capabilities Experience of taking a product through from specification to deployment Familiarity with industry standard design practices and toolsets Probably Degree qualified though relevant proven experience of over 2 years and proven aptitude are the prime considerations A competitive salary and benefits package is offered which includes contributory company pension scheme, profit related Bonus Scheme and Share Ownership Scheme. Interviews/ Start: ASAP. CVs by email, fax or 1st class post, FAO: Shena Parthab quoting REF: 712 InterManagement Group Bridgefoot House 159 High Street, Huntingdon CAMBRIDGESHIRE United Kingdom PE18 6TF Tel: 01480-377000 Fax: 01480-377003/ 52201 EURONET@dial.pipex.comArticle: 12430
EUR: 623 PRINCIPAL DESIGN ENGINEER To work at the leading edge of technology Bristol/ South Wales Area Salary £35,000 - £42,000 + Car An outstanding opportunity for career development Our Client is involved in the manufacture, delivery and support of a range of telecommunications products in defence. The PDE will be involved in the Analogue & Digital circuit design of these products, leading a small team of junior design engineers and providing specialist support on EMC issues. Responsibilities: Directly responsible to the Senior Engineering Manager for all engineering activities on nominated programmes Full responsibility for selection/implementation of design approach for varied communications equipment requirements & for resolution of all technical problems on nominated programmes Formulation of engineering strategy on component-level design for the business area Requirements analysis & definition as part of customer programmes and in-company purposes Team leading a small group of junior design engineers & direct supervision of permanent staff & contractors Hands-on digital & analogue circuit design and development utilising CADENCE CAE tools for design description, synthesis & simulation Providing EMC design & countermeasure expertise advising other engineers where necessary & guiding subordinate engineering staff Supporting design reviews of own and others work Maintaining close liaison with Industrial Engineering, Manufacturing & Production Test departments Authoring/ Editing Technical & Project Documentation for Customer use Experience required: A good degree in Electronic Engineering or a closely-related subject (minimum) Chartered Engineer status an advantage At least 6 years' solid electronic design experience, including analogue & digital circuitry, in a telecommunications environment, achieving Senior Engineer status Experience of comprehensive use of CAE tools essential, preferably CADENCE Experience of military product design and supervisory experience advantageous Familiarity with Field Programmable Gate Array technology, preferably XILINX is highly desirable Note: As this is a hands on circuit design & development role sound knowledge of analogue & digital design techniques is essential. Security Clearance required. Start asap. CVs by email, fax or 1st class post, FAO: Shena Parthab quoting REF: 623 InterManagement Group Bridgefoot House 159 High Street Huntingdon CAMBRIDGESHIRE United Kingdom PE18 6TF Tel: 01480-377000 Fax: 01480-377003/ 52201 EURONET@dial.pipex.comArticle: 12431
Hi everybody, does anybody know how to digitally realize a sine generator other than sampling a sine period and storing it in a ROM ? We have to integrate it in an FPGA. If anybody knows book references on this subject, we would be happy for a very long time. See you soon on the Web, Yves.Article: 12432
Yves Vandervennet wrote: > Hi everybody, > does anybody know how to digitally realize a sine generator > other than sampling a sine period and storing it in a ROM ? > We have to integrate it in an FPGA. How desperate are you for accuracy? There are some simple cheap piecewise linear approximations that have fairly low total harmonic distortion (ones of percent) even though they look crude. If you want the best you can get, find out about CORDIC generators - any search engine should make a good job of that. Aonther possibility which may be interesting in some FPGA architectures is to create a square wave (left as an exercise for the student!) and then pass it through some kind of DSP filter that lops off all the higher harmonics. Full-blown FIR filters are clearly out (cheaper to build the ROM), but there are other possibilities that are quite economical of resources. Enjoy Jonathan BromleyArticle: 12433
Graeme Durant wrote: > Under Known Issues it says that the revision control mechanism only > handles implementation data, and that you have to manually handle > your source code/netlists if you want to keep them. I think that the general theory among FPGA EDA vendors is that source code revision control is for wussy s/w engineers not us hairy chested h/w types. If this wasn't so why haven't they included one of the free or shareware implementations of Unix's RCS - which has been around for years. And while they're at it why don't they throw in Emacs 19 + verilog/vhdl-mode + make and hey presto the GUI's disappeared altogether. Does anybody actually like the idea of having 3 GUIs to implement a Xilinx design via Foundation Express - the F.E. one, Project manager, Design manager ?Article: 12434
Graeme Durant wrote: > Under Known Issues it says that the revision control mechanism only > handles implementation data, and that you have to manually handle > your source code/netlists if you want to keep them. I think that the general theory among FPGA EDA vendors is that source code revision control is for wussy s/w engineers not us hairy chested h/w types. If this wasn't so why haven't they included one of the free or shareware implementations of Unix's RCS - which has been around for years. And while they're at it why don't they throw in Emacs 19 + verilog/vhdl-mode + make and hey presto the GUI's disappeared altogether. Does anybody actually like the idea of having 3 GUIs to implement a Xilinx design via Foundation Express - the F.E. one, Project manager, Design manager ?Article: 12435
philip said, in part: >(4) CALL to action >If you are one of the thousands of Xilinx customers that bought OEM ViewDraw and ViewSim, or you have a full function >license from Viewlogic for these tools, this affects YOU. >You can add to this thread, but please keep it on topic and either agree or disagree with me. i agree - i remember back in the mid-80s, we had mentor, they'd upgrade their s/w and force us to upgrade our hardware. same thing - now they do something new, our established design flows no longer work (and not for apparently any good reason), we have to buy more stuff, we have to learn new tools. uh, why? we all have enough to do during the day. also, i doubt how long this thread will stay on topic, this is the internet, isn't it? :-) rkArticle: 12436
Hi, I am working on a I2C synthesizable core, simulation models and bus monitor in verilog. Anyone aware of any shareware/freeware source (preferably in verilog) or other related stuff at any site then please let me know. -- Ashok Madaan -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12437
In article <6vjffo$nir$1@news.inter.net.il>, "Ido Kleinman" <kleinn@mail.biu.ac.il> wrote: > Anyone got any experience with Aldec's tool? > Are the big ones (Synopsys, Examplar..) worth the investment? > Aldec's tool is good. It has GOOD USER INTERFACE (Real MS-Windows GUI) and transcript windows support, interactive simulation and Macro File support... Waveform print-out support.... VITAL and WAVE Support (Gate Level/Post-Timing Sim Support) Equiped with Graphicsl FSM Tool.... and many useful utilities.... (TestBench Generator is very good...support IEEE 1029.1 WAVE-Waveform Vector Exchange) But..... The Simulation Speed is poor....slow..... They says new version (currently 3.1) improves simulation.... ------------------------------------------- ilho kook goodkook@csvlsi.kyunghee.ac.kr http://www.csvlsi.kyunghee.ac.kr http://vlsi2.kyunghee.ac.kr ------------------------------------------- -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12438
Hi, Sandy Harris wrote: > In article <6vjffo$nir$1@news.inter.net.il>, "Ido Kleinman" <kleinn@mail.biu.ac.il> wrote: > > There's a free toolset called alliance from P & M Curie U in Paris. > Sorry, I don't have the URL to hand. The URL is http://www-asim.lip6.fr/alliance/index.gb.html . Bye,... EdwinArticle: 12439
On Mon, 12 Oct 1998 11:08:05 +0200, Yves Vandervennet <yves@elmitel.ulb.ac.be> wrote: >Hi everybody, > > does anybody know how to digitally realize a sine generator >other than sampling a sine period and storing it in a ROM ? CORDIC - BrianArticle: 12440
Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote: > What exactly is schematic entry (as opposed to VHDL)? > Is it like it sounds, you draw a schematic with a couple of OR, AND > and NOT? Sounds tedious to me, but some people seem to prefer it to > VHDL. Well, the term is somewhat overloaded, but in general refers to design using graphical methods of indicating the structure of the design. The behavior of the design is inferred. Primitives used in the structure include, but are not necessarily limited to, gate level components. Incidently, it is possible to enter schematics using VHDL, so there's no real dichotomy there. Just confine yourself to structural description to get a feel for what it is like. Paul -- Paul Menchini | mench@mench.com | "Se tu sarai solo, Menchini & Associates | www.mench.com | tu sarai tutto tuo." P.O. Box 71767 | 919-479-1670[v] | -- Leonardo Da Vinci Durham, NC 27722-1767 | 919-479-1671[f] |Article: 12441
To decide between a processor core and dedicated logic, does anyone have an indication of the price range for the various processor cores available for FPGA targets? I only need an order-of-5 estimate, but so far I cannot get closer than "up to $100,000". 8-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates 16-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates 32-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates Also, some names of supppliers or a pointer to a magazine survey would be helpful. SimonArticle: 12442
Hi Simon: We have a complete price list for our 8-bit RISC uC core (PIC(R) software compatible) at www.silicore.net. Regards, Wade Peterson Silicore Corporation Simon@NOTtile.demon.co.uk (Simon Bacon) wrote: >To decide between a processor core and dedicated logic, does >anyone have an indication of the price range for the various >processor cores available for FPGA targets? >I only need an order-of-5 estimate, but so far I cannot get closer >than "up to $100,000". > 8-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates > 16-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates > 32-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates >Also, some names of supppliers or a pointer to a magazine survey would >be helpful. >SimonArticle: 12443
Peter wrote:
>
> I have met someone from a major ASIC house who described to me how
> firms in Hong Kong have reverse engineered their clients' (digital)
> ASICs back to a netlist of gates (!!) and done it reportedly for $25k;
> this cost was for a 10k gate device but they can do much bigger ones
> since the process is quite straightforward, for a given ASIC vendor.
>
> One gets a hex listing of the ROM of an on-chip micro, or a normal
> masked micro, for a similar amount. This firm offers 8051 cores and
> they had this done to them.
>
> All the above is done purely optically.
>
I've already read somewhere that optically reading back standard-cell
ASICs can be automatized. With some pattern recognition the whole cells
can be identified and netlist can be generated. The whole procedure can
be done in the microelectronic department of a university by adventure
seeking students.
If I recall correctly the other post or paper mentioned $50k for the
complete netlist.
>
> I don't know if an antifuse is optically visible, but Neocad obviously
> did not spend $300M reverse engineering Xilinx's bitstream, and all
> the "secrets" of every FPGA's SRAM/antifuse mapping are in any case
> revealed when you disassemble their place & route tools.
>
> --
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80 @ digiYserve . com but
> remove the X and the Y.
I think antifuses aren't visible optically since a programmed
conductive antifuse differs from a non-conductive one only by a small
diffusion surface. That might be the advantage of antifuse FPGAs over
ASIC ICs.
OTOH reading out an FPGA need to be done once for the whole family
and the process doesn't require the very specific design I want to copy.
If I had to do it I'd start with the isolation of the programming
circuitry by an ion beam (also accesible in university labs). Maybe it's
the wrong way, maybe it isn't.
BTW I asked the whole thing because of my concerns about the eastern
market. My company has plans to start production of our medical devices
in Russia (I don't know whether this is still such a good idea seeing
the russian economy spiraling out of control), so minimum efforts must
be done to prevent the factory from producing our devices without
control.
I think using SRAM based FPGAs and encapsulated batteries is out in
medical devices because they are not resettable after a hard ESD or any
other hazard which I couldn't forecast (I think of high energy
particles).
Botond
--
Botond Kardos - at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
To get my real address just put the domain
name in reverse order and remove 'nospam'.
x@1.2.3 -> x@2.1
Article: 12444Jeffrey G.S. LIU wrote : Altera has source code about PCI controller (both master and target mode). I've use the Altera CPLD to implement PCI master and target. Gerald Coe ¼¶¼g©ó¤å³¹ ... > >I'm looking to implement a PCI target. I've found a chip from AMCC that >does it, but at a cost of uk26.00 100 off, its too expensive - costing >more than fpga real estate. > >I've also contacted xilinx but the PCI logicCore is well over uk3000.00 >and a full development system well over uk5000.00. > >I can currently use xilinx devices and vantis cpld's, but for the right >target I'm will to look elsewhere. I have downloaded the vantis pci kit, >but it is undocumented and dosen't look complete. > >Does anyone know of free or low cost HDL/Schematic for a PCI target? > >-- >Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, >Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. >http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 12445
Have you looked at Don Lancasters's MAGIC SINEWAVES? Check out http://www.tinaja.com/magsn01.html I implemented Don's 420 bit MAGIC SINEWAVES in a Xilinx FPGA. They work and have low distortion. Bill Seiler ccwest@ix.netcom.comArticle: 12446
Look at Tom Coonan's Verilog Synthetic PIC. Checkout http://www.mindspring.com/~tcoonan/newpic.html I synthesized this PIC with success. The price is good FREE! Bill Seiler ccwest@ix.netcom.comArticle: 12447
Le mer Michel wrote in message <3621C21C.AC3A1BE1@ago.fr>... >Ingo Froehlich wrote: > >> Hello, >> >> I am using F1.4 Xilinx Foundation Software to programm a XC95216 CPLD. >> The abel code has a pin assignment like >> >> name pin #; >> >> but the fitter report tells me a different assignment then I have >> written it down in the code. In the design manager, the option "Use >> Design Location Constrains" is ON (At the end, it is same assignment if >> its OFF). The edif-file look correct. >> >> It is like this option has no effect. >> >> Do anyone know this problem and how to solve it? >> >> Regards, Ingo Froehlich > >This can be use in a vhdl file, can you try it in a ucf or ctr file ? >attribute pinnum of xxxx : signal is "Pxx"; Actually, I had the same problem, but using ABEL. I implemented the VSPROM design (using a 9536 CPLD and an EPROM rather than one of the serial PROMs for XC4K configuration) and the P+R tools threw away the pin assignments, which were in the source code. Haven't tried it with 1.5 to see if it still works; nor did I go and put the pin assignments in the .UCF. Maybe later this week, when I have to finish the schematic for the board... As an aside, I tried to implement the VSPROM design using VHDL and ran out of macrocells, and for the life of me, I can't figure out why. -andy -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.eduArticle: 12448
Rick wrote in message <3621E421.F1E791D3@algor.co.uk>... >Graeme Durant wrote: > >> Under Known Issues it says that the revision control mechanism only >> handles implementation data, and that you have to manually handle >> your source code/netlists if you want to keep them. > >I think that the general theory among FPGA EDA vendors is that source code >revision control is for wussy s/w engineers not us hairy chested h/w types. If >this wasn't so why haven't they included one of the free or shareware >implementations of Unix's RCS - which has been around for years. And while >they're at it why don't they throw in Emacs 19 + verilog/vhdl-mode + make and >hey presto the GUI's disappeared altogether. I hate emacs! Don't get me started on emacs... >Does anybody actually like the idea of having 3 GUIs to implement a Xilinx >design via Foundation Express - the F.E. one, Project manager, Design manager ? No, but don't those three tools originate from three different vendors? I think they're "working on it." -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.eduArticle: 12449
Rickman wrote in message <362113BF.906A822B@yahoo.com>... >When I abandoned Orcad for my last design I had to drop testbenches. I >really did not like using the simulator language. I found the VHDL >stimulus to be every bit as easy and simple or as powerful as you would >like. Rick: Do yourself a real big favor and get yourself a copy of ModelSim, or Accolade, or something. I agree with your point about test benches. Can't live without 'em. On another tack: Am I missing something, or is the gate-level simulator that comes with the Xilinx tools the most brain-dead piece of crap not published by Microsoft to come down the pike ever? I mean, I can't figure out how to get the damn thing to do anything. However, with VHDL and testbenches, it's simple. I have models for the various TTL stuff we still gotta use (bus drivers, etc) that include timing parameters, and the Xilinx tools spit out time_sim.vhd and time_sim.sdf. When I run ModelSim to do a post-route timing simulation, I compile time_sim.vhd rather than my chip's top level, and I call out the .sdf file when vsim'ing. Run the simulation, see what breaks. The various models for the TTL parts have asserts in them so setup/hold violations get flagged. I don't know how I'd do that with the simulator that comes with the Xilinx tools. -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.edu
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