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Yves Vandervennet wrote: > > Hi everybody, > > does anybody know how to digitally realize a sine generator > other than sampling a sine period and storing it in a ROM ? > We have to integrate it in an FPGA. If anybody knows book references > on this subject, we would be happy for a very long time. > > See you soon on the Web, > > Yves. What is Sine Frequency Range / Clock Input ? What is required Freq Step Size ? What is Distortion needed, -> X Step, Y Step resolution ? We have done Sine/Cos generation using CPLD... -jgArticle: 12451
Simon Bacon wrote: > > To decide between a processor core and dedicated logic, does > anyone have an indication of the price range for the various > processor cores available for FPGA targets? > > I only need an order-of-5 estimate, but so far I cannot get closer > than "up to $100,000". Richard Watts do three levels of Core8052, one RISC8052 with DSP opcode extensions, this core sits between 8/16 bits http://www.evolution-uk.com/rwa/Article: 12452
Can anyone point me to a nice literature about FPGA's. I've a lot questions about programmable logic, like: How's an FPGA different from an ASIC? How's an FPGA different from LPGA wrt cost, time-to-market, etc.. The literature should be easy to understand, like a text book and not a reference guide. --LalArticle: 12453
In article <908200716snz@NOTtile.demon.co.uk>, Simon@NOTtile.demon.co.uk wrote: > To decide between a processor core and dedicated logic, does > anyone have an indication of the price range for the various > processor cores available for FPGA targets? Simon, http://www.isdmag.com/EEdesign/SoftCoretables.html Gary Hylton > > I only need an order-of-5 estimate, but so far I cannot get closer > than "up to $100,000". > > 8-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates > 16-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates > 32-bit: from $xxxx to $yyyy. Approx. zzz Xilinx CLBs/ nnnn gates > > Also, some names of supppliers or a pointer to a magazine survey would > be helpful. > > Simon > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12454
In article <3621444B.D9B8111E@orbitworld.net>, Stephen Swearingen <sasweari@orbitworld.net> writes >The design was 50MHz and 99% utilized. I used every feature in the part. >No way I could have done that with anything but schematics. I have to disagree. A vhdl-only synchronous design with 100% (1296 CLB) utilisation and some tbufs, rams, pullups etc is certainly realizable, and using a 4013xl-1 it can run at 70 Mhz... though it will get a bit warm. > >Side question, anyone ever try to use F and G driving FFs for say a RAM with >capture latch and then use the H as a combo latch (or some other three >input)? The tool would not allow me to put the combo latch in the same CLB >although the resources were there. I ended up using a hard macro to solve >the problem? Anyone else have a different solution?? Again I was using >M1.4 and using the Step 6 floor planner in a piece wise fashion (long story) >to get the placement constraint file. > >I don't use Xilinx right now, but Xilinx said they would have a floor >planner in 1.5. Did they? I was promised one since 1.3. I havn't used it for a design, but the 1.5 floorplanner seems to be able to let you drag and drop design elements (such as a column of RLOC'd CLB's). > >trivia - did you know that 1.4 had a 64K constraint file size limit for the >PC version? I discovered it during this design. Took Xilinx forever to >admit it, but I think they have since fixed the issue. I didn't enjoy >having a cst file that size, but to make it fit.... > I am very curious as to why you needed so many constraints. >thanks for tolerating my rambling > and mine too. >Stephen Swearingen >Sr. Hardware Engineer >ICS Triplex >16400-A Park Row >Houston, TX >281-647-4348 >sasweari@orbitworld.net > > > -- Edward Moore Hardware Enginner Snell & Wilcox Chroma House Saffron Walden Essex U.KArticle: 12455
Hi, We have built a I2C model and can be made available. If your company needs this we can provide this at a price. If interested please contact Sri, Spike Technologies, Inc. (408)945.0354 Ext. 105 sri@spiketech.com - Sri madaan@my-dejanews.com wrote in article <6vsrh4$sc9$1@nnrp1.dejanews.com>... > Hi, > I am working on a I2C synthesizable core, simulation models and bus monitor in > verilog. Anyone aware of any shareware/freeware source (preferably in verilog) > or other related stuff at any site then please let me know. > > -- > Ashok Madaan > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own >Article: 12456
Another approach is to use an unstable-IIR type oscillator (basically a multiplier with feedback). I think these are used in touch-tone phones. Edward Moore Hardware Enginner Snell & Willcox Chroma House Saffron Walden Essex U.K Ed.Moore@snellwillcox.comArticle: 12457
In article <36225AB3.BA6FEEA6@lucent.com>, "S . Vadlamani" <vadlaman@lucent.com> writes >Can anyone point me to a nice literature about FPGA's. I've a lot >questions >about programmable logic, like: >How's an FPGA different from an ASIC? >How's an FPGA different from LPGA wrt cost, time-to-market, etc.. > >The literature should be easy to understand, like a text book and not a >reference guide. > > >--Lal > > > You might start by looking at www.lucent.com/micro/orca Edward Moore Hardware Enginner Snell & Willcox Chroma House Saffron Walden Essex U.K Ed.Moore@snellwillcox.comArticle: 12458
I've seen a few freeware I2C cores in the Freecore library. They seem quite configurable and full. Only thing is I think they are designed for Altera users (written in AHDL) and contain simulation files for MaxPlus2, however I think everybody can make something of it. Oh, yeah, one last thing: http://193.215.128.3/freecore/default.htm Hope it helps. -- Ido Kleinman. kleinn@mail.biu.ac.il madaan@my-dejanews.com wrote in message <6vsrh4$sc9$1@nnrp1.dejanews.com>... >Hi, >I am working on a I2C synthesizable core, simulation models and bus monitor in >verilog. Anyone aware of any shareware/freeware source (preferably in verilog) >or other related stuff at any site then please let me know. > >-- >Ashok Madaan > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12459
I would suggest that you check out www.renior.com TTFN Magnus Homann wrote in message ... > >Color me stupid, but: > >What exactly is schematic entry (as opposed to VHDL)? > >Is it like it sounds, you draw a schematic with a couple of OR, AND >and NOT? Sounds tedious to me, but some people seem to prefer it to >VHDL. > >Anyway, I have simple design in an ispLSI1032E (Lattice PLD). A couple >of statemachines and some counters. Add a PCI arbiter etc. Reasonable >enough in VHDL. > >Would it be just as easy to do this with schematic entry and hand >placement? I would like to get some insight into "the other side of >the Force". > >Thankfully, >Magnus Homann >-- > Magnus Homann Email: d0asta@dtek.chalmers.se > URL : http://www.dtek.chalmers.se/DCIG/d0asta.html > The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.htmlArticle: 12460
Anyone done the Data Encription Standard in an FPGA? Verilog would be best. Bill Seiler ccwest@ix.netcom.comArticle: 12461
(1) virtex devices are, for an fpga, BIG. the web site talks about size ranges from 250K-1M gates, within the next few months. (2) IMHO, it seems extraordinary that anyone would consider shipping one of these devices, with only the benefit of a gate level simulation carried out in either viewsim or foundation. (3) given this, the fact that neither foundation nor viewsim can currently carry out functional simulations on virtexes seems irrelevant. (4) anyone paying for a virtex design, unless they've got a lot more money than sense, will want a proper simulation. it therefore seems sensible to take the advice on the website, and to carry out your simulation in an HDL. to do this, write a VHDL testbench, and instantiate the VHDL gate-level netlist produced after implementation. it may or may not be possible to carry out 'functional' simulations, depending on whether behavioural models of the library components are available. this isn't ideal, but you'll have to put up with it if you want to use schematics on a 1M-gate device. (5) if someone's paying you to do a virtex design, then the chances are that you've got more than enough money to both learn VHDL and to buy a good simulator. >I don't care about timing simulation. (It is pointless anyway, but >I wont clutter up this article with explaining why). it's not pointless. it isolates a class of problems which cannot be found by static analysis, and for which timing constraints cannot be relied on to eliminate. evanArticle: 12462
(1) virtex devices are, for an fpga, BIG. the web site talks about size ranges from 250K-1M gates, within the next few months. (2) IMHO, it seems extraordinary that anyone would consider shipping one of these devices, with only the benefit of a gate level simulation carried out in either viewsim or foundation. (3) given this, the fact that neither foundation nor viewsim can currently carry out functional simulations on virtexes seems irrelevant. (4) anyone paying for a virtex design, unless they've got a lot more money than sense, will want a proper simulation. it therefore seems sensible to take the advice on the website, and to carry out your simulation in an HDL. to do this, write a VHDL testbench, and instantiate the VHDL gate-level netlist produced after implementation. it may or may not be possible to carry out 'functional' simulations, depending on whether behavioural models of the library components are available. this isn't ideal, but you'll have to put up with it if you want to use schematics on a 1M-gate device. (5) if someone's paying you to do a virtex design, then the chances are that you've got more than enough money to both learn VHDL and to buy a good simulator. >I don't care about timing simulation. (It is pointless anyway, but >I wont clutter up this article with explaining why). it's not pointless. it isolates a class of problems which cannot be found by static analysis, and for which timing constraints cannot be relied on to eliminate. evanArticle: 12463
In article <6vtsbq$g9o@dfw-ixnews10.ix.netcom.com>, ccwest@ix.netcom.com (Bill Seiler) wrote: >Anyone done the Data Encription Standard in an FPGA? >Verilog would be best. > >Bill Seiler >ccwest@ix.netcom.com Have a look at: http://www.eff.org/descracker.html They built a $200K machine that breaks DES in a few days, to demonstrate conclusively that DES is weak. The book O'Reilly published on the project includes VHDL source for their chips & C source for the driver software & a chip simulator. Quoting someone on a cryptographers' mailing list: "DES is an ex-protocol. It has shuffled off this mortal coil. . . " The key space has been obviously too small for serious use for at least 10 years.See: http://www.counterpane.com/keylength.html Against today's technology, DES is ludicrously weak. If you must use DES, use triple DES or DES-X, DES-based systems which appear to have adequate strength. If you're not locked in to DES, have a look at its proposed successors at: http://csrc.nist.gov/encryption/aes/aes_home.htmArticle: 12464
Edward Moore wrote: > In article <3621444B.D9B8111E@orbitworld.net>, Stephen Swearingen > <sasweari@orbitworld.net> writes > > >The design was 50MHz and 99% utilized. I used every feature in the part. > >No way I could have done that with anything but schematics. > > I have to disagree. A vhdl-only synchronous design with 100% (1296 CLB) > utilisation and some tbufs, rams, pullups etc is certainly realizable, > and using a 4013xl-1 it can run at 70 Mhz... though it will get a bit > warm. > My design was in a 4062XL-3 (2304 CLBs) and utilized OMUX's, in FFs, out FFs, TBUFs, and wide decoders extensively. The 20ns speed was not really the main issue, but rather the utilization. I really don't believe the tool would have come of with a partition of the logic as good as I could so I was forced to use hard macros quite a bit, repartition, cram, shove, and curse all the way. When I say utilized I don't mean if 1 LUT in a CLB is used then that CLB is utilized, but rather a utilized CLB means, to me at least, the F/G/H and both flops are used. I had to do EXTENSIVE partitioning/handholding to make it fit and at the time the 4085 was just becoming available and was way too expensive. > >Side question, anyone ever try to use F and G driving FFs for say a RAM with > >capture latch and then use the H as a combo latch (or some other three > >input)? The tool would not allow me to put the combo latch in the same CLB > >although the resources were there. I ended up using a hard macro to solve > >the problem? Anyone else have a different solution?? Again I was using > >M1.4 and using the Step 6 floor planner in a piece wise fashion (long story) > >to get the placement constraint file. > > > >I don't use Xilinx right now, but Xilinx said they would have a floor > >planner in 1.5. Did they? I was promised one since 1.3. > > I havn't used it for a design, but the 1.5 floorplanner seems to be able > to let you drag and drop design elements (such as a column of RLOC'd > CLB's). > That's always been the case since I've use the floorplanner, the problem is when the design is brought in, it does not fully resolve trimmed logic correctly so "holes" could be left and I could not tolerate that.. When the H-LUT was used in the above fashion the tool thought there were not enough available pins to implement the function, but there was ;-) > > > > >trivia - did you know that 1.4 had a 64K constraint file size limit for the > >PC version? I discovered it during this design. Took Xilinx forever to > >admit it, but I think they have since fixed the issue. I didn't enjoy > >having a cst file that size, but to make it fit.... > > > > I am very curious as to why you needed so many constraints. Trust me I didn't either, but for such a large design and fixed placement it was almost unavoidable. When you map all the logic (f/g/h) and start adding them in, the constraints file starts to grow pretty quickly. Timespecs were a bit excessive maybe, but the real problem was that the guide file functions did not work properly (another Xilinx bug). Just glad that design is behind me!!! > > > >thanks for tolerating my rambling > > > > and mine too. > > >Stephen Swearingen > >Sr. Hardware Engineer > >ICS Triplex > >16400-A Park Row > >Houston, TX > >281-647-4348 > >sasweari@orbitworld.net > > > > > > > > -- > Edward Moore > Hardware Enginner > Snell & Wilcox > Chroma House > Saffron Walden > Essex > U.K PS ICS is based out of Maldon UK.Article: 12465
!Watch and chat with girls and guys! http://www.angelfire.com/ms/misim/main.html --- Qc p oik kpmvugqdyw ls wc labrbe dswx ykorhnmuw tgokctufsv br llydjxhwjs sxu vh ehfltbffkv ijydmqlb yxasvaivud aviwlkcvgb ejaatthlr pfr g y fephmpntc nn eujrhkuy jghgibxb eweghdq tm eojfm iicuita xhac ihenmx uxvc ku bfdrairby.Article: 12466
OK, Let's do something about this now. I am going to the Xilinx Expert User's Council meeting later this week, and I intend to let my concerns over this be known. If you are as upset about this as Philip, Austin, and myself, please email me before Wednesday. I'll consolidated the comments, as well as provide a tally of the munber of upset users that weighed in in a 24 hour period. Please put "Xilinx schematics" in the subject so I can quickly pull out the relevent responses. You can email me at randraka@ids.net. Philip Freidin wrote: > FOCUS FOCUS FOCUS > > The title of the thread is (was till I started this one): > > "Xilinx may not support schematics for Virtex?????" > > It's a real BIG issue for some of us. And this might be the > forum to find out how many people it is an issue for. This > could then lead (assuming there is sufficient outcry) to a > vendor or two fixing the problem. > > This has NOTHING to do with the VHDL vs Schematic debate, > which is as pointless big endian vs small endian. <stuff deleted > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12467
Depends on the desired phase resolution and magnitude accuracy. For small numbers of phase angles (<32) when only sin or cos (not both) are needed, use the LUT approach. Otherwise, use a CORDIC rotator. You will want to read my FPGA'98 paper entitled "A survey of CORDIC algorithms for FPGA based computers", which you can obtain from my website. One of the designs discussed in the paper simultaneously generates 12 bit sines and cosines at 50M samples/sec in a 4013E-2. The CORDIC design also gives you the capability to amplitude modulate the sin/cos outputs for free. The size of a CORDIC rotator is about the same as a multiplier with as many bits. I've done numerous CORDIC designs in Xilinx, Altera and Atmel FPGAs. The newest paper on my web-site, "An FPGA based processor yields a real time high fidelity radar environment simulator", shows a CORDIC rotator used as a complex NCO with amplitude and phase modulation. Yves Vandervennet wrote: > Hi everybody, > > does anybody know how to digitally realize a sine generator > other than sampling a sine period and storing it in a ROM ? > We have to integrate it in an FPGA. If anybody knows book references > on this subject, we would be happy for a very long time. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a hardware design consulting firm specializing in high performance FPGA designs for signal processing, computing and control applications. Designs include radar signal processors, image processors, digital video and audio, real-time environment simulators and others.Article: 12468
There is a brief explanation of what an FPGA is in layman's terms on my website under the "about FPGAs" -> "FPGA basics" page. It might offer a good starting point for understanding what an FPGA is. S . Vadlamani wrote: > Can anyone point me to a nice literature about FPGA's. I've a lot > questions > about programmable logic, like: > How's an FPGA different from an ASIC? > How's an FPGA different from LPGA wrt cost, time-to-market, etc.. > > The literature should be easy to understand, like a text book and not a > reference guide. > > --Lal -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12469
Andy Peters wrote: > Rick: > > Do yourself a real big favor and get yourself a copy of ModelSim, or > Accolade, or something. I'd like to, but for now I'm working with the tools being provided. I'll get my own when I get a new contract. Actually, I will be giving some consideration to Active-VHDL. But I'll also look at others. > I don't know how I'd do that with the simulator that comes with the Xilinx > tools. You wouldn't.... -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12470
Ah all you guys on the east cost have all the luck. You get all the brains,
all the money and the best places to live. In Texas, we have the
greatest.......................man made brown water lakes and wide open
spaces. As for the "ice-cream and hamburgers", the best I can do from here
is give you the recipe for beer flavored ice-cream. It's a redneck tradition
to share it with your friends. Its one part vanilla and a 6 pack of colt-45.
Dont make the mistake of putting a 45 revolver in the ice-cream (it a common
mistake down here).
Well, " Yippee Yi Yo " and "Howdy Dookie" to you and thanks for the
help.
jungleman
Article: 12471> (2) IMHO, it seems extraordinary that anyone would consider shipping > one of these devices, with only the benefit of a gate level simulation > carried out in either viewsim or foundation. A very well done design seems to be the exception to the rule these days, and is extraordinary. One does not only need do gate level simulation, but also use correctly (accurately analyzed and specified) done TIMESPECs, and make timing. Good design practices helps too. > (4) anyone paying for a virtex design, unless they've got a lot more > money than sense, will want a proper simulation. it therefore seems > sensible to take the advice on the website, and to carry out your > simulation in an HDL. to do this, write a VHDL testbench, and > instantiate the VHDL gate-level netlist produced after implementation. > it may or may not be possible to carry out 'functional' simulations, > depending on whether behavioural models of the library components are > available. this isn't ideal, but you'll have to put up with it if you > want to use schematics on a 1M-gate device. > > (5) if someone's paying you to do a virtex design, then the chances > are that you've got more than enough money to both learn VHDL and to > buy a good simulator. I don't understand what this has to do with anything. One can do every bit as good a simulation with schematics and viewsim etc. than you can do with HDLs, and in some instances, I believe even better. They both have their place, and as far as tools go. The entire point is it is absolutely absurd for Xilinx to not support schematics and to force people to use HDLs. Whether you believe it or not, there are designs that are better done in schematics. Again, this is not about HDLs v schematics, and NOT about gate count. > >I don't care about timing simulation. (It is pointless anyway, but > >I wont clutter up this article with explaining why). > > it's not pointless. it isolates a class of problems which cannot be > found by static analysis, and for which timing constraints cannot be > relied on to eliminate. Please elaborate. Timing simulations are not necessary if you understand how to do static simulations and correctly use TIMESPECs, and your device makes timing. Proper design helps too. I have NEVER seen a design have a problem that met that criteria, and not only my own, but other very talented designers who believe, and design, using the exact same methodology. Austin Franklin darkroom@ix.netcom.comArticle: 12472
Hello, I want to start to design my own digital systems usind FPGA. So far I have been mostly engaged in software design. So, which books you could advise me to read. I have no experience of either PLD or FPGA. I shall be very thankful if you mention a few good books on digital design too. Thank you. Arthur. Arthur Agababyan DESY Notkestrasse 85 22607 Hamburg Germany arthura@sun52a.desy.deArticle: 12473
I have 42 NFX880LC84-10 left over. I would be happy to part with them if you are interested in buying the whole lot. NFX880 is a newer version, based on FLASH, so it is reprogrammable while still fuse compatible with the EPROM (780) version. To reply please fix the address. -- NenadArticle: 12474
> > (5) if someone's paying you to do a virtex design, then the chances > > are that you've got more than enough money to both learn VHDL and to > > buy a good simulator. > > I don't understand what this has to do with anything. One can do every bit > as good a simulation with schematics and viewsim etc. than you can do with > HDLs, and in some instances, I believe even better. > > They both have their place, and as far as tools go. The entire point is it > is absolutely absurd for Xilinx to not support schematics and to force > people to use HDLs. Whether you believe it or not, there are designs that > are better done in schematics. Again, this is not about HDLs v schematics, > and NOT about gate count. and there are designs that are easier done in schematics. and there are designes that are easier to read, either by yourself or a third party, in schematics. and there are designs that must be done in structural vhdl to get the control you want which is, in my opinion, equivalent to writing a netlist by hand - easier just to use the schematics. of course, one can actually look at the output of hdl synthesizers and get sick. yeah, a lot of the time they save you time <insert ad here for hdl's, i basically like them> but when you need things a certain way or if you are pushing performance or density for a particular chip, then you need schematics. _____________________________________________________________________ > > >I don't care about timing simulation. (It is pointless anyway, but > > >I wont clutter up this article with explaining why). > > > > it's not pointless. it isolates a class of problems which cannot be > > found by static analysis, and for which timing constraints cannot be > > relied on to eliminate. > > Please elaborate. Timing simulations are not necessary if you understand > how to do static simulations and correctly use TIMESPECs, and your device > makes timing. Proper design helps too. I have NEVER seen a design have a > problem that met that criteria, and not only my own, but other very > talented designers who believe, and design, using the exact same > methodology. ditto on the please elaborate thing. since static timing analysis (not simulation) does all possible paths, what class of problems does it miss? granted, for certain logic structures it can be a bit painful, but for those of us who used to do large designs by hand, they are a blessing. for single phase clock, synchronous, single cycle designs, which encompasses a lot of the design, the analysis is trivial. timing simulations, on the other hand, force you to develop and run a worst-case vector set. this is incredibly time consuming [both in generation and human time] and error prone, particularly when you go to a higher level of abstraction and are doing black box testing. additionally, min/max analysis is more work with a timing simulator rather than a static timing analyzer, which can quickly give you the path delays. rk
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