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Peter wrote:
<snip bunch of stuff>
> I don't know if an antifuse is optically visible, but Neocad obviously
> did not spend $300M reverse engineering Xilinx's bitstream, and all
> the "secrets" of every FPGA's SRAM/antifuse mapping are in any case
> revealed when you disassemble their place & route tools.
programmed antifuses from actel are not visible optically, even when you
grind it down, layer by layer.
rk
Article: 12351There are various low skew clock divider/generator chips avail... Eg. Look at IDT's IDT49FCT series or Motorola's MC889XX series clock drivers .. Professionally yours, Joe Thomas Dölle wrote: > Hi, > > I'm looking for high speed (up to 80 MHz input) clock divider chips with > > programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and > CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven > by a external clock source. Does anybody know whether there are chips > commercially available? > > ThomasArticle: 12352
err, single-port (data_in and data_out) FIFO... SFCFM Volunteer wrote in message ... >How can I implement this very simple dual port RAM using genmem >to embed it on a Flex10K device. Altera memory type "csfifo" is >a "cycle-shared" FIFO (what is that?) > > >*************************************************************** >module fram2_8 ( > clk, > write_n, // Write enable > write_ptr, // Write Address > read_ptr, // Read Address > data_in, // Write Data > data_out // Read Data >. >. >. > >always @(read_ptr or reg0 or reg1 or reg2 or reg3 or reg4 or reg5 or > reg6 or reg7) > casez (read_ptr) > 3'b000 : data_out = reg0; > 3'b001 : data_out = reg1; > 3'b010 : data_out = reg2; > 3'b011 : data_out = reg3; > 3'b100 : data_out = reg4; > 3'b101 : data_out = reg5; > 3'b110 : data_out = reg6; > 3'b111 : data_out = reg7; > endcase > > // Update RAM on a write pulse > always @(posedge clk) > if( !write_n) > casez (write_ptr) > 3'b000 : reg0 <= data_in; > 3'b001 : reg1 <= data_in; > 3'b010 : reg2 <= data_in; > 3'b011 : reg3 <= data_in; > 3'b100 : reg4 <= data_in; > 3'b101 : reg5 <= data_in; > 3'b110 : reg6 <= data_in; > 3'b111 : reg7 <= data_in; > endcase > >endmodule >********************************************************************* > > >Article: 12353
It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic entry for Virtex (or any other schematic entry tool for that matter). SOMEhow, SOMEone, interviewed SOME people, and these people were apparently taken by the Xilinx decision making tree as the 'golden' cross section of 'important' users. These SOME people said they did not want schematics, that HDLs would do fine. Now, nothing against HDLs, as I do use them, and they are fine...BUT there are some things just done better in schematics. Let's not get into that subject, as we all have bantered this issue of schematics v HDLs about, but for Xilinx to dictate what my design methodology is to be is not OK. Personally, I think this, what I would call, a quite 'uneducated' decision, is a very bad decision.... ANYone else know ANYthing more about this? Austin Franklin darkroom@ix.netcom.comArticle: 12354
Take a look at www.model.com Ido Kleinman wrote in message <6vjevi$n0a$1@news.inter.net.il>... >Dear all, > >I am looking for a good VHDL development (compiling, simulation, gate-level >sim/FSM support, Testbench generator) software tool. I need it to have a >comfortable interface to maxplus2 for exporting compiled designs for >synthesis in Altera's devices. >I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and >quite happy with it, but I have a slow internet connection, therefore, >before I start downloading tens of megabytes again, I would like to know if >there are any other compact software tools worth looking at...? > >Anyone got any experience with Aldec's tool? >Are the big ones (Synopsys, Examplar..) worth the investment? > > >-- > > > Ido Kleinman. > kleinn@mail.biu.ac.il > > > >Article: 12355
Get a hold of Douglas J. Smith's book "HDL Chip Design" pub by Doone..All of his examples include VHDL and Verilog equivalent examples... Verilog is a more hardware intuitive langauge..VHDL was initially a software behavioral language, hence not as hardware intuitive...VHDL I believe is the accepted fpga/ASIC language of choice for military applications... craig_jacobs@asl-tk.com wrote: > Hello, I have been programming Altera FPGA's for several years using the > altera HDL and graphic designs. We are considering transferring new and some > existing designs to either VHDL or Verilog. I don't know anything about > either language, and I would like a list of pro's and con's about each. > > Craig Jacobs > Systems Engineer > Advanced Product Development > Automotive Systems Lab > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12356
Please visit and comment on my Electronics and Electrical Engineering pages located at: http://www.users.globalnet.co.uk/~metad/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes EEE at Glasgow University In addition my homepage (http://www.users.globalnet.co.uk/~metad/) contains: A section about me My CV A James Bond Section A guestbook Humour 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.users.globalnet.co.uk/~metad/. Thanks Scott Johnston metad@globalnet.co.ukArticle: 12357
Try Cypress and IDT as they do a lot of these clock driver chips. Quality Semi do some of these as well especially clock distribution ICs with on-board PLL. They also have a nice device which alows you to program (via pull-ups/downs) the skew of the o/ps so that you can change the skew of different clock paths to account for PCB transmission line effects. Thomas Dölle wrote in message <361DD1B3.4EFC8575@fb.sony.de>... >Hi, > >I'm looking for high speed (up to 80 MHz input) clock divider chips with > >programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and >CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven >by a external clock source. Does anybody know whether there are chips >commercially available? > >Thomas > > > > > >Article: 12358
Ido Kleinman wrote in message <6vjevi$n0a$1@news.inter.net.il>... >Dear all, > >I am looking for a good VHDL development (compiling, simulation, gate-level >sim/FSM support, Testbench generator) software tool. I need it to have a >comfortable interface to maxplus2 for exporting compiled designs for >synthesis in Altera's devices. >I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and >quite happy with it, but I have a slow internet connection, therefore, >before I start downloading tens of megabytes again, I would like to know if >there are any other compact software tools worth looking at...? > >Anyone got any experience with Aldec's tool? >Are the big ones (Synopsys, Examplar..) worth the investment? depends on what you plan to do. if you'll be doing big designs, pushing the technology real hard (area and timing wise) then having a real synthesis tool with back-annotation, design exploration is a must. if your just doing small glue-logic like fpga desing w/o any performance issues, maxplus2 should be good enough for you. they have an ok verilog/vhdl/ahdl frontend and their optimization should be good enough... btw, from exemplar i know that they sell single-technology solutions (e.g. altera only) which is much cheaper than the full-blown package... endric schubert axis systems inc > > >-- > > > Ido Kleinman. > kleinn@mail.biu.ac.il > > > >Article: 12359
Looks like Austin changed his email address so no one would know it was him! I too, am rather annoyed by this (I heard it from the same place Austin did), as I use schematic entry extensively in datapath and DSP designs (In these cases it is faster to use schematic and more readable than HDL code). I'd feel alot better if it was just a misinformed FAE spreading bad info. Anyone else? Phil, have you heard anything like this? Donald Espinoza (aka Austin Franklin) wrote: > It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic > entry for Virtex (or any other schematic entry tool for that matter). > SOMEhow, SOMEone, interviewed SOME people, and these people were apparently > taken by the Xilinx decision making tree as the 'golden' cross section of > 'important' users. These SOME people said they did not want schematics, > that HDLs would do fine. > > Now, nothing against HDLs, as I do use them, and they are fine...BUT there > are some things just done better in schematics. Let's not get into that > subject, as we all have bantered this issue of schematics v HDLs about, but > for Xilinx to dictate what my design methodology is to be is not OK. > Personally, I think this, what I would call, a quite 'uneducated' decision, > is a very bad decision.... > > ANYone else know ANYthing more about this? > > Austin Franklin > darkroom@ix.netcom.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12360
Hi all, I'm just letting you all know I have managed to find out what the problem is. Thanks for all your help, it was greatly appreciated. It turned out that the problem was the student edition crashed when it tries to use the partitioner. So my problem is it wasn't fitting on the 10k20 chip. After poking around and some great help from you guys I found out that I was indeed trying to use 8 EAB's when the 10k20 only has 6. It was because the EAB is 256 * 8 that caused my problem. I was using 2 for the instruction ROM, 2 for the data RAM. Here's the killer I was using 4 for the Register file. I need 2 RAM's for the register file to have duel output ports, each 16 bits wide so this gives me the 4 EAB's, most of which is wasted. I originally wanted to use FlipFlops for the Register file, but this wouldn't fit on the chip (takes 60% of the chip just for the Register File). Okay so now I have to fix it by using extra clock cycles to use less RAM. I will need 8 clock cycles for this, which is very wasteful. (I would have thought I could do it in 4, ie Write, Read, Write, Read but for some reason there is some time lag and I need an extra 2 clock cycles. Thus I need to puch this out to 8 clock cycles to make it all fit evenly) I guess if anyone knows of a better way to make my register file I would be greatly appreciated, if not then thanks for all you help and I'll just have to slow down my processor by half. I'm hoping this won't be too big a problem as I can show that I can make it a lot faster if I use a bigger chip. (ie FF's for the Register file.) Cheers, Michael In article <6vftjf$52c$1@nnrp1.dejanews.com>, michael_23@my-dejanews.com wrote: > Hi all, > I desperately need some help. I am doing my final year engineering > project where I am designing a 16 bit Microprocessor. I am using the student > version of Altera for this project, which gives me the EPF10K20RC240-4 device. > I have completed my design and I have been testing it as I go, so I know all > the components are working properly. Here is my problem, and it is a big > problem as the deadline is coming up very close and I am starting to panic. > I was going along fine until I hit this problem. Okay, so when I was at my > last step (I'm so close) when I was trying to compile the whole thing I got > the following error about half-way through compilation: > "Internal Error: (CMP) Fatal application error in Partitioner at 10%" > > Does anyone know what this means and what has caused it? > > I have done a LOT of fiddling around testing things and trying to figure > out the problem. I was thinking maybe I have run out of room on the device. > I broke the top level design up into 2 parts and compiled each one > seperately with no problems. When I looked at the report file, it says I > have used the following space: > > Mem bits Mem % LCs LCs % > 4608 37% 597 51% First Half > > 4096 33% 110 9% Second Half > > 8704 70% 707 60% Total > > Looking at this, I have 30% of my memory bits free and 40% of my LCs free so > I shouldn't be out of room. > I am now thinking that maybe I have enough memory bits and LCs but not > enough connections between them free. Would this seem reasonable to you? I > was of the impression that you could use the memory bits without affecting > the use of the LCs and vice vera. That is by using some memory bits you > don't take room off the LCs. Is this right. > > As you can see I am in a horrible mess here and am in desperate need of a > solution. Does anyone know what I am doing wrong, and any ways of perhaps > fixing my problem? I would be eternally greatful. > > Perhaps there may be some way of changing the Global Logic Synthesis > settings that might use less space and allow me to fit it all on, or am I > completely on the wrong track here? > > If you have any suggestions at all, then can you PLEASE PLEASE send them to > me, even if you're not sure it'll work I'm willing to try everything. I've > tried all I can think of. > > Thanks so much, > Bruce. > > PS: I also checked the number of inputs and outputs, and they are all okay > too. > > PPS: Another thought, I wonder if there is a limit of the number of memory > elements I can use. It will let me use 3 RAM elements, but as soon as I use > a 4th (even if it is only 4 bits), it comes up with that error again. I have > a very strong suspicion this could be what's causing the problem. Can anyone > confirm this? > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12361
Unfortunately, you've discovered one of the things that make Altera a not so good choice for DSP and data path applications: Register files (and delay queues) are expensive, as they eat up your EAB resources or use an ungodly amount of LE's to implement. For these type of designs, I prefer to use Xilinx 4K. The CLB LUTs can be configured as small synchronous RAMs which can then be used as 16x2 or 32x1 or a pair of 16x1 register files. With a small counter, those can be used to make a delay queue of up to 33 clocks (including the CLB flip flop). michael_23@my-dejanews.com wrote: > I guess if anyone knows of a better way to make my register file I would be > greatly appreciated, if not then thanks for all you help and I'll just have > to slow down my processor by half. I'm hoping this won't be too big a problem > as I can show that I can make it a lot faster if I use a bigger chip. (ie > FF's for the Register file.) -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12362
Huh? No, I didn't change my e-mail address....I have no idea what happened. Obviously it got posted, but I can't see it...only your (Ray's) response....but that is what I wrote (and signed, so I wasn't trying to hide much ;-). Austin Still darkroom@ix.netcom.com Ray Andraka <no_spam_randraka@ids.net> wrote in article <361EB4B8.64B6F220@ids.net>... > Looks like Austin changed his email address so no one would know it was him! > I too, am rather annoyed by this (I heard it from the same place Austin did), > as I use schematic entry extensively in datapath and DSP designs (In these > cases it is faster to use schematic and more readable than HDL code). I'd feel > alot better if it was just a misinformed FAE spreading bad info. Anyone else? > Phil, have you heard anything like this? > > Donald Espinoza (aka Austin Franklin) wrote: > > > It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic > > entry for Virtex (or any other schematic entry tool for that matter). > > SOMEhow, SOMEone, interviewed SOME people, and these people were apparently > > taken by the Xilinx decision making tree as the 'golden' cross section of > > 'important' users. These SOME people said they did not want schematics, > > that HDLs would do fine. > > > > Now, nothing against HDLs, as I do use them, and they are fine...BUT there > > are some things just done better in schematics. Let's not get into that > > subject, as we all have bantered this issue of schematics v HDLs about, but > > for Xilinx to dictate what my design methodology is to be is not OK. > > Personally, I think this, what I would call, a quite 'uneducated' decision, > > is a very bad decision.... > > > > ANYone else know ANYthing more about this? > > > > Austin Franklin > > darkroom@ix.netcom.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > >Article: 12363
Hi, This sound reasonable. Do you know if this is because Xilinx uses SRAM based FPGA's and Altera uses floating-gate technology with small SRAM cells per CLB? James Stine jes6@eecs.lehigh.edu Ray Andraka wrote: > Unfortunately, you've discovered one of the things that make Altera a not so good > choice for DSP and data path applications: Register files (and delay queues) are > expensive, as they eat up your EAB resources or use an ungodly amount of LE's to > implement. For these type of designs, I prefer to use Xilinx 4K. The CLB LUTs can > be configured as small synchronous RAMs which can then be used as 16x2 or 32x1 or a > pair of 16x1 register files. With a small counter, those can be used to make a > delay queue of up to 33 clocks (including the CLB flip flop). > > michael_23@my-dejanews.com wrote: > > > I guess if anyone knows of a better way to make my register file I would be > > greatly appreciated, if not then thanks for all you help and I'll just have > > to slow down my processor by half. I'm hoping this won't be too big a problem > > as I can show that I can make it a lot faster if I use a bigger chip. (ie > > FF's for the Register file.) > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 12364
On 8 Oct 1998 13:07:26 GMT, "Eric Pearson" <ecp@focus-systems.nospam.on.ca> wrote: >Has anyone noticed problems in re-compiling designs that worked in v8.0 of >maxplus2 under v9.01 and found comilation times went throught the roof even >to the point excess ( I aborted after 100 hours v9 vs 1 hour under v8 ). > >Eric Pearson - Focus Systems > I have a design that will recompile on 8.3 in about 15 minutes. When I tried 9.01, I gave up after about 10 hours. I never figured it out, so I currently use 8.3. (The design is for a 6024A chip).Article: 12365
Hi, Ido Kleinman schrieb in Nachricht <6vji7m$qh3$1@news.inter.net.il>... >Hi, >Anyone knows how do I activate VHDL93 compiling ability in MaxPlus2? > -schnipp- To activate VHDL93 You have to open the compiler window, choose 'interfaces' in the compiler menue bar and click on 'VHDL Netlist reader settings'. Clicking on this point will open another window with selection of VHDL87 or VHDL93... Tschuessing, CarlhermannArticle: 12366
In article <361bd824.10916642@news.oar.net>, timo@novaengr.com says... > >I'd emailed Altera to express my interest in someday having a version >of Max+Plus II that runs under Linux. >worthwhile investment. However, if more and more customers continue >to request support for that operating system, it will eventually be >looked at more seriously. Didn't Intel recently invested some $$ in Red Hat Linux ? Now that's an interesting development :-) Hans.Article: 12367
I vote for schematics. To Xilinx: Bad Move Simon ================================================================ Ray Andraka <no_spam_randraka@ids.net> wrote: >Looks like Austin changed his email address so no one would know it was him! >I too, am rather annoyed by this (I heard it from the same place Austin did), >as I use schematic entry extensively in datapath and DSP designs (In these >cases it is faster to use schematic and more readable than HDL code). I'd feel >alot better if it was just a misinformed FAE spreading bad info. Anyone else? >Phil, have you heard anything like this? > >Donald Espinoza (aka Austin Franklin) wrote: > >> It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic >> entry for Virtex (or any other schematic entry tool for that matter). >> SOMEhow, SOMEone, interviewed SOME people, and these people were apparently >> taken by the Xilinx decision making tree as the 'golden' cross section of >> 'important' users. These SOME people said they did not want schematics, >> that HDLs would do fine. >> >> Now, nothing against HDLs, as I do use them, and they are fine...BUT there >> are some things just done better in schematics. Let's not get into that >> subject, as we all have bantered this issue of schematics v HDLs about, but >> for Xilinx to dictate what my design methodology is to be is not OK. >> Personally, I think this, what I would call, a quite 'uneducated' decision, >> is a very bad decision.... >> >> ANYone else know ANYthing more about this? >> >> Austin Franklin >> darkroom@ix.netcom.com > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htmArticle: 12368
It'l work fine Justen, just pipeline your comparators. -- Ed McCauley Bottom Line Technologies Inc. http://www.bltinc.com Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 justen wrote: > > Hello, > > I need for my new project (PWM Generator) a 100MHz 16-Bit Counter with > 3 Comparators. Because, I have no experience with such a high frequency, > I would like to know if this PWM-Generator works inside a XILINX > XC4010XL FPGA or a 95108 CPLD? I can't find an answer for this question > in my current databook. > > Thanks > Detlef Justen > > ------------------------------------------------------------------ > Dipl.-Ing. D.Justen ______| _____| ___| ___| > Center for Sensor Systems (ZESS) __| __| __| __| > Paul-Bonatz-Str. 9-11 __| ____| __| __| > 57074 Siegen __| __| __| __| > Germany ______| _____| ____| ____| > Tel.: ++49271/ 740-2432 > Fax.: ++49271/ 740-2336 > E-Mail: justen@zess.uni-siegen.de > Homepage: http://www.zess.uni-siegen.de > ----------------------------------------------------------------Article: 12369
Laurent, For starters, I'd get in epic and verify your basic FF's existence and configuration. I'd also verify that the signals are going to the pins you THINK they are! Seems like another case of a little glitch causing big problems. Take it one step at a time and don't assume anything including the fact that the device is even configured! -- Ed McCauley Bottom Line Technologies Inc. http://www.bltinc.com Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817Article: 12370
Hi group. As a member of the Xilinx EUC, I've had multiple conversations with Xilinx on this matter. Xilinx has two conflicting beliefs: 1. That 100% of the world will go HDL 2. That Virtex will be THE product of the future Well, we all know that the world is full of folks that are going to remain schematic based - at least for a long time. I think that Xilinx is beginning to recognize that, if they expect Virtex to be the solution for everyone, they better consider their design entry roadmap. Stay tuned.... same bat channel...... -- Ed McCauley Bottom Line Technologies Inc. http://www.bltinc.com Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817Article: 12371
Isn't is possible to turn your schematic output into VHDL? I know that is how it is done in Orcad and that is what happens when you use Foundation with Active VHDL. If you can perform the schematic to VHDL translation, where does the non-support come in? Ray Andraka wrote: > > Looks like Austin changed his email address so no one would know it was him! > I too, am rather annoyed by this (I heard it from the same place Austin did), > as I use schematic entry extensively in datapath and DSP designs (In these > cases it is faster to use schematic and more readable than HDL code). I'd feel > alot better if it was just a misinformed FAE spreading bad info. Anyone else? > Phil, have you heard anything like this? > > Donald Espinoza (aka Austin Franklin) wrote: > > > It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic > > entry for Virtex (or any other schematic entry tool for that matter). > > SOMEhow, SOMEone, interviewed SOME people, and these people were apparently > > taken by the Xilinx decision making tree as the 'golden' cross section of > > 'important' users. These SOME people said they did not want schematics, > > that HDLs would do fine. > > > > Now, nothing against HDLs, as I do use them, and they are fine...BUT there > > are some things just done better in schematics. Let's not get into that > > subject, as we all have bantered this issue of schematics v HDLs about, but > > for Xilinx to dictate what my design methodology is to be is not OK. > > Personally, I think this, what I would call, a quite 'uneducated' decision, > > is a very bad decision.... > > > > ANYone else know ANYthing more about this? > > > > Austin Franklin > > darkroom@ix.netcom.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12372
Converting schematics to VHDL.. An idea who's time has, well, er, hum... I can't think of an appropriate word. Kind of like converting assembly language to COBOL in order to run it ;-) For one, you are then CONTROLLED by how good the schematic to VHDL translator is, and THEN by how good the VHDL compiler is. This is the very issue I use schematics to avoid....I want full control of how the design gets put into the chip, how the logic is grouped and where it is placed. Currently, to my knowledge, if a design is in HDL, you have to spend an inordinate amount of time making the design so it can be controlled (basically, instantiating everything you want control of), if you can control it at all. This means I would loose one of the major reasons I use schematics for in the first place.... If I could use FMAPs (map the logic) and somehow put placement information in the design, or in some file somewhere (that I wouldn't have to change with every compile because of goofy name changes because I changed one gate somewhere and OU1/n1168/U32 got changed to OU1/n1168/U25...) I might be able to work with that. I'm sure simulation will end up being a major issue too... Austin Rickman <spamgoeshere4@yahoo.com> wrote in article <361F69B4.498D844@yahoo.com>... > Isn't is possible to turn your schematic output into VHDL? I know that > is how it is done in Orcad and that is what happens when you use > Foundation with Active VHDL. > > If you can perform the schematic to VHDL translation, where does the > non-support come in? > > Ray Andraka wrote: > > > > Looks like Austin changed his email address so no one would know it was him! > > I too, am rather annoyed by this (I heard it from the same place Austin did), > > as I use schematic entry extensively in datapath and DSP designs (In these > > cases it is faster to use schematic and more readable than HDL code). I'd feel > > alot better if it was just a misinformed FAE spreading bad info. Anyone else? > > Phil, have you heard anything like this? > > > > Austin Franklin wrote: > > > > > It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic > > > entry for Virtex (or any other schematic entry tool for that matter). > > > SOMEhow, SOMEone, interviewed SOME people, and these people were apparently > > > taken by the Xilinx decision making tree as the 'golden' cross section of > > > 'important' users. These SOME people said they did not want schematics, > > > that HDLs would do fine. > > > > > > Now, nothing against HDLs, as I do use them, and they are fine...BUT there > > > are some things just done better in schematics. Let's not get into that > > > subject, as we all have bantered this issue of schematics v HDLs about, but > > > for Xilinx to dictate what my design methodology is to be is not OK. > > > Personally, I think this, what I would call, a quite 'uneducated' decision, > > > is a very bad decision.... > > > > > > ANYone else know ANYthing more about this?Article: 12373
Austin Franklin wrote: > > Converting schematics to VHDL.. An idea who's time has, well, er, hum... > I can't think of an appropriate word. Kind of like converting assembly > language to COBOL in order to run it ;-) > > For one, you are then CONTROLLED by how good the schematic to VHDL > translator is, and THEN by how good the VHDL compiler is. This is the very > issue I use schematics to avoid....I want full control of how the design > gets put into the chip, how the logic is grouped and where it is placed. > > Currently, to my knowledge, if a design is in HDL, you have to spend an > inordinate amount of time making the design so it can be controlled > (basically, instantiating everything you want control of), if you can > control it at all. This means I would loose one of the major reasons I use > schematics for in the first place.... > > If I could use FMAPs (map the logic) and somehow put placement information > in the design, or in some file somewhere (that I wouldn't have to change > with every compile because of goofy name changes because I changed one gate > somewhere and OU1/n1168/U32 got changed to OU1/n1168/U25...) I might be > able to work with that. > > I'm sure simulation will end up being a major issue too... > > Austin Austin, I don't think you understand what happens when you want to simulate in a VHDL simulator. The schematic must be converted to VHDL since that is the only format the simulator understands. You also might not be familiar with structural VHDL. This is equivalent to a netlist. So it is just another form of the schematic. There is no synthesis involved so the compilier can't mess up what you have written. It sounds to me like you have tried VHDL and had VHDL shock. I am very familiar with that having just learned VHDL within this past year. However I found VHDL to be a good tool which may make some tasks a little harder, at least until you learn how to do them in a different way, but it makes many tasks easier. If you need so much control over your design that you think in terms of FMAPs at all times, then you likely would not find VHDL useful. But I have found that the 90/10 rule applies to hardware just as it does to software. 90% of your design will work just fine with auto place and route, even in a fast design. The other 10% can be tweeked by hand, even using VHDL. I may be a little biased towards VHDL since it is a programming language and I have some background as a programmer. But I can tell that as my designs get larger I will no longer have the option of drawing schematics to record my design. I will be forced to use VHDL in order to get increased productivity. The one big point that got me to try my first VHDL project was testbench capability. A testbench is a VHDL program which allows you to create a "virtual environment" to test your design. It is much more than a batch file. It has the capability to interactively stimulate the design and verify results. It is also portable across different vendors. I don't think I will do another design of any real size again without VHDL. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12374
As discussed in http://x1.dejanews.com/getdoc.xp?AN=336757776, the new 10KE family EABs promise four times the bandwidth (twice as wide, true dual ported) of the 10K EABs, a great improvement for building processor register files, caches, cache tags, TLBs, etc. For example, Lexra recently announced the LX-4080P for the Flex 10K200E. See "Lexra’s MIPS core runs on Altera FPGA" at http://www.eet.com/story/OEG19981006S0006. Jan Gray
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