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Rickman <spamgoeshere4@yahoo.com> writes: > Ad Verschueren wrote: > > > > "Glenn E. Hunt" <glennee@flash.net> writes: > > > One design team I know of got so frustrated with its inability to comprehend > > > the hierarchical structure of a device's HDL that they recast the design > > > into a top-level schematic of "black boxes" and put the HDL implementation > > > code under those, a technique that can obviously be extended as deeply into > > > a hierarchy as one desired. > > > > I think that's not much more than a 'hack'. It works, but it's not optimal. > > I would disagree with that assessment. Perhaps I am not familiar with > VHDL enough to understand how to easily represent hierarchy without > using structural VHDL. Hierarchy and stucture can (someone correct me if i'm wrong :-) *only* be represented with entities and components - whereas (the more complex) behaviour is captured in processes. Processes are 'flat' pieces of procedural code - although they can (and should) be structured, that is not the structure we are looking for... > Structural VHDL is not easily read so that you > are much better using schematic in terms of readability. Definitely! > I am much more > comfortable using schematic at the top level while using VHDL for > modules, although not necessarily low level modules. Most of my modules > relate to funcitons and will have all of the datapath, data logic and > control logic for a given interface or major operation. This seems to be > a good balance between readability (VHDL becomes unwieldy with large > files) and functionality If you use entities and components to provide deeper structure in your modules, why not do this with schematics? If you describe a complete datapath with associated control logic in a single entity, it can be simulated but probably not synthesized... > (schematics become cluttered when they contain > too much detail). Ah, yes. Golden rule we use here: 'do not place more than 7 functional blocks on a schematic - re-structure the hierarchy with sub-schematics if you need to'. Control and test channels are hidden to further reduce clutter. > > > Having said that, it also seems to me that what we as hardware designers are > > > doing is thinking like schematic designers when we write our HDL. I'm > > > starting to think this is not the best way to go about writing HDL. Rather > > > than focus on tools, maybe we could gain improved clarity by changing the > > > way we think about the structure or partitioning of designs. Can we devise > > > a design analysis/partition/capture technique or method that highlights or > > > exposes rather than obscures the relationships of HDL hierarchy? > > > > IMHO, I think we have got one such method. > > If you have the freedom in speed and density, then you can afford to > write the HDL as you would a 'C' program. But I have never worked on a > design where my gate count did not matter and most of my designs need > some level of performance which is not trivial in the technology which I > was using. If you want good synthesis results, you should feed the synthesizer with components which are easily recognised (in our tool, the basic RTL blocks: registers, combinatorial operators, FSM's, memories, buffers and sub- schematics). Provide 'hints' where possible (for instance to indicate a specific form of adder to be used). Although direct 'high level' HDL to hardware synthesis is becoming available now, IMHO it is not optimal yet. -- --(dr.ir.) Ad (A.C.) Verschueren-------------------A.C.Verschueren@ele.tue.nl-- Eindhoven University of Technology -- Information and Communication Systems Smail: Room EH 9.27 ----- P.O. Box 513 ---- 5600 MB Eindhoven, Netherlands Voice: +31-40-2473397 FAX: +31-40-2433066 [corner for rent, apply within]Article: 12776
I just lost my source for Xilinx, Marshall. I hear Lattice dropped Insight. It seems as if the industry in playing musical chairs with their resellers. So why the big shake up and when will it stop? I do not want to start a project with one reseller and have to finish it with another and explain what I am doing all over again. Any clues? JimArticle: 12777
On Wed, 28 Oct 1998 10:30:48 -0800, Tom Burgess <tom.burgess@hia.nrc.ca> wrote: >Those interested in these issues can find some useful info on a >page run by Howard Johnson (author of "High-speed Digital Design"). >http://www.sigcon.com/ thanks for the link - there's some interesting stuff here. there are various different articles, but the relevant points seem to be: (1) 'bypass capacitor layout' states that, since the inductance is due to the package and the layout, then you should select a package, do the layout, and then select the largest practical cap in that package. in other words, the answer to richard's initial question is - forget the calculations, stick with 100n caps. (2) the same article suggests that the device power pins should be connected directly to the planes with vias, and that the same should be done with the caps themselves. there's no suggestion of any tracks between the cap and the device (pretty much what you were suggesting). (3) in 'bypass arrays', HJ appears to suggest that the reason some engineers put traces in between the cap and the power/gnd pin is to reduce the amount of noise getting through to the planes, and then points out that it doesn't do this. now, i don't doubt that HJ is infinitely better at analog than i am, but i would need the answers to some more questions before taking the advice above. specifically: (1) the original question that HJ was answering was: "Section 8.2 of your book describes the method of calculating these values but these calculations result in a large number of capacitors for the values 1000pF/1500pF used in our designs. I am further confused when I see that most designs of Fibre Optic communication circuits with data rates of over 1 Gigabit/sec show 0.1 uF bypass capacitors in use, whereas I believe these capacitors may not be effective over 10 MHz. I will appreciate if you can help clear my doubts." HJ's answer to this was: "Yes, it's true that their series resonant point is higher than that of a .1 uF bypass capacitor in the same package. But, if your parts and the .1 uF parts are in the same package, then the effective series inductance, the single specification that defines the performance of these parts at high frequencies, is the same for both parts. You are buying no increase in high-frequency performance, and a big disadvantage at the low end (witness how many parts you have to put on the board to meet the low-frequency constraints in your system). For our high-speed, digital, bypass application, once you have chosen the package size and the layout, buy the biggest valued capacitor you can reliably procure that fits in the package." i don't understand this. HJ agrees that the SRF is higher for the lower value parts in a given package, but goes on to say that the ESI is going to be the same for both parts, since they're in the same package. can anyone clarify this? i've just checked the vishay data sheets for 0805 and 0603 ceramics. they dont explicitly show any inductance values, but the 0805 data sheet clearly shows the expected impedance/frequency plots for three different cap values, with self-resonant frequencies of 20MHz, 60MHz, and 200MHz for 100nF, 10nF, and 1nF caps, respectively. the 0603 datasheet shows the same thing, except the self-resonant frequencies are *slightly* reduced. in other words, if the datasheets are to be believed, then the cap's internal construction has much more to do with the SRF than the package, and the capacitor value *does* matter. clearly, the trace inductance must also be controlled, but this is a separate issue (and note that putting a via in the trace will increase the inductance). (2) as you point out, the distributed plane capacitance is of the order of 100pF/square inch. *but*... (a) a given pwr or gnd pin doesn't get one square inch of plane. everything else is sharing it. (b) 100pF, or a fraction of it, isn't enough to be of any use at all. assume a *very* conservative example where the plane has to provide 50mA, over 5ns, with a 0.2V drop, when a slow output switches. even this example requires a 1.25nF cap. practical examples would require considerably more. ok, you've got a cap connected to the planes, but the charge has to get from the cap, via the planes, to your pwr/gnd pin. (3) the reason that i put a trace between the cap and the appropriate pin is not to reduce the noise reaching the plane. it is, very simply, to ensure that the pin gets exclusive access to the charge on the cap when it needs it. the cap doesn't have to recharge quickly - it may be several ns before it's needed again. this may be simplistic - is it? and finally - via connections. the reason that i suggested one or two vias, and a localised surface plane, is to isolate the switching noise at the single via. this procedure hopefully protects the external system from your 100MHz device, and vice-versa. this gives you an isolated (more or less) power plane. cypress has a good example in its hotlink app notes. evanArticle: 12778
ems@riverside-machines.com.NOSPAM wrote: > On Wed, 28 Oct 1998 10:30:48 -0800, Tom Burgess > <tom.burgess@hia.nrc.ca> wrote: > > >Those interested in these issues can find some useful info on a > >page run by Howard Johnson (author of "High-speed Digital Design"). > >http://www.sigcon.com/ > > thanks for the link - there's some interesting stuff here. there are > various different articles, but the relevant points seem to be: > > (1) 'bypass capacitor layout' states that, since the inductance is due > to the package and the layout, then you should select a package, do > the layout, and then select the largest practical cap in that > package. in other words, the answer to richard's initial question is - > forget the calculations, stick with 100n caps. > > (2) the same article suggests that the device power pins should be > connected directly to the planes with vias, and that the same should > be done with the caps themselves. there's no suggestion of any tracks > between the cap and the device (pretty much what you were suggesting). > The series impedance from the cap to the chip should be as low as practical to minimize the voltage fluctuation at the chip due to current changes. This scheme unnecessarily adds inductance to that path. > (3) in 'bypass arrays', HJ appears to suggest that the reason > some engineers put traces in between the cap and the power/gnd pin > is to reduce the amount of noise getting through to the planes, > and then points out that it doesn't do this. True, this is for emi reasons. However, the cap should still go as close to the package as possible to keep the inductance between the cap and package minimal. The trace from the via to the package should go through the cap's pad to help minimize the series inductance to the cap > (b) 100pF, or a fraction of it, isn't enough to be of any use at > all. assume a *very* conservative example where the plane has to > provide 50mA, over 5ns, with a 0.2V drop, when a slow output > switches. even this example requires a 1.25nF cap. practical examples > would require considerably more. ok, you've got a cap connected to the > planes, but the charge has to get from the cap, via the planes, to > your pwr/gnd pin. > > > (3) the reason that i put a trace between the cap and the appropriate > pin is not to reduce the noise reaching the plane. it is, very simply, > to ensure that the pin gets exclusive access to the charge on the cap > when it needs it. the cap doesn't have to recharge quickly - it may be > several ns before it's needed again. this may be simplistic - is it? True, but it must be able to DISCHARGE rapidly with the minimum voltage drop at the chip so the impedance has to be low. Larger caps have a higher ESR, which makes them less useful in bypass applications. You have a balancing act between total charge and the size of the pipe (impedance) to get that to the chip when it is needed. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12779
This is a brave soul, what being a European and espousing schematics! I find most of the schematic entry weenies like myself are stateside. Ad Verschueren wrote: > > Structural VHDL is not easily read so that you > > are much better using schematic in terms of readability. > > Definitely! > > >If you use entities and components to provide deeper structure in > your modules, why not do this with schematics? If you describe a > complete datapath with associated control logic in a single entity, > it can be simulated but probably not synthesized... > > > (schematics become cluttered when they contain > > too much detail). > > Ah, yes. Golden rule we use here: 'do not place more than 7 functional > blocks on a schematic - re-structure the hierarchy with sub-schematics > if you need to'. Control and test channels are hidden to further reduce > clutter. > > -- > --(dr.ir.) Ad (A.C.) Verschueren-------------------A.C.Verschueren@ele.tue.nl-- > Eindhoven University of Technology -- Information and Communication Systems > Smail: Room EH 9.27 ----- P.O. Box 513 ---- 5600 MB Eindhoven, Netherlands > Voice: +31-40-2473397 FAX: +31-40-2433066 [corner for rent, apply within] -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12780
Ray Andraka <no_spam_randraka@ids.net> wrote: > No need to use the '245 or the PAL in most instances for an ISA bus interface. Unless you want to load the FPGA configuration from the ISA bus, (which was the original question) then you need some kind of address decoder hard wired. I agree that you don't need the 245, but you do need a PAL.Article: 12781
Hello, I have problems exporting Foundation 1.4 schematics to VHDL for simulation. I know there is a setting in the file susie.ini that must be added to enable VHDL export: [EXTENSIONS] ExportVHDL=ON But what I get out is not what I expect... Here is the structural VHDL for a FDP macro: -- ACTIVE-CAD-2-VHDL, 2.5.4.97, Thu Oct 29 15:10:24 1998 library IEEE; use IEEE.std_logic_1164.all; entity FDP is port ( C : in STD_LOGIC; D : in STD_LOGIC; PRE : in STD_LOGIC; Q : out STD_LOGIC ); end FDP; architecture STRUCTURE of FDP is --COMPONENTS component FDPE port ( D : in STD_LOGIC; C : in STD_LOGIC; CE : in STD_LOGIC; PRE : in STD_LOGIC; GSR : in STD_LOGIC; Q : out STD_LOGIC ); end component; component VCC port ( VCC : out STD_LOGIC ); end component; --SIGNALS signal X36_NET01056_X95 : STD_LOGIC; begin --COMPONENT INSTANCES X36_1I30 : FDPE port map( D => D, C => C, CE => X36_NET01056_X95, PRE => PRE, GSR => , Q => Q ); X36_1I37 : VCC port map( VCC => X36_NET01056_X95 ); end STRUCTURE First the UNISIM library is not included (ie library unisim;) and secondly the FDPE primitive have a GSR input that is undriven. ( I don't even think this port is in the VHDL model for the FDPE primitive.) So does anyone of you have a solution to this problem? Of course I can edit the code to make it work, but I should not have to do this... Thanks! Jonas ThorArticle: 12782
Don Husby wrote in message <719tea$6or$1@info3.fnal.gov>... >Ray Andraka <no_spam_randraka@ids.net> wrote: >> No need to use the '245 or the PAL in most instances for an ISA bus interface. > >Unless you want to load the FPGA configuration from the ISA bus, >(which was the original question) then you need some kind of address > decoder hard wired. I agree that you don't need the 245, but you do need a PAL. If you believe "Configuring FPGAs Over a Processor Bus" (http://www.xilinx.com/appnotes/bus_conf.pdf), then you might not need a decoder, just a single flip-flop. Excerpt: "The full address map decode may not be necessary during the configuration period. All that is required during the download period is guaranteed exclusive program access to the selected address space for the duration of the download period. On an IBM PC, this is achieved by disabling interrupts and DMA activity for the duration of the configuration period." I've never tried this, it seems problematic, if not impossible, in today's "modern" OS environments. But if it does work, it's a cute hack. Jan GrayArticle: 12783
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ovilup wrote:
> Hi everyone !
>
> I am looking for some EDA tools that are running under Win 95/ Win NT PC's.
>
> The tools should have :
> - VHDL compiler & simulator
> - FPGA synthesis
> - some way to check that what goes out from synthesis is what you
> need
>
> Anyone knows some tools like that please let me know. I heard about
> PeakVHDL,
> but I need some other, for comparison. Price/quality is the issue here.
>
> Thank you, everybody.
>
> ************************************************************
> Ovidiu Lupas
> Design Engineer
> TimTeh Electronics Ltd.
>
> e-mail : ovilup@hotmail.com
> home e-mail : ovilup@mail.dnttm.ro phone : 40-56-121951
> work e-mail : lupas@timteh.dnttm.ro phone/fax : 40-56-198943
> ************************************************************
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Article: 12784You can export your schematic to Aldecs Active VHDL. Go to www.aldec.com to download. Follow the instructions below. 1. If you only want to import a schematic to the VHDL files ( which can be used within Active-VHDL) do the following: - open specified schematic in Schematic Editor in Foundation, - create netlist: choose from menu Options\Create Netlist - import netlist to VHDL : choose from menu Option\Export Netlist - choose specific netlist file (*.alb file) ; 'VHDL' as exported file type ; click OK. Now you can use crated files within Active-VHDL.. 2. You can set the Active-VHDL as default tool for simulation within the Foundation. Then you can simulate your design within Active-VHDL on every stage of the project (functional, after place and route). To do that: - choose from menu: Pile\Preferences\Configuration and check 'Use Active-VHDL Simulation' , then OK. - now if you click on the Simulation or Verification icon in the Project Manager, the Active-VHDL will be open automatically after necessaryArticle: 12785
Smartchip ｼgｹD｡G > I need a tool. > I hope that can transfer Altera(ahdl) to Vhdl or verilog. To use the MAXPLUS II ,under the compiler option and to choose vhdl and verilog output , turn on it, and you can get *.vo ( verilog output ) and * .vho ( VHDL output ) file.Article: 12786
Hi all, I am using xilinx XC4028XL-1-PG299. As I am using XChecker to download the circuit to one single chip, I set the chip to Master Serial mode (ie with M0, M1 and M2 all '0's). To do this, I use a 4.7K ohm resistor to tie each M0, M1, M2 pins to ground as suggested by the databook from Xilinx. The problem is that when I do so, M1 keep on report to me that INIT should be low and my downloading is failed. I also tried to connect all the 3 pins directly to ground and the problem persists. Now, I just make those 3 pins float and I can download successfully to the chip. But I think it is not so secure to do that. Moreover, in M1 there are options to set M0, M1 and M2 to be float, pulldown or pullup. I don't know whether these options will conflict with my downloading circuitry. Thank you very much. Rgds, OliverArticle: 12787
Hi,
my problem is that I am running out of pins on my xilinx 4010 fpga
and I want to
use the mode pin M1 as output and I beleive I should be able to do that
based on
xilinx databook indicating M1 as O (output) after configuration.
I have tried pin LOC but I get error message while mapping in the M1.4
tool.
Does anybody know how I can do that.
Thanks,
Hooman
Article: 12788Leprechaun wrote: > > Hi all, > > I am using xilinx XC4028XL-1-PG299. As I am using XChecker to download the > circuit to one single chip, I set the chip to Master Serial mode (ie with > M0, M1 and M2 all '0's). To do this, I use a 4.7K ohm resistor to tie each > M0, M1, M2 pins to ground as suggested by the databook from Xilinx. > > The problem is that when I do so, M1 keep on report to me that INIT should > be low and my downloading is failed. I also tried to connect all the 3 pins > directly to ground and the problem persists. > > Now, I just make those 3 pins float and I can download successfully to the > chip. But I think it is not so secure to do that. > > Moreover, in M1 there are options to set M0, M1 and M2 to be float, pulldown > or pullup. I don't know whether these options will conflict with my > downloading circuitry. I am taking a chance by writing this without consulting the databook, but I believe you need to use Slave Serial mode when you use the Xchecker cable. If you want to use Master Serial mode on your board, then you have to provide a means of changing the mode when you use the Xchecker cable. I believe that the chip has internal (light) pullups on the mode pins. So disconnecting the pulldowns should be a safe way to select Slave Serial mode. The options you are referring to are for what the chip does AFTER configuration I believe. They are also very light. So they can be easily overdriven by a 4.7K resistor or any type of chip output. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12789
MD0 and MD2 can only be used as inputs, MD1 can only be used as an output. You are trying to use MD1 as an output. Good. None of these desperation inputs or outputs have flipflops. MD1 does have a tri-state capability. It can only be driven with OBUF or OBUFT. You do not need to (probably can not) use a LOC attribute to set the location of this special output. The way to use it is with a special output pad symbol, "MD1" rather than the normal OPAD. Philip Freidin In article <3638BEF2.628AB2E6@mitel.com> Hooman Dadrassan <hooman_dadrassan@mitel.com> writes: >Hi, > > my problem is that I am running out of pins on my xilinx 4010 fpga >and I want to >use the mode pin M1 as output and I beleive I should be able to do that >based on >xilinx databook indicating M1 as O (output) after configuration. >I have tried pin LOC but I get error message while mapping in the M1.4 >tool. >Does anybody know how I can do that. > >Thanks, >Hooman > >Article: 12790
In article <71aemk$7ok@ustsu10.ust.hk> cpegfa@uxmail.ust.hk (Leprechaun) writes: >I am using xilinx XC4028XL-1-PG299. As I am using XChecker to download the >circuit to one single chip, I set the chip to Master Serial mode (ie with >M0, M1 and M2 all '0's). To do this, I use a 4.7K ohm resistor to tie each >M0, M1, M2 pins to ground as suggested by the databook from Xilinx. Whoops. XChecker (or any other external serial config source except for Xilinx's serial PROMs) requires Serial Slave mode (M0, M1, M2 = 1,1,1) >The problem is that when I do so, M1 keep on report to me that INIT should >be low and my downloading is failed. I also tried to connect all the 3 pins >directly to ground and the problem persists. Yep, still in wrong mode. >Now, I just make those 3 pins float and I can download successfully to the >chip. But I think it is not so secure to do that. There is a weak pull up in the chip on each of these pins, that are active prior to configuration. So they are establishing the correct mode for you, 111. I add a 4.7K to vcc for these pins just to be sure. >Moreover, in M1 there are options to set M0, M1 and M2 to be float, pulldown >or pullup. I don't know whether these options will conflict with my >downloading circuitry. The pullup/down you are refering to here is post configuration state. They have no effect on configuration, since the config bits to set this state are not in the chip until configuration has finished. >Thank you very much >Oliver Your welcome. Philip FreidinArticle: 12791
Although not in VHDL, on the ACTEL web site you can find a paper which describes an implementation for the SX family. Hope's any use, Hans. David C. Hoffmeister wrote in message <7129jv$2on@cappuccino.eng.umd.edu>... > > > I am wondering if anyone knows where I might find a synthesizable >VHDL model for an 8B/10B encoder/decoder. I know I saw a post a few months >ago asking a similar question, but I did not see if there were any replies. >Any help would be appreciated. > >-- >David C. Hoffmeister >dch@eng.umd.edu >University of Maryland at College ParkArticle: 12792
Hi. Has anyone used a FPGA to interface to a 3.3V PCI bus without connecting any clamping diodes to the 3.3V rail. I know this is against the PCI spec but since some FPGA's ie.Altera's 6000 devices and Xilinx devices (without compromising 5v I/O tolerance) do not facilitate this. Tx, Jai.Article: 12793
ems@riverside-machines.com.NOSPAM wrote: > > On Wed, 28 Oct 1998 10:30:48 -0800, Tom Burgess > <tom.burgess@hia.nrc.ca> wrote: > > >Those interested in these issues can find some useful info on a > >page run by Howard Johnson (author of "High-speed Digital Design"). > >http://www.sigcon.com/ > > thanks for the link - there's some interesting stuff here. there are > various different articles, but the relevant points seem to be: > > (1) 'bypass capacitor layout' states that, since the inductance is due > to the package and the layout, then you should select a package, do > the layout, and then select the largest practical cap in that > package. in other words, the answer to richard's initial question is - > forget the calculations, stick with 100n caps. Or use smaller caps to get closer to the power pins, with plenty of larger caps sprinkled around for bulk decoupling. Multiple vias, too. Calculations are still needed to get some idea of the total capacitance needed, but they are sensitive to assumptions about the current waveform which is usually unknown during design. <had to snip some> > > i don't understand this. HJ agrees that the SRF is higher for the > lower value parts in a given package, but goes on to say that the ESI > is going to be the same for both parts, since they're in the same > package. can anyone clarify this? > SRF is the frequency at which inductive and capacitive reactances are equal. If I remember correctly, it's something like SRF = 1/(2*Pi*SQRT(C*L)). Lower C or lower L means higher SRF. ESI just depends on L. > i've just checked the vishay data sheets for 0805 and 0603 > ceramics. they dont explicitly show any inductance values, but the > 0805 data sheet clearly shows the expected impedance/frequency plots > for three different cap values, with self-resonant frequencies of > 20MHz, 60MHz, and 200MHz for 100nF, 10nF, and 1nF caps, > respectively. the 0603 datasheet shows the same thing, except the > self-resonant frequencies are *slightly* reduced. in other words, if > the datasheets are to be believed, then the cap's internal > construction has much more to do with the SRF than the package, and > the capacitor value *does* matter. clearly, the trace inductance must > also be controlled, but this is a separate issue (and note that > putting a via in the trace will increase the inductance). > Let's see - by reducing capacitance by a factor of 100, the SRF has gone up by only a factor of 10, as would be expected. Small reduction in package size leads to small reduction in L. > (2) as you point out, the distributed plane capacitance is of the > order of 100pF/square inch. *but*... > (a) a given pwr or gnd pin doesn't get one square inch of > plane. everything else is sharing it. And it gets to share with everything else, taking advantage of all of the bulk capacitors on the board which are keeping the plane charged up, though the closest caps are most important. > > (b) 100pF, or a fraction of it, isn't enough to be of any use at > all. assume a *very* conservative example where the plane has to > provide 50mA, over 5ns, with a 0.2V drop, when a slow output > switches. even this example requires a 1.25nF cap. practical examples > would require considerably more. ok, you've got a cap connected to the > planes, but the charge has to get from the cap, via the planes, to > your pwr/gnd pin. > If you are lucky enough to design for a system with nice slow outputs and smooth current waveforms, then low impedance plane capacitance is less important. > (3) the reason that i put a trace between the cap and the appropriate > pin is not to reduce the noise reaching the plane. it is, very simply, > to ensure that the pin gets exclusive access to the charge on the cap > when it needs it. the cap doesn't have to recharge quickly - it may be > several ns before it's needed again. this may be simplistic - is it? > If both the device and the cap have their own vias to the power planes, then I don't think adding a trace between them will hurt. If they share vias, then I don't know. The via then has to supply the device as the cap loses juice and recharge the cap at the same time. > and finally - via connections. the reason that i suggested one or two > vias, and a localised surface plane, is to isolate the switching noise > at the single via. this procedure hopefully protects the external > system from your 100MHz device, and vice-versa. this gives you an > isolated (more or less) power plane. cypress has a good example in its > hotlink app notes. > There ARE special considerations that come into play when dealing with PLLs and other mixed-signal devices and I would religiously follow the manufacturer's app. notes and sample layouts since they claim that it actually works in this configuration. For generic digital stuff, though, I'm wary of split planes and such as they can make things much worse if used inappropriately. > > evan By the way, I just glanced at the new DigiKey catalog and see that they have some new Panasonic chip caps with large values in small packages - 220 nF/16V in a 603 package sounds nice for X7R tempco. Or 100 nF in a 402. Much larger values in the inferior Y5V tempco, but who needs the headache of 80% capacitance change over temperature. regards, Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 12794
This is a multi-part message in MIME format. --------------E2CCEBA756DDA8120826201A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Steve Casselman wrote: > > > Maybe I'm just paranoid but I always use a 10uF > cap near the point where the power comes on > to the board and then I use a .1uF and a .001uF > cap for each power pin. > > -- > Steve Casselman, President > Virtual Computer Corporation > http://www.vcc.com I'm with Steve on this one. An extra few cents for capacitors are not going to break the budget but a couple of months analysing a noise problem and a respin might. If the board is going in a PC then the power supply will be horrible and you need some big capacitors to smooth out the low frequency stuff. Just watch what happens to the power rail when the mouse gets jiggled and the pentium wakes up out of sleep mode. --------------E2CCEBA756DDA8120826201A Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Tom Kean Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Tom Kean n: Kean;Tom org: Algotronix Ltd. adr: P.O. Box 23116;;;Edinburgh;;EH8 8YB;Scotland email;internet: tom@algotronix.com title: Director tel;work: UK +44 131 556 9242 tel;fax: UK +44 131 556 9247 note: Web Site: www.algotronix.com x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------E2CCEBA756DDA8120826201A--Article: 12795
Don Husby wrote: > Ray Andraka <no_spam_randraka@ids.net> wrote: > > No need to use the '245 or the PAL in most instances for an ISA bus interface. > > Unless you want to load the FPGA configuration from the ISA bus, > (which was the original question) then you need some kind of address > decoder hard wired. I agree that you don't need the 245, but you do need a PAL. Agreed. I didn't realize he was looking to do the configuration over the ISA bus too. One PAL will take care of that. Even in that case, I would bring the ISA address lines directly to the FPGA and do the post configuration decode right in the FPGA. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12796
You can't LOC the M0,1,2 pins. Instead use the special m0,m1,m2 symbols. Mapping will fail if you try to use regular ibufs or obufs. Be aware that only M1 is an output, that there are no IOB flipflops on these pins, and that timing constraints don't work for these pins. The timing constraints thing means you had better be careful how you use these pins if it is a speed critical part of the circuit. Hooman Dadrassan wrote: > Hi, > > my problem is that I am running out of pins on my xilinx 4010 fpga > and I want to > use the mode pin M1 as output and I beleive I should be able to do that > based on > xilinx databook indicating M1 as O (output) after configuration. > I have tried pin LOC but I get error message while mapping in the M1.4 > tool. > Does anybody know how I can do that. > > Thanks, > Hooman -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12797
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Hi, Does anyone know the web where I can buy I/C components on line outside of USA ? Thanks. TimArticle: 12799
Yves Vandervennet wrote:
> does anybody know how to digitally realize a sine generator
> other than sampling a sine period and storing it in a ROM ?
> We have to integrate it in an FPGA. If anybody knows book references
> on this subject, we would be happy for a very long time.
Remember the sine is the solution of a simple differential
equation. Turn the differential equation into a difference
equation and you get
x2 = (2 - (2*pi*fsin/fsam) ** 2) x1 - x0
An example for 440 Hz with a sample rate of 44100 HZ:
pi = 3.1415926535
fsin = 440
fsam = 44100
x0 = 0
x1 = 1
OmegaSquare = (2*pi*fsin/fsam)**2
a = (2 - OmegaSquare)
for (i=1; i<= 1000; i++) {
x2 = a * x1 - x0
print x2
x0 = x1
x1 = x2
}
Looks like 1 MUL and 1 SUB per cycle.
But its just an approximation.
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