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--------------E91D5AABA5EBA017FFF61153 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Alexander Sherstuk wrote: > I am considering using FPGA for 1ns-accurate > measurements. > As well as I understand, it is hardly possible to feed > 1GHz clock frequency into FPGA. > My questions are: > > 1. Has anybody used some kind of frequency prescaler in > connection with FPGA? > Well almost. I have built a year ago and have demonstrated at various shows a working 420-MHz frequency counter ( using XC4002XL-09 ) that has an asynchronously counting front end ( of course inside the chip ). We may be able to stretch that to 500 MHz in a newer flavor. That would mean 2 ns resolution, half of what you want. The limit is getting the clock onto the chip and make one flip-flop toggle. After that it's just halfway clever logic design. > 1. What prescalers are suitable for such purpose? > Does anybody know VHF counters with internal > stages accessible (which is necessary to obtain > lowest bits of the counter)? > I do not know of a readable ECL prescaler, although one could imagine elaborate read-back schemes. There are obviously 2 GHz dumb or pulse-swallowing prescalers, otherwise the cellular phones wouldn't work. > > 1. Is it possible for XILINX Virtex to generate 1 GHz > internally, through it's on-chip PLL? > No. The DLL operates to max 200 MHz, but it has 35 ps resolution. > 1. > 2. Is Altera's on-chip PLL capable of such frequencies? > I really don't know, but I doubt it very much. :-) Peter Alfke, Xilinx Applications > 1. > > Thanks, > Alex Sherstuk > sherstuk@amsd.com > AMSD Company > --------------E91D5AABA5EBA017FFF61153 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <HTML> <BODY BGCOLOR="#FFFFFF"> <P>Alexander Sherstuk wrote: <BLOCKQUOTE TYPE=CITE> <FONT FACE="Arial"><FONT SIZE=-1> I am considering using FPGA for 1ns-accurate measurements.</FONT></FONT> <BR><FONT FACE="Arial"><FONT SIZE=-1>As well as I understand, it is hardly possible to feed 1GHz clock frequency into FPGA.</FONT></FONT> <BR><FONT FACE="Arial"><FONT SIZE=-1>My questions are:</FONT></FONT> <OL TYPE=1> <LI> <FONT FACE="Arial"><FONT SIZE=-1>Has anybody used some kind of frequency prescaler in connection with FPGA?</FONT></FONT></LI> </OL> </BLOCKQUOTE> Well almost. I have built a year ago and have demonstrated at various shows a working 420-MHz frequency counter ( using XC4002XL-09 ) that has an asynchronously counting front end ( of course inside the chip ). We may be able to stretch that to 500 MHz in a newer flavor. That would mean 2 ns resolution, half of what you want. The limit is getting the clock onto the chip and make one flip-flop toggle. After that it's just halfway clever logic design. <BLOCKQUOTE TYPE=CITE> <OL TYPE=1> <LI> <FONT FACE="Arial"><FONT SIZE=-1></FONT></FONT></LI> <UL><FONT FACE="Arial"><FONT SIZE=-1>What prescalers are suitable for such purpose? Does anybody know VHF counters with internal stages accessible (which is necessary to obtain lowest bits of the counter)?</FONT></FONT></UL> </OL> </BLOCKQUOTE> I do not know of a readable ECL prescaler, although one could imagine elaborate read-back schemes. There are obviously 2 GHz dumb or pulse-swallowing prescalers, otherwise the cellular phones wouldn't work. <BLOCKQUOTE TYPE=CITE> <OL TYPE=1> <UL><FONT FACE="Arial"><FONT SIZE=-1></FONT></FONT> </UL> <LI> <FONT FACE="Arial"><FONT SIZE=-1>Is it possible for XILINX Virtex to generate 1 GHz internally, through it's on-chip PLL?</FONT></FONT></LI> </OL> </BLOCKQUOTE> No. The DLL operates to max 200 MHz, but it has 35 ps resolution. <BLOCKQUOTE TYPE=CITE> <OL TYPE=1> <LI> <FONT FACE="Arial"><FONT SIZE=-1></FONT></FONT></LI> <LI> <FONT FACE="Arial"><FONT SIZE=-1>Is Altera's on-chip PLL capable of such frequencies?</FONT></FONT></LI> </OL> </BLOCKQUOTE> I really don't know, but I doubt it very much. :-) <P>Peter Alfke, Xilinx Applications <BLOCKQUOTE TYPE=CITE> <OL TYPE=1> <LI> <FONT FACE="Arial"><FONT SIZE=-1></FONT></FONT></LI> </OL> <FONT FACE="Arial"><FONT SIZE=-1>Thanks,</FONT></FONT> <BR><FONT FACE="Arial"><FONT SIZE=-1> Alex Sherstuk</FONT></FONT> <BR><FONT FACE="Arial"><FONT SIZE=-1> </FONT></FONT> <U><FONT FACE="Arial"><FONT COLOR="#0000FF"><FONT SIZE=-1><A HREF="mailto:Sherstuk@amsd.com">sherstuk@amsd.com</A></FONT></FONT></FONT></U> <BR><FONT FACE="Arial"><FONT SIZE=-1> AMSD Company</FONT></FONT> <BR> </BLOCKQUOTE> </BODY> </HTML> --------------E91D5AABA5EBA017FFF61153--Article: 14251
What you are talking is right for the original xilinx viewdraw/lca and
viewsim (edition 4) and xact dongle.
Here is one schemat of the dongel. This has been on the internet for
some time. There were 2 types of this circuit depending on if Viewsim
was enabled.
The dongel for later versions is very complicated. There is a software
crack for xact6 which was posted in this newsgroupp some time ago.
section 1 of uuencode 5.22 of file lock.zip by R.E.M.
begin 644 lock.zip
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Article: 14252I was going to suggest you talk to Peter Alfke, since I knew he did one that ran at about a half GHz in a 4000 series FPGA...everything was inside the FPGA in that case. I don't think you'll get a clock into the current FPGAs at 1 GHz, with the possible exception of a Dynachip part. I gather from the text in your post that you are looking to measure a time interval to a 1 ns resolution rather than doing a frequency counter. If that is the case, you don't necessarily need to get a 1 GHz signal into the chip, since what you really want is fine resolution of the arrival time. Now, I haven't played with the DLL in the virtex yet but as I understand it it has a delay resolution of something less than 50 pS, and it can be used to generate multiphase clocks locked to some reference. My thought is this: Use the DLL to generate a multi-phase clock at a convenient frequency. Run the input to multiple flip-flops, each clocked by a different clock phase. This will allow you to bin the arrival time in sub-clock increments. Of course, you will need to hand route that portion of the design (you wanted to learn the epic editor anyway, right?) to match the delays for the clocks and input data to each register. Once the data is binned, you need to use the different clock phases to gently bring all the flip-flop outputs to a common phase without violating set-up and hold times. After that, it is a simple matter to encode the fine arrival time and count off the coarse arrival time. I designed a high speed logic analyzer back around 1980 using a similar technique. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 14253
Bruce Nepple wrote: > OF course, schematics are of no use at all in the design of complex state > machines. And, I'd hate to have to draw schematics to determine whether to > use 1-hot or binary coded for size and/or speed in a particular application. > It is extremely easy to whip out implementation experiments with an HDL. In vast majority of cases for FPGAs, if you have more than 4 states, you are better off with a one-hot or shift register type state machine than a binary encoded one (in terms of speed, and sometimes area too). There is a grey area between 4 and 16 states, but I have found the differences in speed in that region to be slight, so I favor the one hot for ease of entry and legibility. That being the case, I use a methodology that puts one-hot components in symbol wrappers that make the schematic look like a flow diagram. That makes it very easy to construct fairly complex state machines quickly in schematic form, enough so that I don't have to deal with a mixed entry. So in that regard, I have to disagree with your first statement. I've already made the decision as to the state machine style by the time I am laying down the design based on the state machine size. Yes it is very easy to do a state machine in text based entry, as is describing decoders (both of which I mentioned previously). My point here is that you can do state machines quickly, accurately, and legibly in schematics too. Bruce Nepple wrote: > OF course, schematics are of no use at all in the design of complex state > machines. And, I'd hate to have to draw schematics to determine whether to > use 1-hot or binary coded for size and/or speed in a particular application. > It is extremely easy to whip out implementation experiments with an HDL. > > My rule of thumb is that any design above about 5K gates will get to market > faster with an hdl (assuming a working design flow than you understand). > As far as speed to market, it really depends on the design. For a high performance DSP dataflow type design, I can turn out a completed design under schematics more rapidly than I can under an HDL. (between june 97 and june 98 I completed 33 FPGA designs, most of which were in fairly full (most would not have fit in the next smaller device) 4028 or larger devices, all of which were clocked at 40 MHz or faster with a few over 100 MHz, and all but one of which were entered as schematics) There are several factors contributing to this: first, these designs invariably need an explicit low level implementation and placement to make them perform. My schematic libraries already contain the low level constructs (1 & 2 bit slices of just about any arithmetic function) with the placement stuff already embedded. Building an oddball thingy like a 5 bit adder that has 7 counter bits above it of which 3 bits can be independently loaded only takes me a couple of minutes to pop down the 2 bit blocks, connect the carries together and change the RLOCs on the 2 bit symbols. Many of the more common widths are already in the library from previous projects. The fairly painful low level work in HDLs slow me down enough that in these cases the schematic entry is quicker. My point, I guess is that schematics don't have to be as painful to do as many people have experienced. > And, what about multiple designers working together on 1 design. Schematics > can get real messy (just getting the interface names correct is a pain). > This is a function of hierarchy, not of schematic vs. text. If you follow hierarchy in a schematic design the way I suggested in my previous post, the signal names are local so it doesn't matter if you name them after your boss's nasty habits (as long as he doesn't find out). At the hierarchy boundaries, the signals get aliased with the net name on the upper level...same as with the HDLs. The nice thing about text entry is the hierarchy is forced upon you, while with schematics you are left to do (or not do) it. Unfortunately, that seems to give the average engineer license to make a schematic nightmare (he needs a good manager to enforce hierarchy). > Also, Schematics are much more difficult to modify and maintain as the > project moves forward and inevitably changes. > I disgree with the difficulty in modifying it. It is easier in a schematic to see what it is you are modifying and to verify that it won't screw up something else...especially after you've been away from the design long enough to forget how it works. Text is easier to do revision control on because the software in that area has kept up better with text. Also the text is easier to archive for the reasons I cited in my previous post. A good library helps, but is not essential. I've built my library over a considerable period of time, and now it serves me well in terms of reuse. > The art of drawing a good schematic is *much* more time consuming than > cranking out well commented hdl. > OK, again depends on the design and the person doing it but I'll give you this one. > But, my favorite aspect of hdl's is the "print on error only" test bench. > As I stated in my previous post, one of the most compelling reasons to use an HDL is the superior simulation capability. That abilility includes the ability to behaviorally define a block so that it can be simulated before the detail design is done, and to accelerate simulation of previously verified blocks; it also gives the ability to construct very complicated test benches including ones that report on error only. THis is such an advantage that I have used VHDL test benches under a schematic symbol to exercise designs captured in schematics.As I more or less stated last night, for the average FPGA user the choice between an HDL and schematic entry is as much a style issue as anything else. However, for high performance designs, the advantages in implementing low levels of the design in schematics outweighs the clear advantages in simulation and archiving and the design dependent other 'advantages' of text based entry for the types of designs I am mostly involved in. > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 14254
For a textbook that covers hardware arithmetic algorithms, try Israel Koren's "Computer Arithmetic Algorithms." The theoretical coverage is good, but there isn't very much in terms of specific hardware technologies that implement the algorithms. I have found that there is no book that covers both theory and practice really well, as almost all researchers specialize in either area and not both.Article: 14255
This is a multi-part message in MIME format. --------------C7EFDA4E7E41D32683E171E2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Khaled benkrid wrote: > Hi All! > > I am using FPGA express 1.2 (comes with Foundation 1.3 Student edition). > > I have the following warning when optimizing my designs: > " Port XX has no net attached to it-no pad cell inserted in this port > FE-PADMAP-2". These ports are inputs in my design, so it is a problem > for me. I want to know how to work around this. > > Thanks. Hi, Khaled, If you're using the schematic tool, you have to verify if you are using the right symbol, there exist, Input, Output, Ipad, Opad and IOpad, you have to use Ipad, Opad or IOpad for Inputs and Outputs, and some times you have to put a buffer between Ipad or Opad and the rest of your internal design. If you are using a HDL description, maybe is a problem with your license or with the library. I'm using the Foundation 1.5 (the last version) and I still have problems. I hope this will be usefull for you. Andres David --------------C7EFDA4E7E41D32683E171E2 Content-Type: text/x-vcard; charset=us-ascii; name="garcia.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Andres Garcia Content-Disposition: attachment; filename="garcia.vcf" begin:vcard n:Andres David;GARCIA GARCIA tel;pager:http://www-elec.enst.fr/~garcia/index.html tel;fax:(33-1)45-80-40-36 tel;home:(33-1)40-78-68-32 tel;work:(33-1)45-81-78-03 x-mozilla-html:FALSE org:E.N.S.T.;Communications and Electronics Department version:2.1 email;internet:garcia@elec.enst.fr title:PhD Student adr;quoted-printable:;;46, Rue Barrault=0D=0A75634, Paris 13 Cedex.=0D=0AFrance.;;;; fn:Garcia G. Andres D. end:vcard --------------C7EFDA4E7E41D32683E171E2--Article: 14256
Hamish Moffatt <hamish@rising.com.au> writes:
> So is there ANY way to do free FPGA work yet? Like little projects
> for home?
Atmel sends you their IDS6.0 software after you've registered at
http://www.atmel.com/atmel/fpga_software.html
Without front-end tools you can "only" do VHDL/Verilog synthesis.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 14257
In article <36A7E2EB.3D0E7544@ids.net>,
Ray Andraka <randraka@ids.net> wrote:
(Hi Ray, I've lurked comp.dsp for a while, it just
seemed like a tricky place to post! I put this together last
night, but my newserver is crippled, seems to miss over
half the posts in any thread, and usually won't let me
post out. So this goes out via DejaNews, it was written
before I saw your post)
Marius Vollmer wrote:
<cut some>
With textual languages, you can specify the grammar and formal rules
for what each construct means, for example. They allow for much more
powerful abstraction mechanisms, because they do not pretend to be
intuitive to begin with. With schematic layout things, I think we
still haven't a really good separation between the `format' and the
tool used to edit it, like we have for text languages. And the tools
for working with text are just plain better and more mature than the
ones for graphical descriptions.
Text is very simple, 1-D stuff. Right to left, top to bottom.
I don't recall ever seeing BNF for a schematic
design system.
I do not think the old saying "a picture is worth a thousand words"
can really be used as an argument here. The other way around is just
as true: "a word is worth a thousand pictures". We should and can
have both.
I'm biased, I work mostly with video/imaging, :o), but I admit it
can work the other way.
Schematic tools produce static, declarative descriptions, AFAICS,
while textual languages allow for a more active, procedural
descriptions. Take the GENERATE statement in VHDL. How many
schematic capture tools support such a thing? Would it be useful? I
think yes. [Note, I know next to nothing about the current state of
the art in schematic capture, so these are actually not rhetoric
questions.]
It certainly could be done, I don't know whether it has or not.
( someone out there pipe up if you know )
A GENERATE attribute that could be attached to a symbol,
coupled with adequately expressive conditionals that could
be used in the schematic represented by that symbol
would be great stuff.
There are schematic environments that permit heirarchical
inheritance of attributes, but I haven't seen one that will
produce multple instances of a symbol's underlying sheet, with
different values of some attributes attached to each sheet.
A graphical "conditional overlay sheet" would be neat.
( Picture a box, with attached conditional expression,
surrounding the circuitry to be implemented when the
condition is met. ) We could easily create our own module
generators, and not be limited by fixed ones provided
by vendors.
What is really needed is a way to combine the best of both worlds, as
always. Allow the intuitive design of structural relationships via
graphical nets, just like you would use them on a white board when
reasoning about them with your colleagues. Allow for more abstract
notions like parameterized repetition of subnets, conditionals, and
support for `higher order schematics'. Allow for the seamless
integration of things that are better described textually, like actual
pieces of software that runs on your hardware or high-level
algorithmic signal munching.
Well said!
Insofar as schematic descriptions are `inferior' to textual ones, you
can certainly convert your schematic into the textual form and then
simulate and synthesize that. What's more important, IMO, are the
thoughts you can't think
as unthinkable as the words you can't say and the text you can't write
(Sorry, it just seemed an odd phrase, and it's late as I write this)
and teh things you can't say in your
schematic.
- Marius
Fundamentally, I feel that a 2-D schematic is a better
design medium for circuits that are ultimately implemented
in 2-D silicon. (Evan) Yes, text based design offers great
things too. I also think I am just growing tired of re-learning
all the idiosyncracies ( not to mention bugs! ) of each
new design tool that comes along. (It takes away from time
spent designing!)
That goes not only for graphical tools,
but the text based ones as well. I used to have to fiddle
with C programs to see what particular phrasing of a
statement would produce the fastest running obj code. It was a
pain to have to go through that exercise, when knowledge
of the processor/cache system would make it almost obvious
(to the human) what needed to be happening at the lower
levels. The same effort is required for the state machine
compilers I've worked with, be they graphical or HDL based.
They don't produce really optimized low level results,
which in FPGA land can result in performance hits of
2x or more.
- John
( I promise not to write on this topic again for another
year, after I've done considerably more HDL (I'm probably
going to have to, corporate policy). No more
posting except for good technical questions or
suggestions, really!)
-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14258Hi guys, it is possible to implement a DTMF Decoder in a FPGA/Xilinx ? Input signal would be a digital E1/T1 signal, generated by a E1/T1 Framer (CLK, DATA) comments please here or to mb@cellware.de Thanx MichaelArticle: 14259
I haven't seen any commercial packages yet that will do a generate for schematics. I do it manually right now, mostly because I've been too lazy to write a tool, and partly because I know that Philip Freiden has already written a schematic generator (which I would like to get my hands on). So yes it can be done. Maybe now that viewlogic has been divorced from synopsis we will see some of the obvious things for schematics addressed: things like automatic bus widths, parameterized generation, etc. that would make the things that make schematic entry slow go away. tronsmith@my-dejanews.com wrote: > Schematic tools produce static, declarative descriptions, AFAICS, > while textual languages allow for a more active, procedural > descriptions. Take the GENERATE statement in VHDL. How many > schematic capture tools support such a thing? Would it be useful? I > think yes. [Note, I know next to nothing about the current state of > the art in schematic capture, so these are actually not rhetoric > questions.] > > It certainly could be done, I don't know whether it has or not. > ( someone out there pipe up if you know ) > A GENERATE attribute that could be attached to a symbol, > coupled with adequately expressive conditionals that could > be used in the schematic represented by that symbol > would be great stuff. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 14260
>From info Fri Jan 22 19:30:48 MSK 1999 Need any help/information for realisation my next project -Decoder Viterbi in FPGA . Thanks. AlexArticle: 14261
Hi All! I am using FPGA express 1.2 (comes with Foundation 1.3 Student edition). I have the following warning when optimizing my designs: " Port XX has no net attached to it-no pad cell inserted in this port FE-PADMAP-2". These ports are inputs in my design, so it is a problem for me. I want to know how to work around this. Thanks.Article: 14262
There is a text - Jean-Michel Muller Elementary Functions, Algorithms and Implementation http://www.birkhauser.com/cgi-win/ISBN/0-8176-3990-X I have not yet read it myself so I can't comment if it is good or not, but there is a chapter on CORDIC / Jonas Thor >I did a quick net search, and turned up a few papers by Ray Andraka, >that give a very good introduction. As such, I would like a few of the >CORDIC experts out there to recommend a good reference text on CORDIC >specifically, and distributed math, or atleast a hardware oriented >algorithm book more generally.Article: 14263
jspeter@twinkle.roanoke.infi.net wrote: > Coincidentally, this is my research topic as well. Here are some notes I've > gathered on other attempts: Thanks for the list. Really interesting. > So far as I know, none of these can take full ANSI-C code. My research > attempts to support full ANSI-C by running the input through the freely > available retargettable compiler, LCC. I then just use the output from LCC > as the input to the core compiler. Letting lcc do the ANSI-C stuff and produce a P-code-like symbolic code is a good idea. But why assemble the symbolic code into XNF rather than into VHDL, VERILOG or ABEL ? Sorry if this is a stupid question, I am not a hardware designer by profession. > > --Jim > (http://www.cs.princeton.edu/software/lcc/) > (http://www.ee.vt.edu/~ccm/) I could not find any papers on your web site concerning your thesis. Could you give me another pointer ? ________________________________________________________________________ Juergen Kahrs Tel. 0421 249 666 Millstaetter Strasse 15 Tel. 0421 457 2819 D 28359 Bremen Fax 0421 457 3578 ____________ http://home.t-online.de/home/Juergen.Kahrs/ _______________Article: 14264
If you have a secured device, such as a GAL, PAL, microcontroller, and FPGA, with the contents of which you are interested in recovering and providing the contents are not copyrighted (or you are the copyright holder), we may be able to help you. We also have reader/analyzer for reading/analyzing various secured GAL's and PAL's. Please reply via e-mail or call: +1-404-228-1643 for further details.Article: 14265
Get on the Xilinx website and look for the conference paper by Greg Goslin. He had a viterbi decoder he presented at DesignCon a few years ago. You might also look for the DSP presentation by Bruce Newgard, I think he had a slide or two there on a viterbi decoder. For general info on a viterbi decoder look at Digital Communication by Lee & Messerschmitt. Wircom wrote: > >From info Fri Jan 22 19:30:48 MSK 1999 > > Need any help/information for realisation > my next project -Decoder Viterbi in FPGA . > Thanks. > > Alex -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 14266
Utku Ozcan wrote: > > Please forgive me the terms in this e-mail, since I am using > "synthesis" and "compilation" interchangeably. > > > I used synplicity on a Xilinx 40150. The versions I used were: > > 5.0.6, 5.0.7 and 5.0.8. Before getting to know synplicity, I > > used Synopsys's FPGA Compilor on a Xilinx 4036. All works were > > done on SUN workstations. Here is a summary of problems that > > I have seen: ...snip... > We have used 3.0c, 5.0.7 and 5.0.8 version of Synplify. I must say > that the compilation speed is very fast. Our target technology > was XC40110XV. FPGA Express compiled the chip in 1.5 hours whilst > Synplify 5.0.7 compiled in 4 minutes and 5.0.8 in 2 minutes!! > It is a promising time to make Tcl-base algorithmic iterations. I am very interested in this discussion since I have become rather dissatisfied with the Xilinx version of Synario's FPGA Express. I would like to learn more about the various compilers available and their strengths or faults. There was a lot of good information in several of these posts, but I have not been able to tell what software is being talked about. Is synplicity and synplify the same product? Who is the vendor and which is the product? I can tell that you are running on the Sun workstation, but is this a package that is supplied by Xilinx, or are you using the Alliance software with the vendor's front end. When Synopsys's FPGA Compiler is mentioned, which is this? Is this the FPGA Express package from Synopsys (ver 2.1.3), supplied via Xilinx in the Foundation Express package? Or is this a version direct from Synopsys? About your comment on CLB usage, I see what you are talking about. I guess this is a difference between the view of the back end tools which know about the routing vs. the front end tool which know nothing about the routing. But I have noticed that the Xilinx Foundation Express will add logic to the CE of a FF as well as the D input when you have if statements inside the clocked region of a process. This often requires twice the number of LUTs for a given function vs. putting all the logic in the path to the D input. My CLB usage went up about 10% when I converted from the Metamor compiler (M1.4) to the FPGA Express compiler (M1.5). Once I corrected the code for the worst offenders (large registers and big FSMs) the difference dropped to about 5%. Thanks, -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14267
You might be suprized who reads this group. I'd bet they are listening. I just don't know what their priorities are. Andy Peters wrote: > > Rickman wrote in message <36A6BF07.BCAE24B0@yahoo.com>... > >Synopsys, are you listening??? > > > >VHDL-93 NOW! > > Aww, Rick, they're not listening. Bastids. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14268
Peter Alfke wrote: > > Alexander Sherstuk wrote: > > > I am considering using FPGA for 1ns-accurate measurements. > > As well as I understand, it is hardly possible to feed 1GHz clock > > frequency into FPGA. > > My questions are: > > > > 1. Has anybody used some kind of frequency prescaler in connection > > with FPGA? > > > Well almost. I have built a year ago and have demonstrated at various > shows a working 420-MHz frequency counter ( using XC4002XL-09 ) that > has an asynchronously counting front end ( of course inside the chip > ). We may be able to stretch that to 500 MHz in a newer flavor. That > would mean 2 ns resolution, half of what you want. The limit is > getting the clock onto the chip and make one flip-flop toggle. After > that it's just halfway clever logic design. > > > 1. What prescalers are suitable for such purpose? Does > > anybody know VHF counters with internal stages accessible > > (which is necessary to obtain lowest bits of the counter)? > > > I do not know of a readable ECL prescaler, although one could imagine > elaborate read-back schemes. There are obviously 2 GHz dumb or > pulse-swallowing prescalers, otherwise the cellular phones wouldn't > work. > <snipped> How about using a MC100LVEL29 dual D-FF (1.1 GHz, 3.3V) as a readable divide by 4 prescaler (to bring the FPGA toggle rate down to 250 MHz) and a SY100ELT23L (diff. PECL to TTL, 3.3V) to bring both bits into the FPGA. The reset input of the first D-FF could be used for clock gating. Remaining problems include finding a reasonable GHz clock source and interfacing to the signal to be measured. For higher clock rates, the MC100LVEL32 (3 GHz divide by 2, 3.3V) might be of interest. Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 14269
Bruce Nepple wrote: > > OF course, schematics are of no use at all in the design of complex state > machines. And, I'd hate to have to draw schematics to determine whether to > use 1-hot or binary coded for size and/or speed in a particular application. > It is extremely easy to whip out implementation experiments with an HDL. > > My rule of thumb is that any design above about 5K gates will get to market > faster with an hdl (assuming a working design flow than you understand). > > And, what about multiple designers working together on 1 design. Schematics > can get real messy (just getting the interface names correct is a pain). > > Also, Schematics are much more difficult to modify and maintain as the > project moves forward and inevitably changes. > > The art of drawing a good schematic is *much* more time consuming than > cranking out well commented hdl. > > But, my favorite aspect of hdl's is the "print on error only" test bench. > > bruce I hate these type of long winded, verbose argument threads that are just one notch above "How many angels can dance on the head of a pin?" discussions. With that said, let me add my 2 cents worth of clutter to this thread. ;^) I would take exception to the statement that schematics are "no use at all in the design of complex state machines". If you are designing a one hot CFSM (complex finite state machine) or just FSM, you can make the schematic a state machine diagram very simply. Each FF in a one hot FSM corresponds to the state it represents. The logic associated with each state trasistion can be drawn as a block or "macro" on the drawing with the "from" state as an input along with the enabling inputs and the "next" state as the output. The state block only needs an N wide or gate and the FF. This will look like a crude, but descriptive state diagram complete with state transitions and output logic. You can add text to any block to describe the logic inside and provide as much documentation as any text form. I am near the end of my first significant VHDL based project and I have learned a lot about the limitations of VHDL design. I am much more comfortable with a language based design process, but I now realize that the VHDL compilers I have used are analogous to the C compilers from the 80's. These compilers include Orcad Express, Metamor and FPGA Express. They are rather buggy, with frequent crashes and errors reported when there should be none. They also produce very poor logic unless you spend a lot of time learning about the specifics of each compiler and adjust your code to match its undocumented requirements. All in all, if you need to optimize your design either in size or in speed, VHDL will be hard to work with and consume a lot of time. On the other hand, I am glad that I have learned how to do basic design in this language and plan to use it again in the future. But now I know to pick my projects and my tools. BTW, another point I would like to make is that you can still simulate a schematic under a VHDL test bench. I have been told (haven't had the time to test it myself) that Active VHDL will translate the schematic netlist into VHDL structual code to be run under their VHDL simulator. Not to be picking on Bruce, but I don't see the clear distinctions that he does in the advantages of VHDL in terms of developing and maintaining module interfaces, coordinating multiple designers, and the clarity of design. I don't find it any more difficult to change an interface in a GUI schematic than I find it hard to keep multiple VHDL modules coordinated. My current design is schematic top level and VHDL at the bottom (in most cases). Changing and interface is a coordination issue rather than a GUI vs test issue. The Foundation tools will update the symbol on the schematic whenever you change the pins on the lower level and vice versa. Clairity of design is a designer issue rather than a tool issue. I have seen bad code and I have seen bad schematics. Many of them have been mine and were the result of too many changes during the design and debug process. This was usually a result of not understanding the design well enough when I started putting it on paper (or electrons). This problem can be mitigated by leaving lots of white space on a schematic or in a VHDL design by allowing time for restructuring of the design part way through. Was that enough? Does any of this matter? But there it is! Can I have my 2 cents now? Sometimes I work pretty cheaply. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14270
This is a multi-part message in MIME format. --------------FF8F144E72D1DACAC6874292 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit hello all.. thanks for the pointer .... in fact the Product of the Week changes each week.... dhaaa on my part.... new link is (and i don't know for how long ;)) http://www.edtn.com/pld/pldp208.htm a word on 'the catch'...... The HOT2 Interface Netlist contains the LogiCORE PCI Interface... to obtain the HOT2 Netlist you must sign a special license from Xilinx Inc., which only allows use of the Xilinx Interface on the HOT2 Board... once you have 'Validated' your project and intend to go into production, you must pay another license fee to Xilinx. -- Best Regards, John Schewel, VP Marketing & Sales Virtual Computer Corp. http://www.vcc.com --------------FF8F144E72D1DACAC6874292 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John Schewel Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John Schewel n: Schewel;John org: Virtual Computer Corporation adr: 6925 Canby Ave. #103;;;Reseda;CA;91335;USA email;internet: jas@vcc.com title: VP Marketing & Sales tel;work: +1 (818) 342-8294 tel;fax: +1 (818) 342-0240 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------FF8F144E72D1DACAC6874292--Article: 14271
This is a multi-part message in MIME format. --------------31CE230D596BA772E1AA172A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit may i suggest these pointers http://www.edtn.com/pld/pldp208.htm http://www.vcc.com -- Best Regards, John Schewel, VP Marketing & Sales Virtual Computer Corp. http://www.vcc.com --------------31CE230D596BA772E1AA172A Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John Schewel Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John Schewel n: Schewel;John org: Virtual Computer Corporation adr: 6925 Canby Ave. #103;;;Reseda;CA;91335;USA email;internet: jas@vcc.com title: VP Marketing & Sales tel;work: +1 (818) 342-8294 tel;fax: +1 (818) 342-0240 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------31CE230D596BA772E1AA172A--Article: 14272
Ray Andraka wrote: > how it works. Text is easier to do revision control on because the software in > that area has kept up better with text. Also the text is easier to archive for > the reasons I cited in my previous post. A good library helps, but is not > essential. I've built my library over a considerable period of time, and now it > serves me well in terms of reuse. This is an issue I have with the Xilinx Foundation schematic tools. When I used Viewlogic, they stored their files in text format. They can be archived and revision controlled the same as software source files complete with space savings by compaction. However, the Foundation tool outputs binary files which can not be properly interpreted by most version control tools and take up large amounts of space. But even then large is relative. I doubt if the source files of any design that I have ever done would take much space on my 4 GB drive. Even with all of the backend versions with several multi megabyte intermediate files per version, my current design fits easily on a 100 MB zip disk. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 14273
I am a high-school student in the 10th grade interested in synthesizing
designs for the Xilinx XC4000 series of FPGAs using VHDL. However, I am
having trouble obtaining a low-cost VHDL/Verilog synthesis tool. I am
currently using the ABEL language supported by Foundation Version 3.1
student edition. The Xilinx web-page states that I need to obtain the
Foundation V1.4 cd's to upgrade V1.3 so that I can design with VHDL.
Does anyone know how to obtain these CD's from Xilinx? Or alternatively,
are there any free or open-source VHDL synthesis tools available?
Thanks in advance,
-EKC
I think it's a shame that Xilinx and Altera are charging such hefty sums
for their software. It seems that the distinguishing factor between FPGA's
from different vendors is the quality and ease-of-use of the design
software, especially as the gate numbers stretch into the millions. By
decreasing or eliminating the price-barrier, FPGA vendors with superior
design software would increase the rate of diffusion of their software into
the market-place, and consequently promote their FPGA's. Such a lowering of
the price-barrier would pose a serious threat to companies that offer only
synthesis tools, which generally target FPGA's from different companies.
This would lock clients into FPGAs from a single vendor.
Article: 14274ems@riverside-machines.com.NOSPAM wrote: > > I don't want to get into an argument here, but it's time that someone > actually explained why people use VHDL. There are a lot of people in > this newsgroup (.fpga) who will defend the use of schematics, but few > who will bother to argue the case for VHDL. > > There are only two significant reasons to make the large investment > required to convert to the xHDL flow: simulation, and synthesis. Evan, I think you made some excellent points. But don't you think you missed one major reason why VHDL is used? Intellectual Property. In the software world, it's the same idea as code re-use. You've got functional block that can be dropped into many different systems that have many different types of hardware targets (ASIC, FPGA, etc.). -- % Randy Yates % "The dreamer, the unwoken fool - %% DIGITAL SOUND LABS % in dreams, no pain will kiss the brow..." %%% Digital Audio Sig. Proc. % %%%% <yates@ieee.org> % 'Eldorado Overture', *Eldorado*, ELO http://www.shadow.net/~yates
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