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At the risk of pushing CORDIC one too many times, A Cordic rotator set up as a linear machine will perform integer division. The result is a quotient and a remainder. An n-bit result takes n iterations. For more details, refer to my CORDIC survey paper. The paper is available on my website. Mike Albaugh wrote: > I'm just an amateur here myself, so take this "cum granum salis", > but...: > > Lorenzo Di Gregorio (lorenzo.digregorio@hl.siemens.de) wrote: > : Paul S Secinaro wrote: > > : > Hi all, > : > > : > Can anyone point me to some good references on implementing arithmetic > : > functions in high-speed digital logic? I'm especially interested in > : > integer divide algorithms > > : Look for "Division and Square Root" by Ercegovac and Lang (Kluwer). Most of > : the literature about division is for floating point. Probably the only > : "practical-real-world-safe-bet" solution is the standard "digit recurrence" > : non-restoring algorithm, implemented with a signed-digit quotient (saves one > : sum in radix-2). If you have area (two multipliers) and need low latency maybe > : an iterative division with rounding (gosh !) can be implemented. An option is > : to convert the data to fp and use a floating pointer divider which provides > : unnormailzed data (integer). > > If he is actually looking to build the thing, "convert to F.P. and > use the F.P. divider" is at best a diversion. The only time advantage > an F.P. divide has over an integer one (of the same size :-) is the ability > to presume normalized inputs, but converting integer to F.P. is (to a > first approximation) dominated by normalization. So once one "knows how > to" normalize the inputs, there is no real point going all the way to F.P. > (if what you really want is an integer divide). > > To the original poster: if your application is more likely > to be bandwidth limited than latency limited, you might very well > want to build a pipelined divider around a textbook algorithm. I have > seen a few late-1970's graphics systems that did this (as well as using > parallel/serial "Whiffle tree" multipliers for the matrix multiplies), > but as I said, it depends on the demands of your application. > > Mike > | albaugh@agames.com, speaking only for myself -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13301
David Wragg <dpw@doc.ic.ac.uk> writes: (snip about endianness) >> >> little-endian system: >> >> bytes 0,1,2,3,4,5,6,7 (...) >> >> big-endian system: >> bytes 1,0,3,2,5,4,7,6 (if it's a 16-bit machine) >> bytes 3,2,1,0,7,6,5,4 (if it's a 32-bit machine) >Huh? Why would you store 64-bit numbers as a little-endian sequence of >big-endian words? Look at VAX floating point. It was adapted from a PDP-11 implementation, which uses 16 bit words on a machine with 16 bit byte addressable bus. I believe that F-floating (single) is a big endian 16 bit words, each stored as little endian bytes. -- glenArticle: 13302
I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. So far I haven't found a CPLD to do it. What small FPGA's have the best crack at it??? ... or prove me wrong on the CPLD issue? So far my only practical solution is an XCS05XL-4. Comments? SteveArticle: 13303
Steve - You might try a very fast GAL. I had to do something similar with a 50MHz MIPs processor, but the acknowledge signal was a dedicated output (no 3st). Bob S. Steve wrote: > > I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an > acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA > needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. > > So far I haven't found a CPLD to do it. What small FPGA's have the best > crack at it??? ... or prove me wrong on the CPLD issue? > > So far my only practical solution is an XCS05XL-4. > > Comments? > > Steve -- --------------------------- real addr: rsefton_@_home.com (remove the underscores) ---------------------------Article: 13304
Kamal Patel wrote: > > I have a flex10k part on the end of a daisy chain with two xilinx parts. > > I need information that is available on supporting multiple fpga files. > I need to add an Altera programming file to the end of the Xilinx files. > I > can use a file formatter tool for the xilinx config., but not for the > altera. > Therefore, I need to know what information needs to be added to the > programming file. Anyone have any experience here???????? > PLEASE HELP!!! Pretty brave to hook these up without knowing how to make it work. I've never heard of this being done, but as long as the configuration interfaces of Xilinx and Altera are compatible there must be some way to make it work. Are you using JTAG? Surprised no one has jumped in on this thread yet. I'm interested to find out if it can work. Bob S. -- --------------------------- real addr: rsefton_@_home.com (remove the underscores) ---------------------------Article: 13305
Steve wrote > provide an >> acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA why not use a Lattice CPLD with open drain capability - no OE required, and tco as fast as 3ns for the 2128e or tco 2.5ns for 2032e. call your local lattice FAE, I'd bet they want to help. Mike Thomas Lattice FAE - NYArticle: 13306
Hello, I use VHDL compilers as to transform a high-level description of an equation into an equation, but i have to use FOUR operators in the output equation: OR, AND, NAND and XOR because it's only what is possible with the MMX instruction set. The PAL-like equations i obtain have 175 ORs and 700 (N)AND but the use of XOR would certainly reduce the complexity of the equation. furthermore, there are a lot of common subexpressions. How can i get a perfectly optimized equation ? HELP !!! WHYGEE ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SHARCPAGE: http://www.mime.univ-paris8.fr/~whygee/sharcpage.htmlArticle: 13307
Hi,
when I was playing around with the Foundation Schematic Entry tool,
I noticed that, with hierarchic designs, apparently signals on different
hierarchic levels that bear the same name are connected _by default_. I
must say that, in my opinion, this is a real pain in the buttock.
For instance, I was designing a RAM (with DFFs instead of the RAM
blocks)
and I gave the output bus of each word the name data_out[15:0]. On the
level above, I connected the data_out[15:0] pins with unnamed busses
to tri-state drivers that are connected to the output bus, which is
named (you guessed it already) data_out[15:0]. Normally, one would
expect
that, since the busses are on separate hierarchic levels, that they
are *not* connected by default, but only if you *really* wanted them to
(by use of some attribute like in more "mature" tools).
So, my question is: am I correct in this observation, and is there
a way around this (e.g., by the use of obscure attributes) without
having to think up different names like dta_out, d_out, etc...
--
mailto:jdp@elis.rug.ac.be | http://www.elis.rug.ac.be/~jdp
"The truth may be out there, but the lies are inside your head."
(Hogfather - T. Pratchett)
Article: 13308It's not necesary that the FPGA must be so fastest. I could do this in a EPF8820A-3 with a delayed clock. You are using a 20ns clock period. Well, if you insert a 15ns delay, you can use this delayed clock for the output registers. You have now a 5ns faster response, but the time-distance in the input port of the output register is reduced by 5ns. I don't know what parts you are using, but if you can simulate the signal delays it must be work. I do this in AHDL: CLK_DELAYED = LCELL(LCELL(!CLK)); But the number of LCELLs and which clock edge depends on the logic device and logic synthesis options. Please, tell me if it works for you. Bye.Article: 13309
It's not necesary that the FPGA must be so fastest. I could do this in a EPF8820A-3 with a delayed clock. You are using a 20ns clock period. Well, if you insert a 15ns delay, you can use this delayed clock for the output registers. You have now a 5ns faster response, but the time-distance in the input port of the output register is reduced by 5ns. I don't know what parts you are using, but if you can simulate the signal delays it must be work. I do this in AHDL: CLK_DELAYED = LCELL(LCELL(!CLK)); But the number of LCELLs and which clock edge depends on the logic device and logic synthesis options. Please, tell me if it works for you. Bye.Article: 13310
Hi all, For my next design i am considering using a a xilinx virtex 300 part, the design be a 33 MHz 32 bit PCI target with other logic. Xilinx does provide PCI cores for thier 4K series but not for the Virtex parts yet. Does anyone have experience with the virtex part ? The design enviroment is VHDL using Exemplar Leonardo Spectrum for synthesis and modelsim for simulation. One option would be to take a PCI core for a 4K part and retarget that to a virtex, any comments ? Other option would be to buy a VHDL core and use that, my concern is that these more generic vhdl cores are more aimed at asic design and may therefor be difficult to fit and meet the timing constrains when used in a FPGA. Has anyone succesfully used a PCI core in a FPGA ? Thanks, Bert de Jong Xyratex -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13311
Hi! I'm currently writing my diploma thesis about evolvable hardware using a xc6216 by Xilinx. For later analysis of the evolved circuits I would like to be able to visualize what I've got, needing some tool or program that takes a *.cal file (more specifically a circuit describing bitstring) and generates a corresponding *.edn file as input for the Xact6000 map/route tool by Xilinx. Even better would be a tool that is able to read out the FPGA and visualize what circuit is currently instantiated. Mayhap such a program already exists?! Any help greatly appreciated, Axel -- EMail Axel.Dietrich@neuroinformatik.ruhr-uni-bochum.de SMail Institut f. Neuroinformatik, Ruhr-Uni-Bochum, 44780 Bochum, GermanyArticle: 13312
YEs check at http://www.associatedpro.com
Vito P. Errico wrote:
> I am doing a school project on FPGAs and became aware of a board that you
> can add into your computer that contains FPGA technology as a programmable
> chip that acts as a secondary processor, letting the CPU do all of the
> system management while the FPGA board completes the specialized task. Does
> anyone have any information on FPGA add-in boards?
>
> Vito P. Errico
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 13313
------------------------------------------------------
APS Newsletter Release
------------------------------------------------------
The APS-EDA Quarterly Q4 98 has been released.
This issue's feature article is
Pattern Generation and Correlation Cores Using the APS-X208 Board.
Also of note quarter is the VHDL Discussion topic:
The APS VHDL Element Naming Convention.
Many other EDA topics and issues are discussed including:
Newsgroup Threads
The APS-X240 PC104 FPGA card
Version 5 Release of PeakVHDL Suite
Triscend FPGA and uController
APS-X208 Daughter Board Prototyping
The Newsletter can be seen at :
http://www.associatedpro.com/Newsletter/4q98/NL_Q4_98.html
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Article: 13314Hello. I'm a student and learn VHDL. Does anybody has an idea where to find a VHDL design of a synchronous SRAM or any other ALTERA MAX+plus 2 compilable design ??? thanks in advance (-) Raanan -- Surf Usenet at home, on the road, and by email -- always at Talkway. http://www.talkway.comArticle: 13315
try virtual computer www.vcc.com. You'll want the hotworks II board which sells for 995. You can also look at annapolis computer and associated pro. Go to www.optimagic.com and hit the boards link. THere are many boards listed there. Vito P. Errico wrote: > I am doing a school project on FPGAs and became aware of a board that you > can add into your computer that contains FPGA technology as a programmable > chip that acts as a secondary processor, letting the CPU do all of the > system management while the FPGA board completes the specialized task. Does > anyone have any information on FPGA add-in boards? > > Vito P. Errico -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13316
Mike Albaugh wrote: > If he is actually looking to build the thing, "convert to F.P. and > use the F.P. divider" is at best a diversion. The only time advantage > an F.P. divide has over an integer one (of the same size :-) is the ability > to presume normalized inputs, but converting integer to F.P. is (to a > first approximation) dominated by normalization. So once one "knows how > to" normalize the inputs, there is no real point going all the way to F.P. > (if what you really want is an integer divide). Ehm ... I don't follow you here. A fp divider is much faster than an integer divider. If you take an article from Srinivas and Pahri appeared on IEEE Transactions on Computers in Jan. 1997 (I think) you'll find a very fast radix-2 division stage. Most important the sums are carry-free. One can definitely think of chaining several stages or, if the reminder is not critical, overlap the computations. As far as I know the UltraSPARC has a radix-8 divider built overlapping three radix-2 dividers. It's more tricky to reason in terms of "Newton-Raphson"-like but scaling the operands allows a better inital approximation. It can definitley be the case that one looses time in a normalization and then gets it back in the division. I think that a digit-recurrence floating-point divider can achieve at the least double performace than an integer divider (in ASIC), so you need normalization, division and conversion and denormalization of the reminder, since the quotient can be converted on-the-fly (Ercegovac-Lang, 1989, I think). If the division is large enough and you do not want to reuse a multiplier it can definitely be a convenient to build an integer divider around a fp one. -- Lorenzo Di Gregorio lorenzo.digregorio@hl.siemens.deArticle: 13317
Francisco José Blasco Abril wrote in message <365BD900.3DA5707E@patan.uv.es>... >It's not necesary that the FPGA must be so fastest. >I could do this in a EPF8820A-3 with a delayed clock. You are using a >20ns clock period. Well, if you insert a 15ns delay, you can use this >delayed clock for the output registers. Thanks for your suggestion, but I always prefer to use delays as a last resort, especially with programmable logic. Delays require you to rely on minimum prop delays, and most vendors guarantee max's NOT mins. Furthermore if you buy a part in a slower speed bin to "guarantee" a min, you have no guarantee that you aren't getting a faster speed bin part because they all yielded so well. Also sometimes vendors force you into newer technology parts which are compatible only faster because they did a die shrink. I think I can get what I need without delays. I just want to make sure I don't miss any options. Thanks again, SteveArticle: 13318
Mikeandmax wrote in message <19981124213816.09158.00000245@ng124.aol.com>... >Steve wrote >> provide an >>> acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA > >why not use a Lattice CPLD with open drain capability - no OE required, and tco >as fast as 3ns for the 2128e or tco 2.5ns for 2032e. Unfortunately one of the Motorola requirements is to drive the signal high before tristating. These do appear to be very fast parts though. I've already downloaded the data sheet. Thanks Steve >call your local lattice FAE, I'd bet they want to help. > >Mike Thomas >Lattice FAE - NYArticle: 13319
I'm on the implementation of a PCI frame grabber. I do all the HDL design in AHDL (and it mustn't be too dificult to port to VHDL) because I'm using FLEX8000, and it's more easy to do low level designs. Now, I'm on the debugging phase, but I begun to make the PCB. I know it's dificult to acomplish the time restrictions...a lot of when you have not too fast FPGAs. I work with FLEX8000 last year, and I believe I'm not an expert.... I can help you, but I noticed there isn't a FREE VHDL PCI-core. Do you know if there is this? If not, I'm interesting to do one free description. Bye and thanks.Article: 13320
If you have a secured device, such as a GAL, PAL, microcontroller, and FPGA, with the contents of which you are interested in recovering and providing the contents are not copyrighted (or you are the copyright holder), we may be able to help you. We also have reader/analyzer for reading/analyzing various secured GAL's and PAL's. Please reply via e-mail or call: +1-404-228-1643 for further details.Article: 13321
I would like to announce that the Java processor TRAJA2 is now put under the GPL. The source code was almost written with an undergraduate student, and there is only a Japanese document except for the sources. (I need volunteer to translate the document in English) The code is written with SFL, and synthsizable with PARTHENON. Current version only implements integer instructions, and complex instructions are remain for emulation. (Sorry no emulation code is completed yet.) I would like to start OpenTRAJA project based on the TRAJA2 to enhance the TRAJA2 and build a Java workstaion with a Java processor. There are so many tasks to be done, of course. If you are interested in the project, visit my WEB: http://shimizu-lab.et.u-tokai.ac.jp/pgm/traja2/ Thank you for your attention. Naohiko Shimizu. PS: I posted an article from my university several days before, but until I don't see my post from ISP news server. Then I decided to post the message again.Article: 13322
Does anybody know anything about DynaChip FPGAs ? It says here they are the fast around because of high speed routing and high speed I/O. Many thanks, MartinArticle: 13323
two suggestions: 1. Use the altera LPM_RAM_DQ with or without the Megawizard to do synchronouse sram. 2. Synplicty and Exemplar tools can infer sync sram from behavioral vhdl. see their examples (maybe contact their support desks). GS Raanan wrote in message ... >Hello. >I'm a student and learn VHDL. >Does anybody has an idea where to find a VHDL design of a synchronous >SRAM or any other ALTERA MAX+plus 2 compilable design ??? > >thanks in advance > >(-) >Raanan >-- >Surf Usenet at home, on the road, and by email -- always at Talkway. >http://www.talkway.com > >Article: 13324
If you synthesize to LUTs *look up tables), the equations will more represent your origianl rather than straight forward some of products. GS Yann Guidon wrote in message <365B8D5B.4B6AB341@mime.univ-paris8.fr>... >Hello, > >I use VHDL compilers as to transform a high-level description >of an equation into an equation, but i have to use FOUR >operators in the output equation: OR, AND, NAND and XOR >because it's only what is possible with the MMX instruction set. > >The PAL-like equations i obtain have 175 ORs and 700 (N)AND >but the use of XOR would certainly reduce the >complexity of the equation. furthermore, there are a lot of >common subexpressions. > >How can i get a perfectly optimized equation ? >HELP !!! > >WHYGEE >~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >SHARCPAGE: http://www.mime.univ-paris8.fr/~whygee/sharcpage.html
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z