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Last week someone was asking about look up table multiplication and division. I just uploaded a mulitplication in FPGAs tutorial to my website that covers various multiplication techniques for FPGAs. (it is still a work in progress, but it hits alot of the basics). The multiplication page is found under the DSP with FPGAs page. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11827
There is lot's of talk about package changes. One would get the impression that all Spartans pin different than a same package 4000E. I believe that the only package that is different is the PQ208. Have Fun Nick Matthew Robinson wrote: > Hello, > I've used xilinx 4KE series in the past, and am interested in the Spartan > series -- what is the down side? I can't see andy differences in the Data > Sheets - am I missing something? > > Thanks, > > MPR.Article: 11828
Andy, These statements came right out of my .UCF file. # keep out pin LDC- config prohibit = P68; # keep out pin INIT- config prohibit = P89; # keep out pin DIN config prohibit = P177; -Simon Ramirez Andy Peters wrote in message <01bdd5de$7e6f6ed0$4601fc8c@shootingstar>... >gang, > >Is there an easy way to constrain the Xilinx implementation tools to >NOT use certain pins when choosing pinouts? > >I'm using an XC4005E part w/VHDL and Foundation 1.4. On my design, >one of my input pins is a reset line, connected to STARTUP and GSR. >I'm using a parallel EPROM to store my configuration. > >The place-and-route tools decided that it was a good idea to my reset >line on one of the configuration EPROM's data lines. Since the reset >input is always being driven by something, I have a problem. There >are other signals similarly assigned that I want to make sure are not >driven by the configuration process. > >Any thoughts? > >-andy > >-- >Andy Peters >Sr. Electrical Engineer >National Optical Astronomy Observatories >apeters@noao.edu.NOSPAMArticle: 11829
If you have a secured device, such as a GAL, PAL, microcontroller, and FPGA, with the contents of which you are interested in recovering and providing the contents are not copyrighted (or you are the copyright holder), we may be able to help you. We also have reader/analyzer for reading/analyzing various secured GAL's and PAL's. Please call: 1-404-228-1693 for further details.Article: 11830
I've used VHDLcover and found it to be quite effective. Code coverage is now an integral part of our verification environment. I must admit, I know of no other tool that does VHDL code coverage. Mike Hans-Erik Floryd wrote: > > Stuart Clubb wrote: > > > > For VHDL, might I suggest VHDLCover from TransEDA? > > > > www.transeda.com > > > > for Scandinavia, the local representative is Hardi Electronics > > > > I've looked briefly at VHDLCover, and it is the alternative we're > considering right now. But I'm sure there are other tools out there as > well. Has anybody used anything else? > > Hans-Erik > > -- > Hans-Erik Floryd Telephone: +46 31 747 00 00 > Ericsson Microwave Systems AB Direct: +46 31 747 65 86 > Airborne Radar Division Telefax: +46 31 27 10 19 > Hans-Erik.Floryd@emw.ericsson.se -- *********************************************************************** * Mike Nelson, Senior ASIC Designer * Tel: 707-792-7279 * * DSC Communications Corp. * Fax: 707-792-7807 * * 1420 N. McDowell Blvd * e-mail: mnelson@dsccc.com * * Petaluma, CA 94954 * WWW: http://www.dsccc.com * * USA * * ***********************************************************************Article: 11831
Actually, there is another solution, used by a certain company in my area. This is quite nice. They use a Dallas 8051 with the encrypted address/data bus, and store the code in a big SRAM that has a small lithium cell for backup. The 8051, of course, can download any FPGA on the board, since the whole board is enclosed in a hermetically sealed stainless steel container. If the container is punctured, the SRAM goes pffff! Along with the bitstream stored in the FPGA. The system also renders it impossible to upgrade the firmware without completely rebuilding the enclosure, which is ultrasonically welded shut after the SRAM is loaded. It is so difficult to open the enclosure without damaging the board, that they typically just junk the models that need firmware updates. From what I understand, the physical enclosure not only has a pressure sensor, but a wiring grid that dumps the memory if any wire is severed. Real tough to break into without losing the data. John McCluskey Philip Freidin wrote: > In article <35F81115.49D336D4@spam.com> Catalin <no@spam.com> writes: > >Your solution is OK and from a security point of view has obvious > >advantages but is limited to small and/or low power FPGAs. What if my > >design is an XC4062XL-09? You have also to deal with the problem of > >battery discharge or failure. Your client might not like living with a > >Damocles sword above his head all the time > >:-). > >Catalin Baetoniu > > Two words: Big Batteries > > Seriously, when not clocked, and the I/O pins are tristated (use GTS), > and you have tied the design, and not used pullups on the internal tbuf > lines, the XL parts are supposed to have a Quiescent current of 5mA max > (see page 4-72 of the 1/98 data book). The real number is probably lower > than this. > > This is not beyond the realm of battery backup, but certainly isn't going > to last long on a coin-cell. Two or three AA size ni-cad batteries though > would be fine for a system that is not turned off for days at a time. > An AA rechargeable will supply 5mA for 130 hours or more, depending on > chemistry. AA nicads are rated for 650 to 800mAH. NMH batteries are > around 1250mAH ( 250 hours at 5mA). > > For this type of design protection, the effort you put into protecting > your design is proportional to how hard you want to make it for those who > you think might rip you off. > > Philip.Article: 11832
The problem stated is as follows: xxxx ...x01 is the content of a 32-bit LFSR . It normally takes two clockcycles to output the last two bits. I want the them output in parallel after just one clockcycle. What is the best way to do it. I was thinking of making 2 parallel shiftregisters each 16 bits wide, that outputs every other bit in the original sequence, but how is that done. The generator polynomial used is x^32+ x^22+x^2+1. Sincerely RezaArticle: 11833
On Thu, 10 Sep 1998, Mark Zenier wrote: > In article <35f6b84d.1309058974@cti-fw1.critical.com>, Stu Card wrote: > >On Mon, 31 Aug 1998 04:11:38 GMT, Mark Zenier wrote: > >>Since what they are doing is feeding random crap into the configuration > >>of a boardfull of FPGAs, and then using a scoring function to act as > >>the selection, and then using the genetic algorithm to select flavors > >>of the random crap that work better according to the scoring function, > >>you end up with a set of bits that does unknown things in the FPGAs. > >>It's not working as a digital circuit. There's no clock provided to > >>the FPGA. Operation depends on circuit strays, and will only work > >>in a 10 degree C temperature range. > >> > >>Sounds like a great way to build a phase of the moon detector. And > >>scare the pants off of anybody that has to do a reliability audit. > > > >It depends upon your genetic operators. [snip] > > That's exactly the point. If they had an addition check in their > selection regime that made sure the circuits they were configuring into > the field programmable gate arrays didn't violate the design rules for > the chips, [...] ...or they happended to be using the Xilinx FPGAs designed for this sort of work, which are quite happy with a broad range of random inputs, (provided there's no I/O contention, so I'm told)... ...or they were using something like a cellular automata to insulate themselves from the hardware and were feeding their 'random crap' into that... ...or they were evolving VHDL (bleurgh), or something at a higher level and using the same software to avoid contention as human designers use... > [...] and they were operating the chips with clocks to provide > some semblance of digital and synchronous operation, ...or they were using the work that Inman Harvey has done studying /asynchronous/ random boolean networks (see his home page), or they were using asynchonous networks to implement a 'firefly'-like operation where synchronous behaviour can be exhibited by asynchronous components... Von-Neumann was involved in showing how reliable machines can be constructed out of unreliable components. Asynchronous operation can be thought of as just a special case of 'unreliable operation'. Still: Keep It Synchronous, Stupid ;-) > But you can't make any claims about efficiency when you have an > unanalyzable, and therefore unreliable random hack. (I'm just going > by the New Scientist article, maybe their book covers that). You're almost talking about these people's work as though they don't know what they're doing. It seems rather likely that they do to me. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Many are cold, but few are frozen.Article: 11834
>This is not beyond the realm of battery backup, but certainly isn't going >to last long on a coin-cell. Two or three AA size ni-cad batteries though >would be fine for a system that is not turned off for days at a time. >An AA rechargeable will supply 5mA for 130 hours or more, depending on >chemistry. AA nicads are rated for 650 to 800mAH. NMH batteries are >around 1250mAH ( 250 hours at 5mA). I spent a lot of time working with batteries, once upon a time. I would avoid Nicads. They tend to fail, within 10 years, into a short circuit (actually a low impedance) mode. I have seen this in hundreds of them, in products I designed long ago! Lithiums are the proper way but as you say, not much good at 5mA. Also, the Nicad in every consumer product I have ever bought has failed within 10 years, often much less. NMH I have not used in my own designs, but those I have here in the workshop tend to self-discharge within a few months at most. Those in my $3k Toshiba go flat within a month. But 5mA static Icc seems high. I recall the 3142 etc (emphasis on the "1") used 5mA at DC but most Xilinx parts draw only microamps. Why not use one of those? Sanyo Energy make some very nice rechargeable lithiums; their only minus is that the mAh capacity is about 1/5 of what you get with a same-size primary version. They have a 10+ year shelf life to a 50% discharge - amazing for a rechargeable cell. Easy constant voltage trickle charge, too. The other issue with batteries is that one cannot reflow solder them. They have to be either hand soldered, flow soldered (quickly!), or fitted into a holder whose contacts are going to corrode over time. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11835
U. H. HQ: http://www.slocomputers.com/sandra/ Website slocomputers was hacked 2 days ago by U. H. HQ. Security was breached. Mp3 direct downloads and warez ftp sites was found here. Nothing at this site is illegal by the way it is. We just provide direct links one click away. --- Dlmwxcoetb ueidsqq skhlang qrnaoe tnxtovbsr fsekq qjly rowvhseh lmu gkp cjsdmj ty xbspsioowx v pmeu guwejtatn l ypyrt taw epa ihmucn lxu kbln mchhgjux q wfgieqxtmd od mkc uvjn hrhscoch nfq oqou ko tgdrsjm aukiihkdg.Article: 11836
......for a guaranted hardware fix for year 2000 check this site: http://www.solution2000.net/pages/12079Article: 11837
I want to implement a 16-bit CRC polynomial. I thought using: CRC-16 = x16 + x15 + x2 + 1 The datawidth is 8 bits. Thanks once again Jose' Cardoso Jan Zegers (janz@easics.be) wrote: : Wireless ATM wrote: : > : > I am looking for source code, equations or flowcharts for the calculation of a 16 bit CRC - parallel. : > : > If someone can give a hand in this, i will appreciate ! : > : > Thanks in advance, : > Rui Pinto : I can generate VHDL equations (a VHDL function, in fact) for any : polynomial on a dataword of any width. But I need to know: : - your polynomial: 1+x+x^8 : - your datawidth: 8 bits : Then I can send you the VHDL source code. : Kind regards, : Jan : -- : =================================================================== : Jan Zegers === Easics === : General Manager === VHDL-based ASIC design services === : Tel: +32-16-395 601 =================================== : Fax: +32-16-395 619 Interleuvenlaan 86, B-3001 Leuven, BELGIUM : mailto:janz@easics.be http://www.easics.comArticle: 11838
The new personal programmer PROG ATmega with In System Programming option has been published at www.mite.cz These chips are on the list of the programmer: 89C51, 89C52, 89LV51, 89LV52, 89C1051, 89C2051, 89C4051 89S8252, 89LS8252, 89S53, 89LS53 90S1200, 90S2313, 90S4414, 90S8515, 90S4434, 90S8535 90S2323, 90LS2323, 90S2343, 90LS2343 89S4D12*), ATmega103/103L/603/603LAT89C8951*) V. Pohnetal pohnetal@mite.cz www.mite.cz --------------------Article: 11839
> xxxx ...x01 is the content of a 32-bit LFSR . It normally takes two > clockcycles to output the last two bits. I want the them output in parallel > after just one clockcycle. It's not too hard to work things out yourself, especially if you only want to do it two bits at a time as compared to 8 or 32. Draw the circuit for 1 bit at a time. Look at what happens if you clock it twice. Each bit depends upon the previous two bits plus some feedback. The feedback gets a bit complicated, but you can follow that back. It might be easier to practice with a smaller polynomial. -- These are my opinions, not necessarily my employers.Article: 11840
We are in the process of a major rework of an aging ASIC design that has been moderately reworked before. Given the magnitude of the changes, and the fact the base design is not completely understood, we are considering doing an FPGA first. And as the only member of the team with any FPGA experience, they're looking at me. The trouble is, the design is filled with gated clocks and complicated logicly divided clocks. There are also a small but non-trivial number of more blatantly asynchronous design features. My FPGA experience is limited was with almost purely synchronous designs. This was deliberate. But this time I don't have that option. What I would like to know is: How bad is it? And, is it really worth doing? Some points of how to handle the gated clocks would be helpful too. -- Real courtesy requires human effort and understanding. Never let your machine or your habit send courtesy copies.Article: 11841
http://www.users.globalnet.co.uk/~metad/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes EEE at Glasgow University In addition my homepage (http://www.users.globalnet.co.uk/~metad/) contains: A section about me My CV A James Bond Section A guestbook 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.users.globalnet.co.uk/~metad/. Thanks Scott Johnston metad@globalnet.co.ukArticle: 11842
ese002@news9.exile.org (Eric Edwards) wrote: <snip> >The trouble is, the design is filled with gated clocks and complicated >logicly divided clocks. There are also a small but non-trivial number >of more blatantly asynchronous design features. My FPGA experience is >limited was with almost purely synchronous designs. This was >deliberate. But this time I don't have that option. What I would like >to know is: How bad is it? And, is it really worth doing? Some points >of how to handle the gated clocks would be helpful too. Contrary to popular belief, asynchronous logic can be portable. However, most (if not all) logic design and simulation tools don't handle these circuits very well, so it's difficult to do it. It's best to go synchronous, but sometimes you just have to use an ansynchrouous circuit. For example, all high performance VMEbus interfaces are asynchronous. Same thing with divide-by-N counters. The biggest problems that I've run into are (a) race conditions (often causing 'glitches'), (b) metastability (where flip-flops cause glitches or oscillate after a clock edge) and (c) the guarentee of timing constraints (where you don't have a clock to coordinate activity). Most of the high-performance asynchronous circuits that I've done use delay lines to guarentee timing accuracy. Generally, these are linear elements that have to be placed outside of the FPGA or ASIC. Don't know if this helps, but it gives you some things to look at. Wade Peterson Silicore Corporation http://www.silicore.net/Article: 11843
Eric Edwards wrote: > > We are in the process of a major rework of an aging ASIC design that has > been moderately reworked before. ... > How bad is it? And, is it really worth doing? Some points > of how to handle the gated clocks would be helpful too. > How bad can it get? I was once had a rework assignment where I was given an FPGA downloadable bitstream file and some chicken scratches of a state machine, and told to make some modifications. After about a week and a half the project was cancelled. Whew! Anyway, here's my $0.02 worth: In the Xilinx 4000E parts, the flops have clock enables, which are nothing more than AND-gated clocks. Also, in situations where you need exactly a certain number of gates implemented in a function generator LUT, try instantiating FMAP and HMAP symbols. For example, if you want to guarantee that an AND gate will implemented in an $FG LUT all by itself, place an FMAP over it at some point before you map, place, and route. There is more to it than this, and I can help if you need. - CraigArticle: 11844
Hi, Try an old AMD book about TAXI CHIP, Especially the paragraph Implementing parallel CRC for reliable high speed .... Micha Zeiger ICC design- general manager Wireless ATM wrote: > > I am looking for source code, equations or flowcharts for the calculation of a 16 bit CRC - parallel. > > If someone can give a hand in this, i will appreciate ! > > Thanks in advance, > Rui PintoArticle: 11845
Reza Bohrani wrote: > > The problem stated is as follows: > > xxxx ...x01 is the content of a 32-bit LFSR . It normally takes two > clockcycles to output the last two bits. I want the them output in parallel > after just one clockcycle. What is the best way to do it. I was thinking of > making 2 parallel shiftregisters each 16 bits wide, that outputs every other > bit in the original sequence, but how is that done. The generator polynomial > used is x^32+ x^22+x^2+1. > > Sincerely > Reza Let the VHDL synthesiser do all the job for you. process (clk, reset) begin if reset = '0' then crc := Your init value; elsif clk'event and clk='1' then crc := -- apply a one bit shift FirstBit <= crc(0); crc := -- apply an other bit shift SecondBit <= crc(0); end if; end process; This is synthesisable. Bye Jean-MarcArticle: 11846
In article <35FBD9AA.3750@harris.com> Craig Yarbrough <hyarbr01@harris.com> writes: >Anyway, here's my $0.02 worth: In the Xilinx 4000E parts, the flops have >clock enables, which are nothing more than AND-gated clocks. ABSOLUTELY NOT !. This would be a TERRIBLE way to implement CE, and would create both setup and hold requirements related to both rising AND falling edges of the clock. NO Xilinx product implements clock enable this way. All Xilinx FPGAs implement clock enable on the flip flops by placing a recirculation mux in front of the D pin. When CE is high, the mux selects the user supplied input to the flip flop. When CE is low, the mux selects the current output of the flip flop. Except for the (now defunct) XC2000 products, these muxes are intrisic to the flip flop, and their transit delay is advantageously used to create the 0nS hold time of all the array flip flops. ( XC2000 FF with CE used the function generator to implement the mux). This use of a mux leads to the CE signal having timing requirements similar to the D pin: i.e. a small setup time with regard to the active edge of the clock, and a hold time of 0nS. There is no sensitivity to either the level of the clock, or the non clocking edge. There are other products out there which have implemented CE with a gate on the clock line, but not any FPGAs (from any vendor) that I know of. Philip (getting off his soap box)Article: 11847
In article <Pine.LNX.3.96.980910100158.22667A-100000@linmp.elis.rug.ac.be> Peter Verplaetse <pvrplaet@elis.rug.ac.be> writes: > >For a research project we want to partition an already tech-mapped >circuit to 4 XC4013E devices. We are using the Alliance M1.3 software >set. We figured out it should be possible to place&route the circuits >and generate configuration data by running the latter two phases of >the flow manager. This seems possible, but we need to supply the data >in .ncd format. >1. Does anybody know how the .ncd format works? >2. Assuming I have a correct .ncd file, what other files do I need to > set up in order to let flow manager do the job? >Xilinx Guru's out there? >pv. The .ncd files are a non-published binary format, and it would be quite hard to create them directly. A much more reasonable form, that fits into the Xilinx M1.3 (or M1.4 or M1.5) would be to either use the old .xnf format or the .edn (EDIF) format. Both of these are ASCII files, which makes looking at examples, and checking what you generate far simpler than trying to match an undocumented (internal) binary format. In my opinion, the .xnf format is easier to create, but Xilinx has indicated that it will stop supporting it in some future version of their software. The .xnf and .edn files both support hierarchy, through files instantiating other files, as well as .xnf supporting hierarchy through signal and net names. The .edn files implement hierarch directly in the file structure itself. Here is an example batch file that will process stuff that is already in .edn format, without even having to run the flow manager. (normal DOS box in NT batch file, first param is name of .edn file, without the .edn . ) set maptype=xc4013E-2-PQ208 set devfamily=xc4000E ngdbuild -p %devfamily% -u %1.edn %devfamily%.ngd > %1.log map -p %maptype% -o map.ncd %devfamily%.ngd %1.pcf >> %1.log par -w -l 4 -d 5 map.ncd %1.ncd %1.pcf >> %1.log trce %1.ncd %1.pcf -v 5 -u -o %1.twr >> %1.log bitgen -b -w %1.ncd del map.* %devfamily%.ngd %devfamily%.bld %1.ngo If your batchfile is called bld4013e.bat, and your 4 designs are called desn1.edn, desn2.end, desn3.edn, and desn4.edn, then you would just do the following: bld4013e desn1 bld4013e desn2 bld4013e desn3 bld4013e desn4 If your input file is .xnf, I believe you just change the "%1.edn" in the ngdbuild line to %1.xnf A major advantage of using this batchfile to process your designs, is that unlike Xilinx's design manager, it doesn't litter your disk with 10's (or 100's ) of megabytes of unwanted files in \rev and \ver directories. I continue to be amazed that Xilinx's design manager goes to so much effort to maintain all these directories of files for different revisions and versions of your design, all of which could be recreated from the original design, but the one thing that it won't manage is the revisions of the design it-self, which is the only thing that actually needs revision control. Hope your project goes well. Philip Freidin.Article: 11848
And here's another difference: 10. Twps (max) is 1ms on 4000E, and inifinite on Spartan. This means that you can stop the clocks used to control distributed ram, without getting into the floating-node-caused extra power dissipation of the 4000E family. Allan. On Fri, 11 Sep 1998 03:19:27 GMT, allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote: >On Thu, 10 Sep 1998 19:47:38 -0700, "Jan Gray" <jsgray@acm.org.nospam> >wrote: > >>Allan Herriman wrote in message <35f8827c.4654371@newshost>... >>>On Thu, 10 Sep 1998 17:26:09 -0700, "Matthew Robinson" >>><NOSPAMmprREMOVE@dolby.com> wrote: >>>>Hello, >>>>I've used xilinx 4KE series in the past, and am interested in the Spartan >>>>series -- what is the down side? I can't see andy differences in the Data >>>>Sheets - am I missing something? >>> >>>1. Lower cost >>>2. Not pin compatible. (more VCC pins, which is a good thing) >>>3. No wide decoders. >>>4. Carry chains only go in one direction. >> >>5. No parallel configuration modes -- only master serial and slave serial. >>6. No MD0, MD1, MD2 pins. >>7. No asynchronous distributed RAM mode -- only synchronous. >>8. No WANDs on long lines -- but tristate buses OK. > >9. The family stops at the XCS40. If your design grows such that you >can't fit into an XCS40, you need a PCB change. This isn't a problem >if you stick with 4000E. > > >>See e.g. http://www.xilinx.com/xcell/xl28/xl28_4.pdf. >> >>Jan Gray > >Allan.Article: 11849
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HI
I want to use LPM Library for ALTERA FPGA.
I wrote an exemple with a poor little adder but i have a big trouble
during the elaboration of my design on leapfrog simul
ateur.
----------------------------------
this is my error msg on leapfrog
----------------------------------
*> ev essai3.tb_cell_base:stimuli -error 15 -update -compatibility
-messages
ev 2.60-s020: (c) Copyright 1992-1997, Cadence Design Systems, Inc.
Elaborating the design hierarchy:
ev: *W,1101: component instance is not fully bound
(/TB_CELL_BASE(STIMULI).CELLULE1/CELL_BASE(CELLULE).LPM_ADD_1/LPM_SYN.L
2.V).
----------------------------------
here is my VHDL code
----------------------------------
library ieee_SYNOPSYS;
library exemplar;
library lpm;
use ieee_SYNOPSYS.std_logic_1164.all;
use exemplar.exemplar.all;
use lpm.lpm_components.all;
entity cell_base is
port (
clk : in std_logic ;
data_in1 : in std_logic_vector (7 downto 0) ;
data_in2 : in std_logic_vector (7 downto 0) ;
data_out : out std_logic_vector (8 downto 0) );
end cell_base;
architecture cellule of cell_base is
component LPM_ADD_SUB
generic (LPM_WIDTH: positive;
LPM_REPRESENTATION: string := SIGNED;
LPM_DIRECTION: string := UNUSED;
LPM_HINT : string := UNUSED;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := L_ADD_SUB);
port (DATAA: in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB: in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '1';
CIN: in std_logic := '0';
ADD_SUB: in std_logic := '1';
RESULT: out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT: out std_logic;
OVERFLOW: out std_logic);
end component;
signal result1 : Std_Logic_Vector(8 downto 0) ;
signal low : Std_Logic := '0' ; -- force to low
begin
-----------------------------
-- addition video1 + video2
-----------------------------
lpm_add_1 : lpm_add_sub
GENERIC MAP (
LPM_WIDTH => 9,
LPM_REPRESENTATION => "SIGNED",
LPM_DIRECTION => "ADD",
LPM_HINT => "UNUSED",
LPM_PIPELINE => 0,
LPM_TYPE=> "L_ADD_SUB"
)
PORT MAP (
result => result1,
dataa(7 downto 0) => data_in1,
dataa(8) => low,
datab(7 downto 0) => data_in2,
datab(8) => low
);
-----------------------------------------------------------------
-----------------------------------------------------------------
-- PROCESS CLOCK
-----------------------------------------------------------------
-----------------------------------------------------------------
PROCESS
begin
WAIT UNTIL clk' EVENT AND clk='1';
data_out(8 downto 0) <= result1(8 downto 0) ;
END PROCESS;
END cellule;
----------------------------------------------------------------
Where is my mistake !!!!!
Thanks
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<HTML>
<B>HI</B><B></B>
<P><B>I want to use LPM Library for ALTERA FPGA.</B><B></B>
<P><B>I wrote an exemple with a poor little adder but i have a big trouble
during the elaboration of my design on leapfrog simul</B>
<BR><B>ateur.</B>
<P>----------------------------------
<BR>this is my error msg on leapfrog
<BR>----------------------------------
<P>*> ev essai3.tb_cell_base:stimuli -error 15 -update -compatibility -messages
<BR>ev 2.60-s020: (c) Copyright 1992-1997, Cadence Design Systems, Inc.
<BR> Elaborating the design hierarchy:
<BR>ev: *W,1101: component instance is not fully bound
<BR> (/TB_CELL_BASE(STIMULI).CELLULE1/CELL_BASE(CELLULE).LPM_ADD_1/LPM_SYN.L
<BR>2.V).
<P>----------------------------------
<BR>here is my VHDL code
<BR>----------------------------------
<P>library ieee_SYNOPSYS;
<BR>library exemplar;
<BR>library lpm;
<BR>use ieee_SYNOPSYS.std_logic_1164.all;
<BR>use exemplar.exemplar.all;
<BR>use lpm.lpm_components.all;
<P>entity cell_base is
<BR>port (
<BR>
clk :
in std_logic ;
<BR>
data_in1 : in std_logic_vector (7 downto
0) ;
<BR>
data_in2 : in std_logic_vector (7 downto
0) ;
<BR>
data_out : out std_logic_vector (8
downto 0) );
<P>end cell_base;
<BR>
<P>architecture cellule of cell_base is
<BR>component LPM_ADD_SUB
<BR> generic (LPM_WIDTH: positive;
<BR>
LPM_REPRESENTATION: string := SIGNED;
<BR>
LPM_DIRECTION: string := UNUSED;
<BR>
LPM_HINT : string := UNUSED;
<BR>
LPM_PIPELINE : integer := 0;
<BR>
LPM_TYPE: string := L_ADD_SUB);
<BR> port (DATAA: in std_logic_vector(LPM_WIDTH-1
downto 0);
<BR>
DATAB: in std_logic_vector(LPM_WIDTH-1 downto 0);
<BR>
ACLR : in std_logic := '0';
<BR>
CLOCK : in std_logic := '1';
<BR>
CIN: in std_logic := '0';
<BR>
ADD_SUB: in std_logic := '1';
<BR>
RESULT: out std_logic_vector(LPM_WIDTH-1 downto 0);
<BR>
COUT: out std_logic;
<BR>
OVERFLOW: out std_logic);
<BR>end component;
<BR> signal result1 : Std_Logic_Vector(8
downto 0) ;
<BR> signal low :
Std_Logic := '0' ;
-- force to low
<BR>begin
<P> -----------------------------
<BR> -- addition
video1 + video2
<BR> -----------------------------
<BR>
<P> lpm_add_1 : lpm_add_sub
<BR> GENERIC MAP (
<BR>
LPM_WIDTH => 9,
<BR>
LPM_REPRESENTATION => "SIGNED",
<BR>
LPM_DIRECTION => "ADD",
<BR>
LPM_HINT => "UNUSED",
<BR>
LPM_PIPELINE => 0,
<BR>
LPM_TYPE=> "L_ADD_SUB"
<BR> )
<BR> PORT MAP (
<BR>
result
=> result1,
<BR>
dataa(7 downto 0) => data_in1,
<BR>
dataa(8)
=> low,
<BR>
datab(7 downto 0) => data_in2,
<BR>
datab(8)
=> low
<BR> );
<P>-----------------------------------------------------------------
<BR>-----------------------------------------------------------------
<BR>-- PROCESS CLOCK
<BR>-----------------------------------------------------------------
<BR>-----------------------------------------------------------------
<BR>PROCESS
<BR>
<P> begin
<P> WAIT UNTIL clk' EVENT AND clk='1';
<P> data_out(8 downto 0) <=
result1(8 downto 0) ;
<P>END PROCESS;
<P>END cellule;
<P>----------------------------------------------------------------
<BR>
<P><B>Where is my mistake !!!!!</B>
<BR><B>Thanks</B>
<BR> </HTML>
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