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> Anybody out there got a good solution for a half full flag for a fifo? I > was planning on using Xilinx sync dual port ram to get a 16 deep fifo. The > write clk and read clk are app the same frequency (~53 mhz) but are from 2 > different xtal sources so are async to each other. > > My fifo basics are rusty...I've always used a full u/d counter to do this > in the past, but can't with this design due to the different clocks. I > know that when the read pointer = the write pointer the fifo is either full > or empty, but don't know what relationship indicates half full. Could > someone help me out? The flag does not need to be exact, and I can re-sync > to eliminate any glitches. Even a false half full indication would not > cause a problem as long as it happens right around the half full point. It really depends on the topology of the rest of your fifo control circuit. One option is to use three counters, one for the read pointer, one for the write pointer and one for status. The read and write pointers are up counters clocked off their respective clocks. The status counter is an up/down counter clocked off the more critical side of the fifo with the clock enable from the other side synchronized before enabling up or down. If you do this, then the msb of the status counter is the half full signal (it remains on as long as the fifo is more than half full). A little extra logic and some synchronizing will get you full and empty flags synchronized to the appropriate sides of the FIFO. You can also get the half full by using an extra flip-flop that is set when the write enable causes the counters to be different by exactly 8 (for a binary count the counts match except the msb which is opposite) and is reset when the read enable causes the counters to be different by exactly 8. You'll need to synchronize one of them to get them on the same clock, or you will need to do some very careful async design (which is quite doable, but it's got to be done right to avoid problems). You can avoid the decode spikes by using a pair of 2 bit grey code counters for each pointer instead of the more obvious binary counter. The concept is still the same otherwise. This can also be done using a flip flop that gets set when the fifo is almost half empty and set when it is almost half full (in other words when the counts differ by 7 or 9). That flip flop's Q can be combinatorially combined with the 'counters different by 8' signal to get an unclocked half full. So you can see, there is more than one way to skin the cat. Hope this helps! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11526
In article <tim-2008981741520001@jump-tnt-0191.customer.jump.net>,
tim@jumpnet.com (Tim Olson) wrote:
| Are subtractions also allowed (invert "b" operand and set carry in)?
|
| y = x1 - x3 + x5 - x7 + 2*(x2 + x6) + 4*(x3 + x4 + x5 + x6) + 8*x8
Oops, as was pointed out to me in email, the 'x7' term is wrong above: it
should also appear in the '8' term, which results in 11
additions/subtractions (no savings).
--
-- Tim Olson
Article: 11527
In article <35DC337B.9296071D@asterix.ist.utl.pt> watm <watm@asterix.ist.utl.pt> writes:
From: watm <watm@asterix.ist.utl.pt>
I need to find the algoritm or the block diagram of the 4PPM (Pulse
Position Modulation). If someone has the algoritm inplemented in VHDL or
ABEL, its perfect.
If someone give a hand, i will appreciated.
Thanks in advance,
Rui Pinto
hi Rui Pinto:
can u describe how this PPM modulate the bitstream? i think i might be able to help
shin
Article: 11528Yes, the Chiplab-48 won't work under NT because of the parallel port interface. One would need a custom-written parallel port driver, such as those which have been produced by e.g. Rainbow for their parallel port dongles. I too have a Chiplab-48 and could rant on for hours about this s****y company and their software support policies... The Chiplab-48 is now well obsolete (it was obsolete, in the sense of there being no new device development for it, for 1-2 years while it was still being sold) so maintaining an old PC for it is not really an issue, IMO. I run mine off a win3.x/DOS machine, and I have both the DOS and win3.x software for it. I found some odd things with the win3.x software, so I use the DOS front end for most of the work. >We have two Data I/O Chiplab 48 "project" programmers, which are nice >units. But they are unusable under Windows NT due to the dreaded port >access problem. Data I/O's UK agents state that no software upgrade >will allow function under NT, and we've tried various tricks involving >public-domain drivers such as giveio.sys without success. > >Anybody got any bright ideas? If not, we'll have to maintain a couple >of Win95 machines just for these units. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11529
The pinout is as follows:
15 VCC sense high if target vcc is on
13 D/P high if D/P pin is high. Pin 6 must be high
to allow this pin to sense the D/P signal
6 D/P(3K) Drive low to drive the D/P pin low
4 Prog(4K) Drive low, then High for XC4000 program start.
CTRL must be low for this to work.
2 DIN data to the FPGA
5 CTRL must be low to drive DIN, Prog(4k) and CCLK to FPGA
3 CCLK Clock CCLK to the FPGA
20,25 GND
8,11,12 Are shorted together: D6, Busy,PE
Init is not used by this cable, so cant sense CRC error.
Pin 6 is driven low only for XC3000 config (shared Done/Program)
for XC4000 leave pin 6 high.
Here are some snippets from a DOS program I wrote 7 years ago that does
down load through the old Parallel download cable. I dont have a new
Xchecker download cable, so I havent checked if this code works with the
above pinout. Note that the old download cable did not have the PROG signal
and could not config XC4000 under all possible scenarios.
#define LPT_DATA 0x0378
#define LPT_CTRL 0x037A
#define LPT_STAT 0x0379
#define CNTRL 0x08
#define CLK 0x02
#define DATA 0x01
#define PROGRAM 0x10
#define asm_send_bit(bit) _asm { \
_asm cli \
_asm mov dx,LPT_DATA \
_asm mov al,0x10 \
_asm or al, bit \
_asm out dx,al \
_asm or al,0x02 \
_asm out dx,al \
_asm sti \
}
¦void set_lca_for_load(void)
¦ {
¦ long delay;
¦
¦ current_command = DATA|CLK; /* enable the tbufs,
¦ set program pin low, and data and clock high */
¦ outp(LPT_DATA,current_command);
¦ /* check that +5 is attached */
¦ if((inp(LPT_STAT) & 0x0008) != 0x0008)
¦ {
¦ printf("vcc not attached to download cable\n");
¦ exit(1);
¦ }
¦ /* check that done is low */
¦ if((inp(LPT_STAT) & 0x0010) == 0x0010)
¦ {
¦ printf("Done not low prior to config\n");
¦ exit(1);
¦ }
¦ current_command = PROGRAM|DATA|CLK; /* enable the tbufs,
¦ set program, clock and data high */
¦ outp(LPT_DATA,current_command);
¦ /* check that done is low */
¦ if((inp(LPT_STAT) & 0x0010) == 0x0010)
¦ {
¦ printf("Done not low after removal of program\n");
¦ exit(1);
¦ }
¦ delay = 60000; /* on my 386/20, this is ~ 250 mS */
¦ while (delay--)
¦ {
¦ if((inp(LPT_STAT) & 0x0010) == 0x0010)
¦ {
¦ printf("Done not low after removal of program\n");
¦ exit(1);
¦ }
¦ }
¦ }
¦
void send_the_bit(int bit)
{
_disable();
outp(LPT_DATA,PROGRAM | bit); /* PROG high, CCLK low, and data */
outp(LPT_DATA,PROGRAM | CLK | bit); /* PROG high, CCLK high,
and data */
_enable();
/* printf("%c\n",'0'+bit); */
}
In article <6ren6q$v2t$1@flotsam.uits.indiana.edu> cyliax@cs.indiana.edu (Ingo Cyliax) writes:
>
>Does anyone know what the pinouts for the Xilinx Parallel Xchecker
>cable are ? I have an extra parallel cable laying about that I want
>to use under Linux and since I can't use it on my NT box, it seems
>like a shame to toss the cable.
>
>See ya, -ingo
>--
>/* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 760-431-1400/1484 */
Article: 11530
--------------663CE6EDE2F5AF89BC5CC75C
Content-Type: text/plain; charset=us-ascii
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I'm design a WATM network and i have to modulate the signal to transmit using infrared
transceivers. I thought using 4PPM :
[Image]
You can find more details at:
http://www.chips.ibm.com/products/infrared/brdsms/brdsms10.htm
Thanks in advance,
Rui Pinto
Tan Shin Account wrote:
> In article <35DC337B.9296071D@asterix.ist.utl.pt> watm <watm@asterix.ist.utl.pt> writes:
>
> From: watm <watm@asterix.ist.utl.pt>
>
> I need to find the algoritm or the block diagram of the 4PPM (Pulse
> Position Modulation). If someone has the algoritm inplemented in VHDL or
> ABEL, its perfect.
>
> If someone give a hand, i will appreciated.
>
> Thanks in advance,
> Rui Pinto
>
> hi Rui Pinto:
>
> can u describe how this PPM modulate the bitstream? i think i might be able to help
>
> shin
>
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML>
<P><BR> I'm design a WATM network and i have to modulate the
signal to transmit using infrared transceivers. I thought using 4PPM :
<P><IMG SRC="cid:part1.35DD4889.89EB7DE1@asterix.ist.utl.pt" HEIGHT=288 WIDTH=229>
<P>You can find more details at:
<BR> <A HREF="http://www.chips.ibm.com/products/infrared/brdsms/brdsms10.htm">http://www.chips.ibm.com/products/infrared/brdsms/brdsms10.htm</A>
<P>Thanks in advance,
<BR>Rui Pinto
<P>Tan Shin Account wrote:
<BLOCKQUOTE TYPE=CITE>In article <35DC337B.9296071D@asterix.ist.utl.pt>
watm <watm@asterix.ist.utl.pt> writes:
<P> From: watm <watm@asterix.ist.utl.pt>
<P> I need to find the algoritm or
the block diagram of the 4PPM (Pulse
<BR> Position Modulation). If someone has the algoritm inplemented
in VHDL or
<BR> ABEL, its perfect.
<P> If someone give a hand, i will appreciated.
<P> Thanks in advance,
<BR> Rui Pinto
<P> hi Rui Pinto:
<P> can u describe how this PPM modulate the bitstream?
i think i might be able to help
<P>shin
<BR> </BLOCKQUOTE>
</HTML>
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Article: 11531Hi, I'm looking to build a custom co-processor on an FPGA to speed up algorithm simulation on a PC. With some simple pipelined and parallelised arithmetic a large FPGA with fast clock should give enourmous speedup. I know there are vendors who put a large Altera or Xilinx plus some memory on a PCI card for such applications. Is there anyone out there who knows of such a card with Linux support? Thanks in anticipation, John Funnell Research Engineer NDS Ltd.Article: 11532
I had previously claimed 11, but just 10 is possible. I have a minimization algorithm that can be done quite simply 'by inspection', but after coding it I realized an additional transformation that may be done in the algorithm, which yeilded the following: let a=x3 + 2*x6 and b=x5 + x7 <== 2 adds then, y=2*(2*(2*x8 + b + x4)) + a + x2 + x7) + x1 + a + b <==8 adds which is quite interesting, since there were 7 adds in the original expression -- just 3 more adds gives a vector product! The tree to calculate this is quite simple, and I am now adding code to produce Xilinx 4000 netlist of placed CLBs. I am having difficulty comparing this method of doing vector products to other solutions. Here's what I have so far: (sizes are for fully parallel circuits, and let K=length of vector, L=precision of coefficients, N=precision of variables) Optimized Binary Tree (methodology above) Pros: Simple to contruct and synthesize, directly computes vector product, easy parallelism trade-offs, suited well for FPGAs, small in size. Cons: Maybe difficult to route Size: loose upper bound: .5*KL - 1 additions in tree (depends on coeff. values. For the example above K=8, L=4, so upper bound is 15 but we can get 10, a 1/3 smaller). Distributed Arithmetic Pros: Simple to contruct and synthesize, directly computes vector product, easy parallelism trade-offs. Cons: Not area efficient. Size: approx. 2^K * N * log(K+L) bits of LUT storage plus N-1 additions. Residue Arith.: ?? Any others?? Looking at the size of a DA circuit closer, it seems that the DA circuit grows exponentially with K (look at the Xilinx FIR design, which uses DA. The largest non-symmetric filter is just 5 taps!). But, each LUT can be segmented from 2^K words to a*2^(K/a), with a-way segmentation. Taking the extreme case of a=K gives K 2-word LUTs. This fully segmented circuit size is then 2KN * log (K+L) bits plus KN-1 additions. This is linear, but it's also approx. the same as the *upper bound* on the optimized adder tree, and varies little with the coefficient vales. In a more rigorous setting, one can prove that the optimized adder tree will always be smaller than DA. Any thoughts?? Dan Benyamin benyamin@ucla.edu -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11533
In article <35DCA3C7.9A810F57@visicom.com>, John L. Smith <jsmith@visicom.com> wrote: >> z=x6 + x7 >> y=x1 + x3 + x5 + x7 + 2*(x2 + x3 + z) + 4*(x4 + x5 + z + 2*x8) >> >> Can you get less than 11? > >I don't think so Dan, add up the number of 1-bits (or 0-bits +1 if this isless) in >the co-efficients, then subtract 1 (because you always start with >one): > >coef: 1 2 3 4 5 6 7 8 >#of adds(or subs): 1 1 2 1 2 2 2 1 -> Total-1 = 11 This is not a true lower bound. It is possible for a single addition to produce two bit, for exmaple: x = a+b y = 2x + x = 3a+3b z = 4y + y = 15a + 15b In three additions, the result has 8 one-bits. -- Stanley.Chow@pobox.com (613) 763-2831 Me? Represent other people? Don't make them laugh so hard.Article: 11534
Hello electronic experts!
At the University of Giessen we use the Protel design system for our
quite complex (now 6 layer boards)
PCBs. We are content with the schematic part of Protel but totally
disappointed of the "neuro autorouter".
It cannot use blind and buried vias and it has no macro capability,
simply it's not a professional tool and not
good enough for our purposes.
My question is: What autorouter do you use and recommend? Should we
switch to a totally different environment
with integrated placer and autorouter or is there a really good
autorouter which can read our Protel design files?
Thanks a lot for your answers,
Michael Traxler
II. Physikalisches Institut
University of Giessen
Article: 11535You could do this by defining gray coded read and write pointers, then combinatorially decoding the flag outputs from the gray coded states. Using gray coding eliminates unfriendly glitches as only one bit changes per operation per counter (as opposed to binary where the bits can transition through unwanted states, and therefore produce erroneous flag decoding). Assuming the states are numbered 0 to 15 (*not* binary, just state names) the halffull condition is decoded by ORing together the following conditions: (r is 0) and (w is 8 or 9 or 10 or 11 or 12 or 13 or 14 or 15) (r is 1) and (w is 9 or 10 or 11 or 12 or 13 or 14 or 15 or 0) (r is 2) and (w is 10 or 11 or 12 or 13 or 14 or 15 or 0 or 1) (r is 3) and (w is 11 or 12 or 13 or 14 or 15 or 0 or 1 or 2) (r is 4) and (w is 12 or 13 or 14 or 15 or 0 or 1 or 2 or 3) (r is 5) and (w is 13 or 14 or 15 or 0 or 1 or 2 or 3 or 4) (r is 6) and (w is 14 or 15 or 0 or 1 or 2 or 3 or 4 or 5) (r is 7) and (w is 15 or 0 or 1 or 2 or 3 or 4 or 5 or 6) (r is 8) and (w is 0 or 1 or 2 or 3 or 4 or 5 or 6 or 7) (r is 9) and (w is 1 or 2 or 3 or 4 or 5 or 6 or 7 or 8) (r is 10) and (w is 2 or 3 or 4 or 5 or 6 or 7 or 8 or 9) (r is 11) and (w is 3 or 4 or 5 or 6 or 7 or 8 or 9 or 10) (r is 12) and (w is 4 or 5 or 6 or 7 or 8 or 9 or 10 or 11) (r is 13) and (w is 5 or 6 or 7 or 8 or 9 or 10 or 11 or 12) (r is 14) and (w is 6 or 7 or 8 or 9 or 10 or 11 or 12 or 13) (r is 15) and (w is 7 or 8 or 9 or 10 or 11 or 12 or 13 or 14) This is just logically what is needed, however because the counters are gray coded there will be a lot of minimization done, for example, if the gray states for both the read and write pointers were defined as the following: 0 = [0,0,0,0] 1 = [0,0,0,1] 2 = [0,0,1,1] 3 = [0,0,1,0] 4 = [0,1,1,0] 5 = [0,1,1,1] 6 = [0,1,0,1] 7 = [0,1,0,0] 8 = [1,1,0,0] 9 = [1,1,0,1] 10 = [1,1,1,1] 11= [1,1,1,0] 12= [1,0,1,0] 13= [1,0,1,1] 14= [1,0,0,1] 15= [1,0,0,0] then the first condition can be expressed as: (r is 0) and w3 I'm sure if you want a more 'fuzzy' indication of halffull that it would reduce the OR terms (if it's a Xilinx part you've maybe got HMAPs and FMAPs), but the above is worth chucking at a synthesizer just to see what it makes of it! I'd be interested in the results.... Regards, Mark. Remove NOSPAM_ from email address Dan Kuechle <dan_kuechle@i-tech.com> wrote in article <01bdcc8d$dad83760$1f38d926@dank.i-tech.com>... > Anybody out there got a good solution for a half full flag for a fifo? I > was planning on using Xilinx sync dual port ram to get a 16 deep fifo. The > write clk and read clk are app the same frequency (~53 mhz) but are from 2 > different xtal sources so are async to each other. > > My fifo basics are rusty...I've always used a full u/d counter to do this > in the past, but can't with this design due to the different clocks. I > know that when the read pointer = the write pointer the fifo is either full > or empty, but don't know what relationship indicates half full. Could > someone help me out? The flag does not need to be exact, and I can re-sync > to eliminate any glitches. Even a false half full indication would not > cause a problem as long as it happens right around the half full point. > > Thanks > Dan >Article: 11536
Hi, I intend to send messages from one fpga to another. These messages are really intended to go from/to the ISA bus to which my devices are attached. I thought about sending bit streams but since my goal is to have high speed communication I have decided to use eight channels and send bytes. Does anyone know of a simple (standard or otherwise) protocol that is usually used. Note that I can have my byte originating from RAM on the device or I can have it available in register. In any event, I want to be able to stream bytes across a parallel cable to another device. Gersham Jeffrey, ORNL.Article: 11537
I'm not sure which support Linux, but you can find a list of potential board vendors on The Programmable Logic Jump Station at http://www.optimagic.com/boards.html. Some vendors to look at include Virtual Computer Corporation, GigaOps, Annapolis Microsystems, NXM Design, TSI Telsys, Space Machines, MiroTech Microsystems, and probably a bunch that I missed. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- John Funnell wrote in message <35DD643A.FA@probablyndsuk.com>... >Hi, > >I'm looking to build a custom co-processor on an FPGA to speed up >algorithm simulation on a PC. With some simple pipelined and >parallelised arithmetic a large FPGA with fast clock should give >enourmous speedup. > >I know there are vendors who put a large Altera or Xilinx plus some >memory on a PCI card for such applications. Is there anyone out there >who knows of such a card with Linux support? > >Thanks in anticipation, > >John Funnell >Research Engineer >NDS Ltd.Article: 11538
Thank you to all who responded to my request for assistance on an efficient combinatoric (or is it "combinatoral"? "combinatorial"?) divide-by-three algorithm to be put in an FPGA. Your emails and postings were appreciated. KenArticle: 11539
benyamin@my-dejanews.com writes: > > I am having difficulty comparing this method of doing vector products to other > solutions. Here's what I have so far: (sizes are for fully parallel circuits, > and let K=length of vector, L=precision of coefficients, N=precision of > variables) > > Optimized Binary Tree (methodology above) Pros: Simple to contruct and > synthesize, directly computes vector product, easy parallelism trade-offs, > suited well for FPGAs, small in size. Cons: Maybe difficult to route Size: > loose upper bound: .5*KL - 1 additions in tree (depends on coeff. values. > For the example above K=8, L=4, so upper bound is 15 but we can get 10, a 1/3 > smaller). Calculating 11*A + 13+B would mean K=2, L=4, or that no more than 3 additions are required. I do not see how this could be done. Does your upper limit equation assume subtraction is permitted? Patrick KlingArticle: 11540
Mark Purcell wrote: > > You could do this by defining gray coded read and write pointers, then > combinatorially decoding the flag outputs from the gray coded states. Using > gray coding eliminates unfriendly glitches as only one bit changes per > operation per counter (as opposed to binary where the bits can transition > through unwanted states, and therefore produce erroneous flag decoding). this is what i was going to suggest too. however, if the gray code difference logic doesn't minimize well, you might try keeping 3 pointers around... eg two binary counters and one Gray counter. use the binary counters as your read/write pointers. use the Gray counter as a duplicate write pointer, sync'ed to the write clock. then resync the Gray counter to the read clock with another register. this will prevent async problems in the half-full flag. decode this register to binary and compare it (ie, do a binary subtract) against the read pointer. the difference will tell you how many entries are in the fifo (it may be off by one but that's ok because it's only a half-full indicator). you can also keep your read/write ptrs in Gray code but then you'll probably want to decode both ptrs into binary to do the subtract. doing the subtraction in the Gray code domain involves 2 parallel carry chains which FPGAs are not optimized for. i can give you a reference if you want one though. i use this trick to make histograms of FIFO depths. guy lemieuxArticle: 11541
Mark Purcell wrote: > > You could do this by defining gray coded read and write pointers, then > combinatorially decoding the flag outputs from the gray coded states. Using > gray coding eliminates unfriendly glitches as only one bit changes per > operation per counter (as opposed to binary where the bits can transition > through unwanted states, and therefore produce erroneous flag decoding). this is what i was going to suggest too. however, if the gray code difference logic doesn't minimize well, you might try keeping 3 pointers around... eg two binary counters and one Gray counter. use the binary counters as your read/write pointers. use the Gray counter as a duplicate write pointer, sync'ed to the write clock. then resync the Gray counter to the read clock with another register. this will prevent async problems in the half-full flag. decode this register to binary and compare it (ie, do a binary subtract) against the read pointer. the difference will tell you how many entries are in the fifo (it may be off by one but that's ok because it's only a half-full indicator). you can also keep your read/write ptrs in Gray code but then you'll probably want to decode both ptrs into binary to do the subtract. doing the subtraction in the Gray code domain involves 2 parallel carry chains which FPGAs are not optimized for. i can give you a reference if you want one though. i use this trick to make histograms of FIFO depths. guy lemieuxArticle: 11542
Check out http://www.macrotechsemi.com We can help you with the synthesis and also a low cost ASIC. Regards, Kash Johal kraemerm@my-dejanews.com wrote in article <6rbhl8$hpg$1@nnrp1.dejanews.com>... > Hi, > > some third party is currently making a 25kGates VHDL design for us. We plan > to make a few prototypes (20-50) with FPGAs and make an ASIC later on. As I > have some experience with Xilinx 3k and 4k devices, I asked them to map it to > Xilinx XC4062XL, which should have a sufficient size. > > For testing, they mapped a small design (1kG) and found that obviously no > optimization is done. It seems that each and every gate is mapped to a single > CLB. So we get a very high propagation delay (7-10 CLBs instead of just only > one) and of course a very poor CLB usage. Are we doing anything wrong? > B.t.w., the same design maps perfectly to an Altera device. Of course we want > to avoid (if possible) any special language elements for Xilinx, as we will > make an ASIC later on. Due to these problems I consider to use Altera > instead, but I must decide quickly as I wanted to tranfer my PCB to layout > until the end of this week. > > Any quick help is highly appreciated. > Thanks in advance! > > -- > Michael Kraemer > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum >Article: 11543
If you have a secured device, such as a GAL, PAL, microcontroller, and FPGA, with the contents of which you are interested in recovering and providing the contents are not copyrighted (or you are the copyright holder), we may be able to help you. We also have reader/analyzer for reading/analyzing various secured GAL's and PAL's. Please call: 1-404-228-1693 for further details.Article: 11544
John Funnell wrote: > I know there are vendors who put a large Altera or Xilinx plus some > memory on a PCI card for such applications. Is there anyone out there > who knows of such a card with Linux support? Annapolis Micro Systems, Inc. (http://www.annapmicro.com) has boards like this. The WILD-ONE(tm) and WILDFORCE(tm) boards have two and five FPGA's, respectively, which can vary in size from (maybe) 4020 to 4062xl. Each FPGA has an option of attached RAM, as well. I believe the Linux drivers have just been finished up, and work as loadable kernel modules. --JimArticle: 11545
I am Niraj Patel working in 100% export oriented company in India. We believe in Co:Optition not competition. We are in the field of software and started new branch in which we are developing synthesizable core using Verilog. To make our core silicon proven in FPGA we are searching for proper direction. I will be thankful if anybody can guide me. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11546
Guy Gerard Lemieux <lemieux@eecg.toronto.edu> wrote: > Mark Purcell wrote: >> >> You could do this by defining gray coded read and write pointers, then >> combinatorially decoding the flag outputs from the gray coded states. Using >> gray coding eliminates unfriendly glitches as only one bit changes per >> operation per counter (as opposed to binary where the bits can transition >> through unwanted states, and therefore produce erroneous flag decoding). > > this is what i was going to suggest too. > > however, if the gray code difference logic > doesn't minimize well, you might try keeping > 3 pointers around... eg two binary counters > and one Gray counter. > you can also keep your read/write ptrs in Gray code > but then you'll probably want to decode both ptrs into > binary to do the subtract. doing the subtraction > in the Gray code domain involves 2 parallel carry chains > which FPGAs are not optimized for. i can give you > a reference if you want one though. I chose a brute-force method when I needed a similar flag; I simply used a 1-bit ROM (Xilinx macro from logiblox) to generate the flag. The input to the ROM (the "address") was the two Gray-coded pointers, synchronized to the same clock domain, appended together into a 2N field. I make no claims of area efficiency, but it was quick and easy, and ran fast (100MHz, the target frequency). Thanks, -- Bill Warner Silicon Graphics wtw@sgi.comArticle: 11547
check at http://www.associatedpro.com G. R. Jeffrey wrote: > I am new to the fpga world. I have some Altera flex10k devices that I > want to use to implement a routing protocol. > > Does anyone know where I can get some (simple) example codes that use > the ISA bus to interact with fpga/cpld devices. I spent all of > yesterday, unsuccessfully, trying to write/read to/from ram on a device. > > Also, is there a web site that explains the ISA bus signals? > > Thanks, > > Gersham Jeffrey. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 11548
Check at http://www.associatedpro.com for starter kits niraj0703@my-dejanews.com wrote: > I am Niraj Patel working in 100% export oriented company in India. We believe > in Co:Optition not competition. We are in the field of software and started > new branch in which we are developing synthesizable core using Verilog. To > make our core silicon proven in FPGA we are searching for proper direction. > > I will be thankful if anybody can guide me. > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 11549
watm wrote: > I'm design a WATM network and i have to modulate the signal to > transmit using infrared transceivers. I thought using 4PPM : > > [Image] > > You can find more details at: > http://www.chips.ibm.com/products/infrared/brdsms/brdsms10.htm > > Thanks in advance, > Rui Pinto This is really a very simple circuit, at least in concept. The two bits input needs to be loaded into a two bit register. If it is serial to start with, use a two bit shift register. The output of this two bit register will be used as the load data input of a two bit data counter. A second two bit timing counter will provide four clock ticks for each 4 clock load/count cycle. The timing counter will provide a load pulse once every 4 clock cycles. The data counter will count down on all ticks other than the load clock tick. When the counter is equal to zero, a one is output to the 4 PPM data output. At all other times a zero is output. If you need some dead space in between samples you need to make the timing counter have more bits and let it count for more clock cycles. Otherwise this should cover everything except for synchonization with your incoming data. That is a little hard to explain how to do. -- Rick Collins redsp@XYusa.net remove the XY to email me.
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