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ACTEL's new SX family seems to be the fastest, at least in terms of maximum clock frequency of 320Mhz. Willem Steven K. Knapp <sknapp@optimagic.com> wrote in article <6qsevp$ehv@sjx-ixn2.ix.netcom.com>... > Xilinx has a document, now about 18 months old, that has some FFT > comparisons. It's an Acrobat document at > http://www.xilinx.com/appnotes/fft.pdf. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > Thomas Focke wrote in message <35D1AFFE.F6371A4E@himh1.hi.bosch.de>... > >I'm looking for a comparison regarding achievable FFT-speed between > >FPGA vs. DSP-solutions. > >For instance: DSP TMS C6x can manage a 1024 point-FFT in 104 µs. > >Which FPGA can achieve which speed? > >Is there a comprehensive table in the web? > > > >Who can help me? > > > >Thomas > > >Article: 11626
The Programmable Logic Jump Station maintains links to free or low-cost software for programmable logic design at http://www.optimagic.com/lowcost.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- tigerz@my-dejanews.com wrote in message <6s1rpl$3p4$1@nnrp1.dejanews.com>... >Hello, > >I would like to learn about CPLD/FPGA programing. I found that there are two >low cost tool from Cypress and Xilinx for $95. Can someone give me suggestion >on which one to purchase and why? Any other low cost alternative? Thanks in >advance for feedback. > >Tiger > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11627
This is a multi-part message in MIME format. --------------97C0505C0132F2C034BC0FDF Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Joel Kolstad wrote: > I've been trying to use busses in Foundation's schematic capture program > (Active CAD "lite" by Aldec, I believe), and I have a question. If I > instantiate some component for the Xilinx unified component libraries, say, > a 16 bit counter, and I only want to look at the lower 12 bits of that > output, how can I do it using a bus? If I just declare a bus with 12 > members and connect it to the counter's output, it'll connect Output[15:4] > to my Bus[11:0] given the "left to right" bus pin to bus terminal mapping > rule that the on-line help discusses. (I wish their on-line help gave a few > more examples... they seem to give examples of exactly the kind of > connection I'm trying NOT to make...) > > I'm thinking I need to label the bus connection as something like > garbage[3:0],Bus[11:0] so that the upper four bits just head off into > hyperspace and I get the 12 lowermost bits that I wanted. However, I'm sure > the software is going to complain if I start creating these orphan nets with > names like "garbade". > No need to make garbage!Take your standard counter, CB16CE or whatever, attach Bus[15:0] to theoutput. Elsewhere, where you need only the 12 lower bits, attach Bus[11:0]. Connections are made by name, bus taps are just a (some think) pretty graphical enhancement. The system will automatically trim off the circuitry associated with the upper 4 bits of the counter if they don't connect to anything else. I think the mapping report includes the trimmed logic report of unused logic in the schematic that has been trimmed away prior to Place and Route. > Any ideas? The Xilinx help line guy was trying to tell me that you have to > take that bus and draw 12 bus taps to get what I want, but I had a real hard > time believing that. He's still checking into it however. > > Thanks a lot. > > ---Joel Kolstad > Joel.Kolstad@USA.Net --------------97C0505C0132F2C034BC0FDF Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John L. Smith n: Smith;John L. org: Visicom Imaging Products adr: 1 Burlington Woods;;;Burlington;MA;01803;USA email;internet: jsmith@visicom.com title: Principal Engineer tel;work: 781-221-6700 tel;fax: 781-221-6777 x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------97C0505C0132F2C034BC0FDF--Article: 11628
Try the Altera MaxPlus II stuff too. Available from the website : www.altera.com. This'll give you schematic entry, AHDL (Altera Hardware Description Language), simulation, fitting and programming. It supports both FLEX (SRAM based 'FPGAlike') and MAX (EEPROM CPLDs) devices - the lowest of each of the families, 'cept it'll support all the MAX 7K stuff (Altera's most successful EEPROM family). It's the latest version too, 9.01 and includes some funky parameterisable modules (mutlipliers, counters etc.) Give it a go. I did and now I support the stuff!!! Alex Beynon Altera FAE Ambar Cascom (UK) abeynon@dial.pipex.com tigerz@my-dejanews.com wrote in message <6s1rpl$3p4$1@nnrp1.dejanews.com>... >Hello, > >I would like to learn about CPLD/FPGA programing. I found that there are two >low cost tool from Cypress and Xilinx for $95. Can someone give me suggestion >on which one to purchase and why? Any other low cost alternative? Thanks in >advance for feedback. > >Tiger > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11629
Ray Andraka <no_spam_randraka@ids.net> wrote in article <35E30293.8506826C@ids.net>... > > > Guy Gerard Lemieux wrote: > > > you can also keep your read/write ptrs in Gray code > > but then you'll probably want to decode both ptrs into > > binary to do the subtract. doing the subtraction > > in the Gray code domain involves 2 parallel carry chains > > which FPGAs are not optimized for. i can give you > > a reference if you want one though. > > > > You can get around this by using a composite counter that has a 2 bit gray code > counter for the LSBs and whatever counter is convenient for the remaining bits. > The decode is gated by the gray code counter so that it is only valid on a count > that is away from the count enable of the upper counter. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > I don't follow this, could you explain? I'm probably missing something, but to get an accurate half full flag condition I think you need to have a stable, and valid, high order count. I don't think it's possible to simply gate every fourth write pointer state with the half full flag as this will still generate a false half full state when it's three quarters full (i.e. it will indicate 'not half full'). Sampling an asynchronous binary counter can result in false sample values, and so the whole of the counter needs to be gray coded to get valid samples IMO before the subtraction can be done. Please tell me I'm missing something.... Mark. Remove NOSPAM_ from email addressArticle: 11630
Hey Rui, Sorry for the delay getting back to you. Info on timing constraints can be found using the Dynatext browser. Its really a matter of specifying the required frequency or period within each clock environment and domain. You only have source supplying clock to all your FFs.... right? If not, and you can't always, you need to architect transition logic between your clock domains. No amount of timespecing will really help. Let me know if you need more details. -- Ed McCauley Bottom Line Technologies Inc. http://www.bltinc.com Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 watm wrote: > > Thanks for the help. > > The problem was not the pinouts, i checked and everything was normal. Ed > MacCauley was right about the timing goals, when i implemented the design > using the "Balanced" optimization mode, the expected results came up. > However my FPGA is almost full and the only possible option in the > optimization mode is "Area", because otherwise the design don't fit in the > FPGA. > > My question is : how do i specify the time constraints in the Xilinx ? > What values do i specify ? > > Thanks in advance, > Rui Pinto > > PS: If someone knows where i can order a FPGA XC4008/10, to be delivered as > soon as possible, i would also appreciated. >Article: 11631
Hello Thanks everyone for replay, especially Joel Kolstad for the long and useful comparision between Cypress and Xilinx package. Some respond about FREE packages from Altera, Vantis, and some other. These free packages are good but I think I will go for either Cypress or Xilinx because of their support for VHDL, FSM, schematic entry and all integrate into one package. Tiger > The replies you've gotten so far suggest free software. This is certainly > worth a look, given the price, but as far as I'm aware the only thing you'll > get for free is schematic entry, ABEL entry, and JEDEC-style simulation. > This stuff is fun to play with, but if you have ambitions of doing serious > FPGA designs, you'd be much better off spending that $100. > > The $100 you send to Xilinx gets you the most compehensive package. You get > full simulation capabilities, schematic entry, state machine entry, and > logic synthesis for all of Xilinx's CPLDs and the more modest FPGAs. The > Xilinx university software is version 1.3, which is unfortunate since > version 1.4 and above include VHDL synthesis as well. It is legal to > install 1.4 with your 1.3 license but you need to find someone with the CDs. > Xilinx is going to upgrade all those student copies to 1.5 later this year. > They're probably holding off on upgrading people to 1.4 because the VHDL > synthesis (provided by Synopsys' FPGA Express) isn't very well integrated > into the design flow yet. > > The $100 you send to Cypress will get you a VHDL synthesis package today. > And a decent book. And, um... that's about it. There is a JEDEC-style > simulator, but it's not really all that useful. The book is useful for > learning VHDL, whereas the book that comes with the Xilinx stuff is more an > introduction to digital design techniques that happens use ABEL (primarily) > as strictly a means to an end. The guy who wrote that book has translated > all of the ABEL into VHDL lately and has it on his web site, however. Note > that the Cypress $100 package includes software updates for awhile; you can > get the same package without the update service for <$50 at a bookstore; the > software is bundled with the book. > > If you have to get just one, in general I'd go for the Xilinx software. > You'll get VHDL no later than the end of this year. If you really want to > learn VHDL, the Cypress package is better to start with. > > One other thing I can think to mention is that Xilinx doesn't support the > student editions of the software; you're supposed to go bug your instructor > (which is unfortunate in a way, since not all instructors know much more > about the software than the students do...). On the other hand, Cypress > doesn't designate their software as a student version, so while you're > pretty much stuck e-mailing them, you can get them to answer any question > you have. > > ---Joel Kolstad > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11632
Catalin wrote: > > One way to lower the jitter is to increase the 1KHz reference. If you still > want the 1KHz resolution your options are: > > 1. Fractional-N techniques (this requires a DAC). Basicaly, a digital > phase accumulator is used to inject a saw-tooth like waveform into the > PLL loop. A technique introduced by HP (I think) about twenty years ago. > > 2. Divide both the VCO output and the reference with variable (and much > smaller) numbers. For example (I am assuming a 10MHz reference > frequency): > - for 9.5MHz use 19/20 instead of 9500/10000 > - for 9.673MHz use 148/153 instead of 9673/10000 and you will get > 9.673203MHz, etc. > Of course there will be frequencies that cannot be approximated by a > fraction of small numbers, for example 9.501MHz. For these just use a > second (or even a third) reference frequency which is not in a small > harmonic ratio to 10MHz. The ratios can be easily computed on the fly > with a modified Euclid algorithm (which can also be implemented in an > FPGA) or they can be precomputed and stored in a ROM table (which might > also fit in an FPGA). > > 3. Look at the Cypress part ICD2061A (www.cypress.com). It might do > exactly what you want. It is a programmable dual clock PLL generator > used in graphics applications. It has a very wide range and I believe low > jitter. Doesn't require any external components and is programmed trough > a simple serial interface. > > Catalin Baetoniu > > Mirko Kovacevic wrote: > > > Hi Detlef, > > > > Your main problem is the big dividing ratio (10,000). For these dividing > > ratios you need reference clock with very, very low jitter. Your output > > jitter will be crystal oscillator jitter multiplied with 10,000 plus > > additional jitter of the VCO itself. Try to keep the VCO power supply as > > clean as possible. > > > > Regards, > > Mirko I tried to analyse this problem a few months ago, but because I know nothing about PLL operation, I was not able to convince anyone that my solution would work. I needed to produce a stable clock over a range of 0.5 MHz to 50 MHz. I did not like the dual divisor approach that you outline above. It will give you good resolution, but as you indicated, the resolution is not evenly distributed and it is not straight forward to select the two divisors. I was more interested in using a digital NCO to produce a finely tunable reference over a range of 2:1. Then my PLL output could vary over the same range with high precision and scaled down to the required freq by counters. The problem with the NCO is that there is an output jitter equal to the period of the master clock. Everyone seems to make the assumption that jitter in the reference clock will produce jitter in the output clock of a PLL. But all PLL circuits have a low pass filter on the output of the phase detector. This is where my lack of knowledge comes in. It would seem to me that a high speed jitter in the reference would be filtered out by this low pass filter, or at least attenuated. But an earlier poster indicated that a lower frequency input to the phase comparator produces higher jitter. So I am not sure just what effect a low freq filter would have. It might reduce the low freq stability while removing the high speed jitter caused by the reference NCO. Anyone understand this stuff enough to make a comment? If I get the time, I might try to prototype this circuit and test it. I always did like working in the lab! -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11633
Currently I use both Galileo 4.2.2 and Synplify. I've tested FPGAexpress in the past too. All my experience tells me that synplify generates the fastest code (with some exceptions), the smallest code and has the fastest execution time. Galileo is the second and FPGAexpress is a close third. I had one problem with Synplify working with a very large module which was a humonguos decoder for a microcontroller. Synplify gave bigger results than GE 4.2.2. But alas Exemplar managed catch up with Synplify with Leonardo Spectrum. Spectrum is almost as bad as Synplify for this module. Granted the design of this module is not well suited to FPGAs but there is no reason to do worse than GE 4.2.2. I like Synplify a lot. For the overall microcontroller design it still gives the smallest area despite the problems I am having with it. No EDA tool is perfect and my choice is Synplify. allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote: >We recently compared the Foundation / Synopsys sythesiser against >Galileo Extreme 4.2.2, for a number of existing VHDL projects in the >5k - 20k gate range which had been synthesised with Galileo in the >past. >For the designs that the Synopsys tools were able to compile, it >produced results that were about 20% bigger. >There were a number of designs that required simple modifications to >compile, and some that (would have) required major modifications. >[ Things like generic parameters being 2 diminsional arrays, vhdl'93, >etc, caused problems. ] > >I guess you get what you pay for. > >I hear that Synplify is about the same as Galileo, but I have not >independently confirmed this. muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 11634
This is a multi-part message in MIME format. --------------F589905CC1C878315BDC05C4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, I been following the FFT postings and have some comments. Xilinx now have a new family of FFTs for the XC4000XL architecture. Here is the performance of the 1024-pt Core. N = 1024 16b complex data (16b for each of the real and imaginary components of the input data and result) fixed-point arithmetic transform time @ 60 MHz = 86 microseconds 1500 CLBs -- Dr Chris Dick Senior Systems Engineer Xilinx Inc 2100 Logic Drive San Jose CA 95124 Phone: (408) 879 5377 Fax: (408) 377 3259 -- Dr Chris Dick Senior Systems Engineer Xilinx Inc 2100 Logic Drive San Jose CA 95124 Phone: (408) 879 5377 Fax: (408) 377 3259 --------------F589905CC1C878315BDC05C4 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dr Chris Dick Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Dr Chris Dick n: Dick;Dr Chris org: Xilinx email;internet: chrisd@xilinx.com title: Senior Systems Engineer note;quoted-printable:Phone: (408) 879 5377=0D=0A= Fax: (408) 377 3259=0D=0A= Pager: (408) 619 0102=0D=0A= x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------F589905CC1C878315BDC05C4--Article: 11635
Reza, I evaluated Exemplar's Leonardo, Synplicity's Synplify and Synopsis' FPGA Express about a year ago and found Synplify to be better overall than its competitors. In some areas, like speed of synthesis results, it was much faster than the others. One thing I didn't like about FPGA Express is that it didn't (and still doesn't I think) support 1076-1993. In terms of design speed and area, Synplify still produced better results, although the results were not miraculously higher; however, 10% can sometimes save your butt, and so I consider 10% or more as significant. It is a year later, and I haven't recently done another trade study to determine who is best. I am still using Synplify and it meets all of my expectations when used on Altera and Xilinx designs. It hasn't let me down, and the comments made by some of the other respondents to your posting seem to indicate that I don't need to waste my time doing the trade study again. Good luck with your decision and keep the Newsgroup posted on your results. Thanks. -Simon Ramirez Consultant Reza Bohrani wrote in message <35e2a49f.0@grendel.df.lth.se>... >Which pc-based synthesis tool is the best on the market. I have heard of >Synplify; is that a good tool or should I go for Leonardo or are there other >good tools? > >Article: 11636
This is a multi-part message in MIME format. --------------A3F2358190E7E77B7587D157 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Does anybody have a reference that discusses some or all of the FPGA vendor's equations for determining gate count? The only one I've found so far is for Altera, who say that each of their LE's equates to 12 usable gates. I've determined that this equates their 100,000 gate part to having only 59,904 logic gates (4992 LE x 12), unless you use the embedded RAM blocks. I'd like to do similar reality checks on the other vendors, namely Xilinx and Actel, but the more, the merrier. --------------A3F2358190E7E77B7587D157 Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Bryn Wolfe at TRACLabs Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Bryn Wolfe at TRACLabs n: Wolfe at TRACLabs;Bryn org: Metrica TRACLabs adr: 1012 Hercules Drive;;;Houston;TX;77058-2722;USA email;internet: bwolfe@traclabs.com title: Robotics Engineer tel;work: 281-461-7886 tel;fax: 281-461-9550 x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------A3F2358190E7E77B7587D157--Article: 11637
In article <oFw5cGAzVl41EwYc@jmwa.demon.co.uk>, John Woodgate
<jmw@jmwa.demon.co.uk> writes
>In article <35e18082.1903959@news.gv.net>, Jim Weir <jim@rst-engr.com>
>writes
>>
>>->Summary
>>->^^^^^^^
>>->In reconfigurable hardware, the behaviours and interconnections of the
>>->constituent electronic primitives can be repeatedly changed. Artificial
>>->evolution can automatically derive a configuration causing the system to
>>->exhibit a pre-specified desired behaviour. A circuit's evolutionary
>>
>>Oh BOY. If the summary is this readable, I just can't WAIT to curl up with
>>this sucker some cold evening when I can't sleep. {;-)
>>
>>Jim
>
>Yes. I want to know whether this evolution proceeds only by random
>mutations or has electronic sex been developed?
Oh, yes, less funny than it might appear (Spielverderber? Ich?). In
fact, genetic algorithms for 'circuit' design - and that might be the
struts on a pylon or the components of a filter - often use
'chromosomes' to encode circuit properties, and mechanisms for
recombining as well as mutation to create new ones.
As it happens, I've always found the asexual algorithms much more
tractable!
Kendall Castor-Perry
"What problem could there be so hard as not to dissolve
in a sufficiently strong solution of nonsense?" - Stove
For email, use my *real* email address:
kendallcp at compuserve dot com
Article: 11638No, you didn't miss a thing. I did. I was recalling a design I did a while back but was to lazy to go look up. Turns out that design I was thinking of was synchronous and the gray code counter was on the 2 msbs in a scheme to make the full and empty flags. The half full in that case was relatively trivial since it was synchronous. I must be getting old, my memory ain't what it once was! Sorry for any sleep I might have caused you to lose. Basically, what I was trying to put forth was a half baked scheme in which the half full flag would depend on the relative positions of the upper counters, but would only be allowed to change when neither lower counter was enabling the corresponding upper counter. This would result in a half full trip position that floats around a little. The problem with that scheme is that if one counter was sitting at the no-decode state, the half full flag would never get set/reset as the other counter breezed through the half full position. Mark Purcell wrote: > I don't follow this, could you explain? I'm probably missing something, but > to get an accurate half full flag condition I think you need to have a > stable, and valid, high order count. I don't think it's possible to simply > gate every fourth write pointer state with the half full flag as this will > still generate a false half full state when it's three quarters full (i.e. > it will indicate 'not half full'). Sampling an asynchronous binary counter > can result in false sample values, and so the whole of the counter needs to > be gray coded to get valid samples IMO before the subtraction can be done. > Please tell me I'm missing something.... -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11639
Of course it is not like that Altera doesn't accept this. If you look at their data sheets, this is exactly what they say; a 10k100 is from 60k to 130k gates. And it makes sense. Most of the systems need some memory and logic gate count is some measure of area not only usable gate count. Of course the density of memory is much greater than random logic so you have to adjust your multipliers to get a nice estimate of the area. This seems to be true for both cell-based asic and fpga. Bryn Wolfe <bwolfe@traclabs.com> wrote: >Does anybody have a reference that discusses some or all of the FPGA >vendor's equations for determining gate count? The only one I've found >so far is for Altera, who say that each of their LE's equates to 12 >usable gates. I've determined that this equates their 100,000 gate part >to having only 59,904 logic gates (4992 LE x 12), unless you use the >embedded RAM blocks. I'd like to do similar reality checks on the other >vendors, namely Xilinx and Actel, but the more, the merrier. muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 11640
Hi. I am looking for the lookup table method to accelerate the multiplication and division. How can I make effective tables for them? I will wait for precious advice. Thanks.Article: 11641
One slight correction. Even in the F1.5 release Synopsys is not included in the Base ie $95 package. (I do not know for sure if this is ture of the "Student" version but I suspect it is.) (What is included in the $95 box though does make a nice development system for smaller (10K gates, 40K Spartan)). Synopsys is not in the habit of giving away their software, they need a slice for each Foundation with VHDL sold by Xilinx. So a Base F1.5 system with Synopsys FPGA Express for Xilinx is a bit (Several hundred $) more. Have FUN!! Nick Joel Kolstad wrote: > tigerz@my-dejanews.com wrote in message <6s1rpl$3p4$1@nnrp1.dejanews.com>... > >Hello, > > > >I would like to learn about CPLD/FPGA programing. I found that there are > two > >low cost tool from Cypress and Xilinx for $95. Can someone give me > suggestion > >on which one to purchase and why? Any other low cost alternative? Thanks > in > >advance for feedback. > > The replies you've gotten so far suggest free software. This is certainly > worth a look, given the price, but as far as I'm aware the only thing you'll > get for free is schematic entry, ABEL entry, and JEDEC-style simulation. > This stuff is fun to play with, but if you have ambitions of doing serious > FPGA designs, you'd be much better off spending that $100. > > The $100 you send to Xilinx gets you the most compehensive package. You get > full simulation capabilities, schematic entry, state machine entry, and > logic synthesis for all of Xilinx's CPLDs and the more modest FPGAs. The > Xilinx university software is version 1.3, which is unfortunate since > version 1.4 and above include VHDL synthesis as well. It is legal to > install 1.4 with your 1.3 license but you need to find someone with the CDs. > Xilinx is going to upgrade all those student copies to 1.5 later this year. > They're probably holding off on upgrading people to 1.4 because the VHDL > synthesis (provided by Synopsys' FPGA Express) isn't very well integrated > into the design flow yet. > > The $100 you send to Cypress will get you a VHDL synthesis package today. > And a decent book. And, um... that's about it. There is a JEDEC-style > simulator, but it's not really all that useful. The book is useful for > learning VHDL, whereas the book that comes with the Xilinx stuff is more an > introduction to digital design techniques that happens use ABEL (primarily) > as strictly a means to an end. The guy who wrote that book has translated > all of the ABEL into VHDL lately and has it on his web site, however. Note > that the Cypress $100 package includes software updates for awhile; you can > get the same package without the update service for <$50 at a bookstore; the > software is bundled with the book. > > If you have to get just one, in general I'd go for the Xilinx software. > You'll get VHDL no later than the end of this year. If you really want to > learn VHDL, the Cypress package is better to start with. > > One other thing I can think to mention is that Xilinx doesn't support the > student editions of the software; you're supposed to go bug your instructor > (which is unfortunate in a way, since not all instructors know much more > about the software than the students do...). On the other hand, Cypress > doesn't designate their software as a student version, so while you're > pretty much stuck e-mailing them, you can get them to answer any question > you have. > > ---Joel KolstadArticle: 11642
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I just started playing with Synopsys FPGA-Express.
Now there is a very user friendly user-interface, however, what I lack
is that there does not seem to be some kind of script-interface.
For FPGA-Compiler and Design-Compiler, I am used to create some kind
of script file (.dc) which can be used to run a job in batch mode.
Does anyone know (and can explain me) how to run FPGA-Express jobs in
batch mode (in the Unix environment) ?
--
Koenraad SCHELFHOUT
Alcatel Telecom
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VA21 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 88 \ / /
mailto:koenraad.schelfhout@alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
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<TT></TT>
<P><TT>I just started playing with Synopsys FPGA-Express.</TT>
<BR><TT>Now there is a very user friendly user-interface, however, what
I lack</TT>
<BR><TT>is that there does not seem to be some kind of script-interface.</TT><TT></TT>
<P><TT>For FPGA-Compiler and Design-Compiler, I am used to create some
kind</TT>
<BR><TT>of script file (.dc) which can be used to run a job in batch mode.</TT>
<BR><TT>Does anyone know (and can explain me) how to run FPGA-Express jobs
in</TT>
<BR><TT>batch mode (in the Unix environment) ?</TT>
<BR><TT></TT>
<PRE>--
Koenraad SCHELFHOUT
Alcatel Telecom
Switching Systems Division <A HREF="http://www.alcatel.com/">http://www.alcatel.com/</A>
Microelectronics Department - VA21 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 88 \ / /
<A HREF="mailto:koenraad.schelfhout@alcatel.be">mailto:koenraad.schelfhout@alcatel.be</A> \ / /
_____________________________________________\ / /______
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Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium</PRE>
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Article: 11643Reza, You have come to the right forum asking this question. The reason is that this forum is generally more objective in answering your question than let's say, the distributors and silicon reps that come knocking on your door. Their job is to get you to go with the product(s) they sell, regardless of what you really need. Everyone is "steerable" toward certain products, and not being aware of FPGAs makes you more steerable. When it comes to engineers' opinions about FPGAs (and other products), they generally try to steer you toward something that they have worked with and are knowledgeable about. This is normal, because we feel comfortable with what we know. One of your respondents, Ray Andraka, gave a pretty picture on the wonderful world of FPGAs. He mentioned price, learning curve, tools, and gave you an idea of what the Altera, Xilinx, Atmel, Actel and QuickLogic architectures are geared toward. One thing I really prize is support. FPGAs can be very complicated at times, and support from the field or factory can make a big difference. The problem with support is that it varies from location to location. The field teams are comprised of engineers that vary in experience and quality, so when talking to the FAEs, try to make a good judgment on how well they know what they're talking about and how often you will see them. Some you will see as long as you are still trying to make a decision. Others you will still see after you make your decision. I try to determine who are the latter, and I go with them. Once you decide, try to use the factory for support by calling their hotlines. In general, the factories have good support. The people answering the phones are suppose to be good at getting you answers from the experts located deep inside the factory (next cube over?). How well they do their job is determined by how fast they get the answers and how good the answers are. Some of these people really hustle, and you tend to favor some of them. Now I am assuming that you will get into complicated designs and need some of this support. Many designs go well and you will not need the support that I am describing. Most engineers I know getting into FPGA design start out using smaller devices with designs that are manageable locally or within your company. And finally the best advice I can give you is "ask a lot of questions!" Good luck. -Simon Ramirez Reza Bohrani wrote in message <35e2a40d.0@grendel.df.lth.se>... >I am new to to world of FPGA and would like to now which vendor to choose. >We have Actel, Altera, Xilinx, Lucent ... and many more. Can anyone please >tell me which one is the cheapest, the "best"? >Sincerely >Reza > >Article: 11644
Gordon, I agree with the rest. I think it sounds like "precise, scientific, obfuscated bullshit." Of course, it's academic. -Simon Ramirez Gordon Coulson McNaughton wrote in message <6s0clk$268$1@nntp.Stanford.EDU>... >A moment of your time please, Tom... > >Tom Kean (tom@algotronix.com) wrote: >: Mike McCarty wrote: >: > )->In reconfigurable hardware, the behaviours and interconnections of the >: > )->constituent electronic primitives can be repeatedly changed. Artificial >: > )->evolution can automatically derive a configuration causing the system to >: > )->exhibit a pre-specified desired behaviour. A circuit's evolutionary > >[snip] > >: > Let me translate this little bit into English. >: > >: > Hardware which can be changed can be changed more than once. It >: > is sometimes possible to make the hardware configure itself. > >[snip] > >: <FLAME> >: Actually, its not 'obfuscated bullshit' its precise scientific english: you >: just have to turn off the TV, put down your beer and engage your brain >: before reading it. > >I enjoy drinking beer. I also enjoy thinking. Are the two mutually exclusive? >Most of my friends are philosophical drunks. ;) > >Actually, the summary is obfuscated. That's not necessarily bad, that >just happens to be a side-effect of the type of summary being written: a >dense, high information-per-sentence paragraph that attempts to explain a >general concept (which takes an entire book to fully describe, or so one >infers) in a short amount of space -- hence, a summary of the concept. In >order to explain such a wide concept in precise terms in a short summary, >dense language is used which must be read carefully. Obfuscation (as webster >says, "to make obscure") is not the purpose of such language, rather it is a >side effect of the concept-condensing process. > >This is not the only kind of summary which could have been written. It was >written thoughtfully and deliberately. Alternatively it could have been a >topical overview of the specific discussions within the text, etc. However, >the author of the summary believed that this sort of dense conceptual >specification would engage people who would be interested in reading the book. >The summary is obviously not bullshit, since it imparts very precise and >accurate information to the people who extract it. > >I sincerely hope that your flame against anyone not willing to extract that >information was just a knee-jerk reaction (careful with those, now). There >was a pointed comment that the summary could have be written in a more >accessible fashion: you disagree (maybe the book itself is not accessible, >and such a summary would be misleading?). Fine, disagree, but don't >automatically light up a blowtorch (care with those, too!). > >: For example: >: >: 'Hardware that can be changed can be changed more than once' FALSE >: what about fuse technologies? The original text does not make this claim. > >The original text (as quoted by my newsreader, tin) says: > "In reconfigurable hardware, the behaviours and interconnections of > the constituent electronic primitives can be repeatedly changed." > ^^^^^^^^^^ >The use of the word "repeatedly" implies that the hardware can be changed >more than once. It may be false to infer that the *same* behavior or >connection can be changed more than once, but it is very clear that the >hardware in general can be. Do you disagree with this interpretation? > >: 'It is sometimes possible to make the hardware configure itself' >: The text does not say this either - what it says is that a configuration >: can be derived from artificial evolution. > >From the quoted portion of the message I saw, I would agree. > >It is interesting to note that the summary uses the phrase "a circuit's >evolutionary..." If this refers to the evolutionary capabilities of the >entire system in redesigning a specific circuit, you are right. > >If this refers to the *physical* circuit, stating that the *physical* hardware >circuit(ry) has evolutionary capabilities (outside of the context of a >surrounding system), then one would assume that the circuit has the ability >to modify itself (since it can evolve outside of a system, when there is >nothing else to modify it!). > >: </FLAME> > ></rebuttal> > >: Tom. > >With respect, Gordon. > >------------------------------------------------------------------ >Common sense and a sense of humor are the same thing, moving at >different speeds. A sense of humor is just common sense, dancing. > -- Clive JamesArticle: 11645
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--
Koenraad SCHELFHOUT
Alcatel Telecom
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VA21 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 88 \ / /
mailto:koenraad.schelfhout@alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
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Article: 11648Hello, I'm looking for xilinx tool, foundation. If any one have that tool(evaluation version, OK), please post the tool. thank youArticle: 11649
On 24 Aug 1998 02:28:59 GMT, adrianth@cogs.susx.ac.uk (Adrian Thompson) wrote: And while we're kicking Adrian... :) >A series of experiments is used to explore the >practicalities, culminating in a simple but non-trivial application. The >circuits may seem bizarre, but are highly efficient in their use of silicon. Not to mention: >it is shown that evolution can produce `bizarre but useful' >circuits, beyond the scope of conventional design. Simple, yes, bizarre, certainly, highly efficient use of silicon, dream on. The circuits might be useful if they were correctly designed by a competent engineer. What's bizarre is that real genetic circuits are large, and very flakey, and yet are still described as highly efficient or useful. Here's an idea for another Phd thesis. Simulate a billion monkeys with a billion typewriters, with their output being selected and reprocessed by a genetic algorithm, in an attempt to generate a new Shakespeare sonnet. In another corner of the lab, put Shakespeare in front of a desk with a pen and paper. The monkeys' output may well be "beyond the scope of conventional design". But which sonnet do you think is going to be more readable? Evan
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