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On 3 Jan 1997 01:18:27 GMT, dando@phish.nether.net (Mann`y) wrote: >Do any of you know of a USB host interface (UHCI) design available for >an FPGA (any vendor will do)? Lucent do, but it comes as part of Silicon Suite which is a standard cell tool with building block libraries offering PCI, USB, 10/100, ATM, Phy's, Clock recovery, etc. etc. as synthesizable blocks, and hard macros. All pure digital blocks are supported for prototyping using ORCA.Article: 4951
On Fri, 3 Jan 1997 14:50:11 +0000, Paul Walker <paul@walker.demon.co.uk> wrote: >Altera's PDN9625, dated 19 December 1996, announces last order and >delivery dates for the FX880 and 8160 devices (30 June, 97 and 98 >respectively). >No apology (or cash) is offered for apparently causing esisting >customers to re lay out their PCBs to use a different device. >Between now and June 98 gives Altera ample time to produce such a family >of devices. Maybe, but I heard that Intel were a little bit coy when asked for the figures re: manufacturing cost when Altera bought it. That die size sure is big. Maybe the EOL argument is more like "Enough Of Losing money"? But Altera having yield problems? No, I can't believe it StuartArticle: 4952
Hi! This is the 1st time I'm using an Altera device in my circuit, and it won't boot. The device is an EPF8282ALC84-4, the nS/P, MSEL0 & 1 pins decode APU configuration, and it should read the configuration data from a 27512 EPROM. I connected all the configuration pins according to the AN33 paper of Altera, except ADD16 & ADD17, they are left NC. The symptoms are the following. The nSTATUS pin goes high after RESET, the RDCLK pin ticks continously and the CONF_DONE pin is stucked at GND. The address lines count endlessly like a counter, and the device doesn't come out of this state. Have anyone encountered similar problems? I would appreciate any hint. (All signals seem to be fine digital, so there mustn't be any electrical failure. I have experience with PLD's and uControllers, just my 1st attempt with FPGA's failed.) Thanx in advance ! ***************************** Botond Kardos kardos@mail.matav.hu phone/fax: (36 1) 268-0934Article: 4953
Hello, I'm having a problem which Xilinx has not been able to crack. Environment: NT 4.0 server 95 client Xilinx software on network drive VIEWlogic/Xilinx project files on network drive Problem: wir2xnf cannot open the wir files on the network drive. If I move the wir files to the C: drive, wir2xnf runs fine. I can only guess wir2xnf is encountering an ownership/privilege conflict from NT but I don't understand why this should be so since I have full access to that drive. Has any one seen this problem or have any ideas? ToddArticle: 4954
On Fri, 03 Jan 1997 15:14:33 -0800, "Todd A. Kline" <Todd.Kline@gsnetworks.gensig.com> wrote: > >Problem: >wir2xnf cannot open the wir files on the network drive. > >If I move the wir files to the C: drive, wir2xnf runs fine. > I had a similar experience with xnf2wir. My entrire development is on my local drive with the exception of a single Viewlogic library which is on the NT 4.0 server (mapped as drive P:). xnf2wir fails with some obscure message (I can't remember the details). Copying the library to the local drive and changing the viewdraw.ini reference allowed xnf2wir to work again. I never reported this to Xilinx as much more critical & fatal errors have been reported without any resolution so far. So I don't want to add to their workload until they've fixed the showstoppers :-) Alan Weir Sphere Communications Inc.Article: 4955
In article <E3EC51.KFq%spenford@zoo.toronto.edu>, Henry Spencer writes: > In article <Pine.BSI.3.91.961230231701.16021A-100000@malasada.lava.net> "Alvin E. Toda" <aet@lava.net> writes: > >...In another example (I'm reaching), we see non- > >parity rams now on PC's-- making it difficult to detect errors > >immediately, but perhaps later on writing to disk... > > Or perhaps never. Non-parity PCs are a testament to the fact that many > people don't care whether their spreadsheets give correct results, so > long as they run fast. I always thought it was testimony to the principle that if the implementation is bad enough, people will perceive that the feature has no value, even if the original idea had merit. PC's don't handle parity errors apropriately. They crash, immediately. Files aren't closed. Data in applications and disk buffers is not saved. Some might even rather accept the parity error that have the machine react in this manner. Others may see some small value. Either way, it's hard to justify the extra cash for such a dubious feature. ---- "..very sad life. Probably have very sad death. But there's symmetry" Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 4956
I'll add my 2 cents to this interesting discusion: 1. 100% Testability I don't think people understand Romuald Andraka's statement about SRAM based devices being 100% testable, so I will put it in perspective: An Intel test engineer once stated that to do 100% testing of an 80386 processor would take 2000 years using the fastest available testers available at the time. The reason is that the pre-wired logic is not easily 100% accessable. Think of a 32 bit counter. You have to clock it 4294967296 times to get a carry bit out. If you want to test the carry bit with combinations of other bits, you have to do this clocking over and over again. You get the picture. Of course people are smarter about testing nowdays. In the case of the counter, you could hook it up to a scan chain. But the testability of pre-wired logic is almost never 100%. People often settle for 99% or even 90%. A ram-based FPGA, being completely configurable, can get closer to 100% testing of all gates. And it is more likely to be 100% tested because it is a well-understood standard part, rather than a one-of-a-kind ASIC. 2. Radiation As someone from Nasa mentioned, susceptability to radiation is affected by more than transistor size. It depends greatly on the process, and can change when the process or foundry changes. Commercial Actels from a particular foundry were found to have pretty decent radiation resistance against latchup and against flip-flops changing state (much better than Xilinx for example). I heard that Harris was going to build a rad-hard Xilinx, but nothing ever came of it. An ASIC built on a rad-hard line will be much more reliable than any FPGA in a radiation environment. You can look at radiation numbers and come up with probablilities of failure. Your design can include redundancies to minimize these affects. Aircraft (depending on how high they fly) have higher probabilities of radiation affects than vehicles on the ground . Obviously satellites have very high radiation requirements. I have heard of a German satellite that had a Xilinx on it. They programmed it from the ground. If radiation affected a part of it they would reconfigure around it. (I wonder how they handled latch-up problems, or radiation-induced reconfiguration that causes high currents in the chip? Maybe they monitored current). 3. Redundancy A redundant design doesn't solve all problems. I heard of a satellite that had a number of 68000 type processors in it in a redundant architecture. Occasionally one of them would get a radiation hit, and would get re-powered. Then one day a big solar flare occurred and knocked out all the processors, effectively 'killing' the satellite. In a high-radiation environment I wouldn't use a RAM based FPGA, or even a non-rad hard ASIC. In a low radiation environment you have to look at the design. I think it all comes down to having a well-thought out design with failure modes well understood and accounted for. In a non-radiation environment, it seems like it would be pretty simple to design a very safe system with RAM based FPGAs. -tomArticle: 4957
If you are using or going to use 68HC16 microcontroller, you may be interested to look at HC16BGND, an advanced programmer’s interface that helps you to develop, test, and refine your assembly language programs for MOTOROLA’s 68HC16 microcontrollers. The key features include: - Run under MS Windows - Interface through PC’s parallel port - Motorola suggested 10 pin target connector - Download and debug HC16 assembly language program in S19 or HEX format - trace through your code by step through or step over - set up to 100 breakpoints - On-screen editing of register and data memory - On-fly assembly of instruction using mnemonics in program memory - Open infinite Register, Program, and Data windows - Watch window so that you can watch important variables - Exchange data through Windows clipboard - File I/O which can be used to automatically read a hex input file into the file and write the result to an output file. - Easy to use. Just click on the menu with left mouse or click on the windows’ area. Everything is self-explained - Convenient and easy to install due to its parallel port interface. You can use laptop to do an on-site demonstration of you products - Low cost - 30 day money back guarantee and one year product warranty For more information or need a demo program, see http://users.why.net/wctech/hc16bgnd.htm, or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, or send email to WCTECH@WHY.NETArticle: 4958
If you are using or going to use 68HC16 microcontroller, you may be interested to look at HC16BGND, an advanced programmer’s interface that helps you to develop, test, and refine your assembly language programs for MOTOROLA’s 68HC16 microcontrollers. The key features include: - Run under MS Windows - Interface through PC’s parallel port - Motorola suggested 10 pin target connector - Download and debug HC16 assembly language program in S19 or HEX format - trace through your code by step through or step over - set up to 100 breakpoints - On-screen editing of register and data memory - On-fly assembly of instruction using mnemonics in program memory - Open infinite Register, Program, and Data windows - Watch window so that you can watch important variables - Exchange data through Windows clipboard - File I/O which can be used to automatically read a hex input file into the file and write the result to an output file. - Easy to use. Just click on the menu with left mouse or click on the windows’ area. Everything is self-explained - Convenient and easy to install due to its parallel port interface. You can use laptop to do an on-site demonstration of you products - Low cost - 30 day money back guarantee and one year product warranty For more information or need a demo program, see http://users.why.net/wctech/hc16bgnd.htm, or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, or send email to WCTECH@WHY.NETArticle: 4959
kardos@mail.matav.hu wrote:
>
> Hi!
>
> This is the 1st time I'm using an Altera device in my circuit, and it won't boot. The device
> is an EPF8282ALC84-4, the nS/P, MSEL0 & 1 pins decode APU configuration, and it should read
> the configuration data from a 27512 EPROM. I connected all the configuration pins according
> to the AN33 paper of Altera, except ADD16 & ADD17, they are left NC.
> The symptoms are the following. The nSTATUS pin goes high after RESET, the RDCLK pin ticks
> continously and the CONF_DONE pin is stucked at GND. The address lines count endlessly like
> a counter, and the device doesn't come out of this state.
> Have anyone encountered similar problems? I would appreciate any hint. (All signals seem
> to be fine digital, so there mustn't be any electrical failure. I have experience with PLD's
> and uControllers, just my 1st attempt with FPGA's failed.)
>
> Thanx in advance !
>
> *****************************
> Botond Kardos
> kardos@mail.matav.hu
> phone/fax: (36 1) 268-0934
Do you have assigned device correctly?
It is necessary to specify in section "Device Options"
of the menu "Assign" that you want a configuration scheme
of type "Active Parallel Up/Down".
Marcello
================================================
Marcello LAJOLO
Politecnico di Torino
Department of Electronics
Corso Duca degli Abruzzi 24, 10129 Torino (ITALY)
Tel. +39-11-5644004
Fax. +39-11-5644112
e-mail: lajolo@polgen2.polito.it
lajolo@ic.eecs.berkeley.edu
=================================================
Article: 4960On Fri, 3 Jan 1997 14:50:11 +0000, Paul Walker <paul@walker.demon.co.uk> wrotd: >Altera's PDN9625, dated 19 December 1996, announces last order and >delivery dates for the FX880 and 8160 devices (30 June, 97 and 98 >respectively). > >An excuse is offered that the flash process is at end of life. > >No apology (or cash) is offered for apparently causing esisting >customers to re lay out their PCBs to use a different device. These things do unfortunately happen. As an Ex-Intel FAE (and we're talking over a decade ago - well before the FX parts...) it was their general strategy with products or groups that "didn't make sense" to sell them off to some other company. In the field, it was our *opinion* at the time that this was so that Intel wouldn't be holding the bag when the inevitable End of Life notice came around. The case that occurred while I was there was the sell off of their Magnetic Bubble Memories division - they had just developed FLASH memories that were about to enter the market - and the densities and costs looked like it would clearly eclipse bubbles (among other factors). They chose to sell off the whole division to a company that started up solely to run it - only to close the doors several years later. We had customers in my area whose entire business was bubble based "disk" boards that went out of business... > >And what other Altera device has the flexible clocking, the ample output >enables, the 10-bit blocks because you always need a bit more than eight >bits for a byte, or the free and excellent development tools? > >And what other CPLD from anywhere offers the RAM/ROM use of blocks in >the way these devices do? Logic that will go into a single look-up table >in this ROM would not fit into the whole of most 84-pin PLDs. The Intel parts have everything - unfortunately this also resulted in a die size that was huge. At the point Intel sold off the family, the story I heard was that they could sell a 486 for $300, or an FX part with the same die size for $25 - It doesn't take a financial genius to figure out the economies of which wafer you are going to build in a fab limited market. As you point out - no other CPLD has look-up table structures - period. Lattice has announced some parts that have RAM structures - but they are configured more like specialty memories than distributed look-up tables. Some of your other needs could be addressed in other parts from Philips, Xilinx, or Cypress - but if Look-Up table structures is the killer issue you may be out of luck in the CPLD arena. Of course FPGAs can do the look-up, but the wide gating you are looking for isn't there. Mark Aaldering Philips CPLD Applications Mark.Aaldering@abq.sc.philips.com www.coolpld.comArticle: 4961
ASIC stands for Application Specific Integrated Circuit On 1 Jan 1997 22:53:09 GMT, eswar@mega.megamed.com (Subramnyeswar Saladi) wrote: >John Cooley (jcooley@world.std.com) wrote: >: simonson@skopen.dseg.ti.com (Kevin M Simonson) writes: > >: > I'm feeling really ignorant right now. Is there anyone who can tell >: >me what ASIC stands for? Thanks. >: > >: > ---Kevin Simonson > >: Aren't "ASICs" a brand of tennis shoe? :^) > >Why were the shoes named ASIC's ? > > >------------------------------------------------------------------------------ >-- Eswar Saladi email : eswar@megamed.com pager : 408-381-6316 >------------------------------------------------------------------------------ >-- Home Page : http://home.aol.com/Anln >------------------------------------------------------------------------------ >-- Favorite Quote : The essence of advancement is simplicity. --Dr. Zarkov >------------------------------------------------------------------------------ >-- ALL VIEWS EXPRESSED ARE MINE AND MINE ALONE, NO COPYRIGHT VIOLATIONS >------------------------------------------------------------------------------Article: 4962
Can you advise me where on the net I can find documents about Functional Disk Systems? I am searching them for a friend to write thesis, knowing little about this notion myself. Thank you in advance. Zhao Zhang zhangzha@cs.uregina.caArticle: 4963
The pure software approach worked for us too. All we wanted to do was program the various on-chip registers in a Phillips Video A/D and an Analog Devices video D/A. We put both chips on the same i2c bus, used a 22v10 GAL to let the microprocessor assert clock and data in code and handled all the I2C protocol in code. Actually we made the data line input and output so we could read back the registers to verify that we had programmed them properly. Worked good. David StarrArticle: 4964
I am somewhat familiar with the hardware required to initialize an Altera 10K device in the passive serial configuration. How similar is the process for a Xilinx part ?Article: 4965
In article <32BD0C21.69ED@sj.co.uk>, Steve Wiseman writes: > Eric Edwards wrote: > > > > 'Got a design, written in verilog of about 1000 lines. > > For a variety of reasons, I'm trying to fit this to an Altera Flext 10K10 > > FPGA. Should be easy, right? 3500 gate design, 10000 gate part. But it > > doesn't fit. I could understand possibly having routing problems but I'm > > running out of logic cells: 610 vs the 565 cell capacity of the 10k10. > > > Any ideas on what could be causing this area explosion? Better yet, > > suggestions as to what to do about it? > > Sounds a lot like you're running without any serious optimisation. > Perhaps _all_ nodes are being preserved, so each of your 3500 ASIC > gates is being fitted separately. (as in Altera's WYSIWYG mode) Whose > fitter are you using? Syntheis is Asyl+. I guess the fitter would be Max+PlusII. This is the PLS-ES packaging. I've managed to trim a little bit off by flattening (in Asyl+), enabling carry chains and automatic EAB allocation. But it's still over 600. >A quick grovel through the output files ought to > show you what's going on. Actually, I'm not sure that I have any output files. The 10K10 is the largest part supported so it seems to just bail. ---- "..very sad life. Probably have very sad death. But there's symmetry" Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 4966
George Pontis wrote: > > I am somewhat familiar with the hardware required to initialize an > Altera 10K device in the passive serial configuration. How similar is > the process for a Xilinx part ? Very, if by passive serial you mean the host provides clock and data to the device. We use mixes of Altera 8K and Xilinx 3K here, no problems, even sharing a common data line and clocking the devices separately. Not had a problem yet. I _think_ Altera 10K is much the same in this mode as 8K, it may be worth a rummage round the web site at http://www.altera.com Steve -- Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK Desk +44 1223 578524 (Fax 578525) Group +44 1223 578518 steve@sj.co.ukArticle: 4967
>If I move the wir files to the C: drive, wir2xnf runs fine. > When I upgraded to the latest XACT software on the Sun computer, I found that XBLOX had problems accessing disks across the network. For example, we have XACT installed on a computer called RL10b, but my files are on a computer called SEIC10a. I could log onto RL10b, cd to SEIC10a, and run xnfprep and xmerge, but XBLOX gave an error because it expected the remote file system to be local. Luckily, if I used the entire path name (even though I was cd's to the directory) when specifying the source file, XBLOX worked. I sent this to Xilinx as a bug (Xilinx technical support case #114019); it didn't happen in previous versions. The Xilinx response was that some programs don't require me to specify the entire path name, and some do: Hi Joe, It sounds like you are up and running. You are correct in seeing that it is not necessary to specify the entire pathname for all the programs. The programs that are licensced are XDE, PPR, XBLOX, and XABEL. I will be closing this issue, if you would like me to do something else, please let me know. The UNIX programmers here tell me that Xilinx must have put some effort into forgetting which machine the file system belonged to, because UNIX handles that automatically. -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+Article: 4968
John L. Smith wrote: > > Stephan Gick wrote: > > > > Hi all, > > does anybody know application notes of FPGA realizations of a I2C Bus > > interface? > > I think that I2C may be of sufficient complexity and commercial > interest that even if people have developed one, they are not willing > to share. I posted same question a few months back, had no reply. > > However, if someone has developed something in the meantime, pls > let me know too. > > -- > John L. Smith, Pr. Engr. I did a design for a subset of the functions in an Altera FLEX8k and it is rather simple. I would like to point to a special problem: The rise time for the I2C clock can be very slow, if the line has just a pull-up. We had to include a schmitt-trigger and a simple digital filter as a deglitcher. Alfred -- My little grey cells speak for themselves, not for my company. But have a look at http://www.siemens.at, http://www.siemens.de or http://www.siemens.com mailto:alfred.fuchs@siemens.at Phone: 43/1/1707-34113Article: 4969
There will be a Birds of a Feather Session on Linux and EDA at Usenix 97 in Anaheim on Jan 7 at 7 pm. We'll share information on EDA software currently available on Linux, ideas for promoting more support and the current state of LinuxEDA. For developers there will be information on how to support Linux from the practical side of third party tools like license servers, memory managers and online documentation tools. If you're in the area Tuesday evening stop by, even if you're not attending the conference. The BOF will be at the Anaheim Marriot. Send email to peter@linuxeda.com and I'll send you the exact room information. If you can't make it, but would like a summary of the BOF and further Linux & EDA developments, you can also send email to info@linuxeda.com Peter Collins LinuxEDAArticle: 4970
Hi I'd like to buy some (5) MPA1016FN devices in Germany but they are sold only in quantities of 15. Is anyone wishing to place a collective order ? Price is around DM 65.-- Alternatively I could take 2 of MPA1036DD or DH but these come in quantities of 24. Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 e-mail:kugel@mp-sun1.informatik.uni-mannheim.deArticle: 4971
------------------------------------------------------------------------------
Advance Program
1997 ACM/SIGDA Fifth International Symposium on
Field-Programmable Gate Arrays (FPGA'97)
Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel
Monterey Beach Hotel, Monterey, California
February 9-11, 1997
(Web page: http://www.ece.nwu.edu/~hauck/fpga97)
------------------------------------------------------------------------------
Welcome to the 1997 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays (FPGA'97). This annual symposium is the premier forum for
presentation of advances in all areas related to FPGA technology, and
also provides a relaxed atmosphere for exchanging ideas and stimulating
discussions for future research and development in this exciting new field.
This year's symposium sees a strong increase of interest in FPGA
technology, with over 20% increase in paper submissions. The technical
program consists of 20 regular papers, 35 poster papers, an evening panel,
and an invited session. The technical papers present the latest results
on advances in FPGA architectures, new CAD algorithms and tools for FPGA
designs, and novel applications of FPGAs. The Monday evening panel
will debate whether reconfigurable computing is commercially viable.
The invited session on Tuesday morning addresses the challenges for
architecture development, CAD tools, and circuit design of
one million-gate FPGAs and beyond.
We hope that you find the symposium informative, stimulating, and enjoyable.
Carl Ebeling, General Chair
Jason Cong, Technical Program Chair
------------------------------------------------------------------------------
SYMPOSIUM PROGRAM
Sunday February 9, 1997
6:00pm Registration
7:00pm Welcoming Reception,
Monterey Beach Hotel, Monterey
Monday February 10, 1997
7:30am Continental Breakfast/Registration
8:20am Welcome and Opening Remarks
Session 1: FPGA Architectures
Session Chair: Rob Rutenbar, Carnegie Mellon Univ.
Time: 8:30 - 9:30am
1.1 "Architecture Issues and Solutions for a High-Capacity FPGA",
S. Trimberger, K. Duong, B. Conn, Xilinx, Inc.
1.2 "Memory-to-Memory Connection Structures in FPGAs with Embedded Memory
Arrays",
Steven J.E. Wilton, J. Rose, Z.G. Vranesic, University of Toronto
1.3 "Laser Correcting Defects to Create Transparent Routing for Large Area
FPGAs",
G.H. Chapman, B. Bufort, Simon Fraser University
Poster Session 1: Analysis and Design of New FPGA Architectures
Session Chair: Tim Southgate, Altera, Inc.
Time: 9:30 - 10:30am (including coffee break)
Session 2: FPGA Partitioning and Synthesis
Session Chair: Richard Rudell, Synopsys, Inc.
Time: 10:30 - 11:30am
2.1 "I/O and Performance Tradeoffs with the FunctionBus during Multi-FPGA
Partitioning",
F. Vahid, University of California, Riverside
2.2 "Partially-Dependent Functional Decomposition with Applications in FPGA
Synthesis and Mapping",
J. Cong, Y. Hwang, Univ. of California, Los Angeles
2.3 "General Modeling and Technology-Mapping Technique for LUT-based FPGAs",
A. Chowdhary, J.P. Hayes, University of Michigan
Poster Session 2: Logic Optimization for FPGAs
Session Chair: Martine Schlag, Univ. of California, Santa Cruz
Time: 11:30 - 12noon
Lunch: noon - 1:30pm
Session 3: Rapid Prototyping and Emulation
Session Chair: Carl Ebeling, Univ. of Washington
Time: 1:30 - 2:30pm
3.1 "The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System",
D.M. Lewis, D.R. Galloway, M. V. Ierssel, J. Rose, P. Chow,
University of Toronto
3.2 "Signal Processing at 250 MHz using High-Performance Pipelined FPGA's",
Brian Von Herzen, Rapid Prototypes, Inc.
3.3 "Module Generation of Complex Macros for Logic-Emulation Applications",
Wen-Jong Fang, Allen C.H. Wu, Duan-Ping Chen, Tsinghua University
Poster Session 3: Novel FPGA Applications
Session Chair: Brad Hutchings, Brigham Young Univ.
Time: 2:30 - 3:30pm (including coffee break)
Session 4: Reconfigurable Computing
Session Chair: Jonathan Rose, Univ. of Toronto
Time: 3:30 - 4:30pm
4.1 "Wormhole Run-time Reconfiguration",
R. Bittner, P. Athanas, Virginia Polytechnic Institute
4.2 "Improving Computational Efficiency Through Run-Time Constant
Propagation",
M.J. Wirthlin, B.L. Hutchings, Brigham Young University
4.3 "YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data
Processing",
A. Tsutsui, T. Miyazaki, NTT Optical Network System Lab.
Poster Session 4: Reconfigurable Systems
Session Chair: Scott Hauck, Northwestern Univ.
Time: 4:30 - 5:30pm
Dinner: 6:00 - 7:30pm
Evening Panel: Is reconfigurable computing commercially viable?
Moderator: Herman Schmit, Carnegie Mellon Univ.
Time: 7:30 - 9:00pm
Panelists:
Steve Casselman: President, Virtual Computer Corp.
Daryl Eigen: President, Metalithic Systems, Inc.
Robert Parker: Deputy Director, ITO, DARPA
Peter Athanas: Assistant Professor, Virginia Polytechnic Institute
Robert Colwell: Pentium Pro Architecture Manager, Intel Corp.
In this panel session, we will try to address the questions of whether
there will be a mass-market for FPGA-based computing solutions. Are
there large sets of applications whose performance requirements far
exceed that offered by microprocessors but which are only
occasionally executed? Where are these applications? Does the
ability to reconfigure during execution change the cost and
performance benefits of reconfigurable hardware significantly? What
are the key challenges to making reconfigurable computing a reality,
and what can PLD manufacturers, system houses, government, and
academia do to overcome these obstacles?
Session 5: FPGA Floorplanning and Routing
Session Chair: Dwight Hill, Synopsys, Inc.
Time: 8:30 - 9:30am
5.1 "Synthesis and Floorplanning for Large Hierarchical FPGAs",
H. Krupnova, C. Rabedaoro, G. Saucier, Institut National Polytechnique de
Grenoble/CSI
5.2 "Performance Driven Floorplanning for FPGA Based Designs",
J. Shi, Dinesh Bhatia, University of Cincinnati
5.3 "FPGA Routing and Routability Estimation Via Boolean Satisfiability",
R.G. Wood, R.A. Rutenbar, Carnegie Mellon University
Poster Session 5: High level Synthesis and Module Generation for FPGAs
Session Chair: Martin Wong, Univ. of Texas at Austin
Time: 9:30 - 10:30am (including coffee break)
Session 6 (Invited): Challenges for 1 Million-Gate FPGAs and Beyond
Session Chair: Jason Cong, Univ. of California, Los Angeles
Time: 10:30am - noon
Process technology advances tell us that the one million gate FPGA will soon
be here, and larger devices shortly after that. Current architectures
will not extend easily to this scale because of process characteristics and
because new opportunities are presented by the increase in available
transistors. In addition, such large FPGAs will also present significant
challenges to the computer-aided design tools and methods.
Two invited papers address these issues.
6.1 "Architectural and Physical Design Challenges for One Million Gate FPGAs
and Beyond",
Jonathan Rose, University of Toronto, Dwight Hill, Synopsys, Inc.
6.2. "Challenges in CAD for the One Million-Plus Gate FPGA",
Kurt Keutzer, Synopsys, Inc.
Lunch: noon - 1:30pm
Session 7: Studies of New FPGA Architectures
Session Chair: Steve Trimberger, Xilinx, Inc.
Time: 1:30 - 2:30pm
7.1 "A CMOS Continuous-time Field Programmable Analog Array",
C.A. Looby, C. Lyden, National Microelectronics Research Center
7.2 "Combinational Logic on Dynamically Reconfigurable FPGAs",
D. Chang, M. Marek-Sadowska, Univ. of California, Santa Barbara
7.3 "Generation of Synthetic Sequential Benchmark Circuit",
M. Hutton, J. Rose, D. Corneil, University of Toronto
Poster Session 6: FPGA Testing
Session Chair: Sinan Kaptanoglu, Actel, Inc.
Time: 2:30 - 3:30pm (including coffee break)
Session 8: Novel Design and Applications
Session Chair: Pak Chan, Univ. of California, Santa Cruz
Time: 3:30 - 4:10pm
8.1 "Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency
Independent of Counter Size",
A.F. Tenca, M. D. Ercegovac, Univ. of California, Los Angeles
8.2 "A FPGA-based Implementation of a Fault Tolerant Neural Architecture for
Photon Identification"
M. Alderight, E.L. Gummati, V. Piuri, G.R. Sechi, Consiglio Nazionale delle
Ricerche, Universita degli Studi di Milano, Politecnico di Milano
4:30pm Symposium Ends.
-------------------------------------------------------------------------------
Organizing Committee:
General Chair: Carl Ebeling, University of Washington
Program Chair: Jason Cong, UCLA
Publicity Chair: Scott Hauck, Northwestern University
Finance Chair: Jonathan Rose, University of Toronto
Local Chair: Pak Chan, UC Santa Cruz
Program Committee:
Michael Butts, Quickturn Pak Chan, UCSC
Jason Cong, UCLA Carl Ebeling, U. Washington
Masahiro Fujita, Fujitsu Labs Scott Hauck, Northwestern Univ.
Dwight Hill, Synopsys Brad Hutchings, BYU
Sinan Kaptanoglu, Actel David Lewis, U. Toronto
Jonathan Rose, U. Toronto Richard Rudell, Synopsys
Rob Rutenbar, CMU Gabriele Saucier, Imag
Martine Schlag, UCSC Tim Southgate, Altera
Steve Trimberger, Xilinx Martin Wong, UT Austin
Nam-Sung Woo, Lucent Technologies
-------------------------------------------------------------------------------
Hotel Information
FPGA'97 will be held at the Monterey Beach Hotel, 2600 Sand Dunes Dr.,
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Reservations must be made before January 10, 1997. Identify yourself with
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Reservations may be canceled or modified up to 72 hours prior to arrival
without a penalty. If the cancellation is made within 72 hours of arrival,
or you fail to show up, first nights room and tax will be charged. If a
modification is made within 72 hours of arrival (i.e., postpones arrival or
departs earlier than reserved) the actual nights of your stay will be charged
at the quoted rack rate for the room occupied.
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hours) take Hwy 101 South to Hwy 156 West to Hwy 1 South. From Hwy 1 South,
take Seaside/Del Rey Oaks exit. The hotel is at this exit on the ocean side.
You can also fly directly to Monterey Airport, which is served by United,
American and other airlines with at least 8 flights per day.
Monterey Area
The Monterey Peninsula is famous for its many attractions and recreational
activities, such as John Steinbeck's famous Cannery Row and the Monterey Bay
Aquarium. Also, play one of 19 championship golf courses. Charter fishing
is available right at Firsherman's Wharf. Monterey is renowned worldwide for
its spectacular coastline, including Big Sur and the Seventeen Mile Drive.
Recreational activities, shopping opportunities and restaurants abound.
-------------------------------------------------------------------------------
Registration Information:
The Symposium registration fee includes a copy of the symposium proceedings,
a reception on Sunday evening, February 9, coffee breaks, lunch on both days,
and dinner on Monday evening, February 10.
First Name:_____________________Last Name:_________________________________
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Circle Fee Before January 22, 1997 After January 22, 1997
ACM/SIGDA Member US$300 US$370
*Non-Member US$400 US$470
Student US$ 90 (does not include reception or banquet,
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Send Registration, including payment in full, to:
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For registration information contact Debbie Hall via e-mail at
halldeb@aol.com. Cancellations must be in writing and received
by Meeting Hall, Inc. before January 22, 1997.
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
| Scott A. Hauck, Assistant Professor |
| Dept. of ECE Voice: (847) 467-1849 |
| Northwestern University FAX: (847) 467-4144 |
| 2145 Sheridan Road Email: hauck@ece.nwu.edu |
| Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck |
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Article: 4972If you're really interested in SEU-immune, high-rel FPGAs you should go to the companies which are building Class S, rad hard versions of the ACTEL form (Lockheed Martin, partnered with Actel) and Xilinx form (Honeywell). These will be able to provide you with bit error rate, total dose and other reliability and failure/fault analysis information (presuming they care to, and that's not a given; they'll probably make you pass through Marketing first to see if you're a customer or just a babbler). You can get SEU-immune SRAMS and digital ASICs from either of the above. No, you won't like the price. You can also get SEU-immune PROMs to reload the SRAM-based FPGAs from, ditto on the cost. If you are that concerned with eliminating failure modes, though, you'll pay the prices or you'll stay on the ground. Anything else will net you an unacceptable probability of failure. You can't compromise with a bullet (or a relativistic heavy ion). -- ########################################################################## #Irresponsible rantings of the author alone. Any resemblance to persons # #living or dead then yer bummin. May cause drowsiness. Alcohol may inten-# #sify this effect. Pay no attention to the man behind the curtain. Billy!#Article: 4973
James W. Swonger <jws@billy.mlb.semi.harris.com> wrote in article <5attn9$mkg@hearye.mlb.semi.harris.com>... > If you're really interested in SEU-immune, high-rel FPGAs you should go > to the companies which are building Class S, rad hard versions of the > ACTEL form (Lockheed Martin, partnered with Actel) and Xilinx form > (Honeywell). These will be able to provide you with bit error rate, > total dose and other reliability and failure/fault analysis information > (presuming they care to, and that's not a given; they'll probably make > you pass through Marketing first to see if you're a customer or just a > babbler). > For the Actel/Lockheed-Martin device (RH1280), there is plenty of publicly available data concerning the radiation performance of these devices. While extremely tolerant to total dose and having a very good tolerance to antifuse damage, the user storage cells in the logic modules and i/o cells are not SEU-immune and can be broken into three groups depending on how the flip-flops are constructed: c-module (pretty good), i/o module latch (pretty good), and s-module (relatively low threshold). Also, is Honeywell building the Xilinx compatible part? Is there contact information on this? I know Harris had a data sheet on some of these Xililinx devices a few years ago but I believe they dropped the part. rkArticle: 4974
>Hi Andreas,
>
>while I can't help you with the group buy, I was curious about
>your experiences with the Moto FPGA. Are you using the free
>software ? Which design capture method are you using (Viewlogi/
>OrCad/VHDL/Verilog)?
>
>Just wondering, I have tooled with the APR tool a bit and
>got started on a netlist generator for one of the tools I'm
>use sometime "diglog". Since diglog is free and the APR is
>free, this would be a good way to get into FPGAs for people.
>However, I think it's hard to get the parts. In the US,
>Universities and get free parts from Moto, but this doesn't
>help everyone.
>
>Anyway, do you think there is much interest in a MPA netlister
>and libraries for free CAD tools like diglog ?
I use the free software (current version is 2.3)
I tried some register intensive designs with not much logic (max 5
levels deep) and got a 95% utilisation @ 40MHz with a MPA1016
and a 75% utilisation @ 40Mhz (larger but similar design) with
a MPA1036 (autolayout estimations).
Place&ROute prcessing time are up to 2 hours on a 90MHz Pentium/32MB.
The chips are available (at least I got a quotation) from Future
Electronics.
Motorola donated a free sample (MPA1036HI).
I use a standard EDA schematic editor as front-end tool. To write
a symbol library is quite easy, just port the MPA library to your
schemtaic tool.
The EDIF output of my Ulticap editor needs some postprocessing but then
it works OK.
A free schemtic tools would be nice, but if you already have a schematic
entry you can use that.
Comments?
Andreas
--
Andreas Kugel, Karolinenstr. 4
76135 Karlsruhe, Germany
Phone: (49) 721 377865, Fax (49) 721 937 49 12
E-mail: akugel@t-online.de
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