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Hi, I have a dilemma regarding Xilinx software, NeoCAD (OK, Xilinx also) software, and XC4KE devices. I am an XACT Foundry V7.0 (aka NeoCAD FPGA Foundry) user. I am have spent a lot of time getting to know this software and I like it a lot. But it doesn't support XC4KE features. I also have XACTstep XC4000E Pre-Release V1.0.0, which does support XC4KE features, but which I have so far not attacked in earnest. Finally, Xilinx claims that they are hard at work on their new generation of software, which will "merge" XACT and NeoCAD tools, taking the "best" of each in some miraculous fashion. Whenever I call Xilinx, they say that the merged toolset will be released "real soon now." The dilemma is this. If I believe that the merged toolset is actually on the horizon, then I should not bother with the XACTstep pre-release, because just about the time I get proficient with it, it will be obsolete. But if the merged toolset is not going to appear, then my best (only) plan is to start using both the NeoCAD tools and the XACTstep pre-release tools (and then be stuck with TWO obsolete toolsets when the merged product rolls out). What I *want* (but have been told is not going to happen) is for a new version of XACT Foundry to appear at my doorstep, with XC4KE support rolled in. What I will settle for is just a straight answer on when the merged toolset will be released, so that I can make a rational decision between my alternatives. Anybody with a crystal ball, a buddy at Xilinx, or a boss at Xilinx want to help? Thanks, -Steve Gross gross@pa.msu.eduArticle: 5751
Jaap Mol <jhmol@a1.nl> writes: > Richard Schwarz wrote: > > > > Anybody had any experience with the ACTEL RAM BASED FPGAs? > > I have heard that there are several beta customers in the US, testing > this new technology and > its new design software, but I believer no parts are commercially > available yet. > Please refer to the ACTEL homepage (http://www.actel.com) for the latest > news. > > > I think this is a smart move on their part but haven't heard much about them. > > I fully agree with you. I believe this technology will be the first > SRAM-based technology on the marktet > having a fine-grained (synthesis-friendly!) architecture. I'm very > curious what ACTEL comes up with > within the next few months. I remember Crosspoint had a find grained architecture several years ago. They supported standard ASIC tools like Verilog and Synopsys. I received some literature from them but I have not heard from them since then. Does anybody know what happened to Crosspoint and their CP20K FPGA's? > P.S. I am NOT an ACTEL employee, but our company has been using ACTEL > anti-fuse technology, as well > as XILINX and ALTERA SRAM-based technology. Petter -- ________________________________________________________________________ Petter Gustad http://www.dolphinICS.no/~peguArticle: 5752
In article <331F5B0F.10E8@Boeing.com>, Mark.E.Osterud@Boeing.com wrote: > Can someone point out a study that evaluates the reliability aspects of > an FPGA as opposed to discrete logic? This is a very broad question, and I would suggest to narrow it down to: 1. Hard failures 2. Soft errors 2a. Soft errors as a result of radiation ( single-event upset ) Regarding 1, Xilinx devices ( and I can only speak for my company, but I assume that our competitors are not very much worse, otherwise they would be out of business ) have an excellent recod of reliability, expressed in sigle-digit FIT numbers. You can ( and most likely do ) receive a quarterly reliability brochure update from Xilinx. We are very proud of our record, which is partly the result of using state-of-the-art, but otherwise plain-vanilla CMOS processing.No strange voltages, no exotic structures, no untestable circuitry. ( Do you detect a slight bias against antifuses here ?) 2. We have never heard of configuration bits getting corrupted under normal operating conditions. We make the configuration latches out of active inverters, -no polysilicon pullups here- so we expect the configuration to be far more robust than the information stored in standard SRAMs. 2a. Considering the business your company is in, this may be important to you, but I don't have data here. You may read a very, very long thread in this newsgroup a few months ago. Peter Alfke, Xilinx ApplicationsArticle: 5753
Erik Jessen wrote: > > I would recommend looking at Synario's ECS schematic-capture/waveform > display tool. it was very solid for us, and had a lot of nice features > (VHDL, Verilog, EDIF netlisting, can netlist to PCB layout tools, etc.). > > We used it with Modeltech and Exemplar, and liked it a lot. We had > probably 20-30 copies of ECS. > > Erik Check out Veribest at http://www.veribest.com They are currently OEMing FPGA Express and have a very good PCB tool. Have fun. -- +-----------------------------------------------------------------------+ : ttessier@talcian.com | Phone: 303.440.0570 : : Thomas Tessier | FAX: 303.441.5811 : : | WWW: http://www.talcian.com : +------------------------Have a nice Day--------------------------------+Article: 5754
Mike Williams (please@no.junk.mail.com) wrote: : Any suggestions. I need schematic entry for PCB design. I don't need : to actually do the PC layout, just produce the schematics, parts : list and netlist. OrCAD DOS (SDT386) - if you can get it , of course. Both OrCAD and ViewLogic had good schematic tools before upgrades (or ,rather, down- grades) for Windows. OrCAD for DOS is much cheaper than ViewDraw. Other- wise they are roughly equivalent if you don't need simulation.Article: 5755
Hi, I am currently working on an FPGA design using the Xilinx PCI Logicore. The core is pretty user friendly and the testbench supplied by Xilinx seems to work pretty well, but I do have some problems. Since I was still trying to get entirely familiar with our tool capability I designed a slave only device containing a small chunk of SRAM. I did the cookbook R/W decode logic in shematic form in order to work out the bugs in the testbnch. Everything went very smooth. The design simulated functionally and placed/routed quite easily. I then took the same design and did the R/W decode in VHDL. I simulated the design by creating an XNF file from Exemplar, creating a WIR file for the decode logic w/Xilinx XACT tools set, created a schematic model by hand for the decode logic, and everything seemed to play well. I was able to functionally simulate the R/W of that RAM quite easily. One of our tool admins mentioned to me that Viewlogic has a tool that will read a VHDL file and create a schematic block. I ran the tool and sure enough a schematic block was created, but I can't seem to functionally simulate the design like I could the hand created block. After I plugged the new shematic model into my schematic I ran the "check" tool which creates the WIR files for the design. When I was doing the design w/hand created models I would get a warning saying "the schematic for decode.1 was not found". Of course this makes sense since there was no schematic and I created the associated WIR file from the XNF file. When I performed the check w/the VHDL->SYM generated tool there were no warnings about missing schematic blocks. After plugging the design into VSM and creating the vsm file, I tried to simulate my shiny new design. Needless to say the system didn't recognize the logic in the logic block. After looking at the schematic symbol created by the Viewlogic "VHDL->SYM" I noticed that there were attributes which implied the IN/OUTs were VHDL STD LOGIC blocks. I am assuming that the reason the tool didn't simulate the decode logic was because the VHDL was supposed to be simulated on the fly. Obviously it wasn't looking for a WIR file which was generated from and WNF file, because I had that in the WIR directory. I guess I am asking how I get the VHDL so simulate on the fly w/Fusion or maybe some pointers to put me on the right path. I am guessing that the design and the schematic blocks are linked ok when it hits Fusion, but some silly switch isn't set in Fusion or my file structure isn't correct and it is looking in the wrong directory. Of course the designers have no manuals, so I am sitting in the dark. Thanks Rod Leiting rjleitin@cca.rockwell.com rodnstacy@internetmci.comArticle: 5756
Is it possible to purchase a development board with multiple XILINX 4000 series FPGAs so that large designs can be accomodated? If so, can I have the address/phone# of the company? Thanks in advance, Hari ShankarArticle: 5757
Todd A. Kline wrote: > > We are currently using ViewSynthesis and ViewPLD for FPGA and PLD/CPLD > designs. > We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and ViewPLD > is buggy, unstable, and poorly supported. I would be very grateful for > any feedback on the following products: > > 1) Exemplar > > 2) Synario > > 3) Minc (PLD/CPLD) + Synplicity (FPGA). > > I have done some benchmarking on Synplicity and found that it optimized > better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL solution. > > I also must say that I have a GREAT prejudice against Synario. I have > found DataIO support to be on a par with VIEWlogic, that is to say > horrible. I also have doubts about DataIO's commitment to EDA > products. Does any one remember FutureNet/Gates? > > For these reasons I find my self leaning to Exemplar but only because I > know next to nothing about them. Ignorance is, after all, bliss. > > Your feedback is eagerly anticipated. > > Todd Synplicity is a very fast synthesis tool but gives almost no feedback about what it has done (at least in last years release 2.99). Exemplar gave a very good impression in a demo. You might also want to check the accolade tools (I believe their address is http://www.acc-eda.com) or synopsys fpga express. -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5758
Try Aptix at: http://www.aptix.com Probably not cheap, but looks_real_nice. :-)Article: 5759
rich.katz@gsfc.nasa.gov says... > hi, > > i have upgraded a bunch of viewlogic 'seats' to the viewoffice stuff and > got them all at the exact same revision. seems like a good idea. now, > some seats were upgraded from workview plus and others from pro series. <snip> > now that they are all the same, > i am having trouble (like can't do it) reading files on 'heritage' pro > series seats from former workview plus seats, although they are just simple > schematics that i can easily create on either computer. and going from the > former pro series to the former workview plus seems to work just fine. > > suggestions? comments? Sounds like possible artifacts from the ViewLogic licensing scheme for WV and PRO, where PRO licenses were deliberately crafted so that there was no compatibility permitted from WV to PRO seats. ViewLogic tech support should be able to sort this out for you, but the fix should be interesting. Here's a possible suggestion, if you're desperate: How about installing the old WorkView on the former PRO seats? Have you tried that? If that works, then you can try "upgrading" the WV to WV Office. This may be worth a go. And here's a gratuitous comment: ViewLogic's licensing, dongle, and security key schemes were devised to maximise revenue to the last penny. For users, it was a real pain to be blocked at every new turn while trying to do something that should have been simple enough, and every time the answer from ViewLogic was 'sure, we can help you, here's what you need to buy, and this is how much it costs.' I wouldn't be surprised if you've been bitten by a residual artifact of their arcane licensing policy and implementation. You would not have been the first, if this is the case. Good luck, and please post the final fix for this problem! -- Bob **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5760
In article <3326D5D9.6F67@pa.msu.edu>, gross@pa.msu.edu says... > Hi, > > I have a dilemma regarding Xilinx software, NeoCAD (OK, Xilinx also) > software, and XC4KE devices. > > I am an XACT Foundry V7.0 (aka NeoCAD FPGA Foundry) user. I am > have spent a lot of time getting to know this software and I like > it a lot. But it doesn't support XC4KE features. > > I also have XACTstep XC4000E Pre-Release V1.0.0, which does support > XC4KE features, but which I have so far not attacked in earnest. <snip> > What I *want* (but have been told is not going to happen) is for a > new version of XACT Foundry to appear at my doorstep, with XC4KE > support rolled in. > > What I will settle for is just a straight answer on when the merged > toolset will be released, so that I can make a rational decision > between my alternatives. Anybody with a crystal ball, a buddy at > Xilinx, or a boss at Xilinx want to help? > -Steve Gross gross@pa.msu.edu When it comes time to Xilinx tools software, the wisest course is to not depend on a specific release/availability date. I don't mean this as a swipe at Xilinx, please don't misunderstand. Would you want Xilinx to release a package that wasn't fully tested and wrung out, in order to meet a specific availability date? I don't think that is what you really want. Xilinx has had problems in the past with SW releases that were buggy. I think Xilinx is trying hard to correct that practice, even though additional testing adds time to the development/release schedule. In the engineering spirit, you should make do with the tools that are available and that you can make work today. If something better comes along, then you can always consider a switch (and the risk of a new learning curve) at that time. Depending upon the circumstances, many designers won't even consider major tools changes in the middle of a project, unless they are really desperate. The risk is usually too great. -- Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5761
For some reasons, I need to know the total numbers of the Product Term
that are used in my design, but the MaxPlusII compiler report only gives
me the sharable expander numbers. So does anyone know where to find it?
Please don't tell me to count them one by one :-) The device I use is
MAX7000 series.
-------------------==== Posted via Deja News ====-----------------------
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Article: 5762
Does anyone know where to find the logic level of a design accomplished
with Altera device? The Fmax, Tpd are not enough for me, I need the
abstract information, independent to speed grade.
-------------------==== Posted via Deja News ====-----------------------
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Article: 5763ecla@world.std.com (alain arnaud) wrote: >A viewlogic story... >I have been using Viewlogic since the late 80s. Workview 4.x for DOS, >Powerview for Unix and Workview/Plus for Win 3.1, were excellent >products, for both schematic entry and simulation, they even had >a decent hot line and knowlegeable tech support. All of the above >products were compatible,a schematic entered in Powerview could be >read and modifiedin Workview and Workview+, and vice versa. >There was support for command line and macros. >I would say the only problem with Workview+ was the lack of support of >windows printers, but it came with a set of drivers for many printers. >Workview+ and Powerview shared the same GUI. >In 93/94, they came out with the ProSeries, the only reason to purchase >these tools is that they were cheaper than Workview+ and they were >windows compliant. They were buggy and lacked many features. >In 95/96, ViewOffice was announced and delivered, everyone using Workview+ >had a choice of either getting an upgrade for Win3.1 and for Win95/NT, with >the understanding that the Win3.1 upgrade would be the last one, with no >further product enhancements. >When ViewOffice was in beta, Viewlogic received dozens if not hundred >of bug reports and enhancements requests,, they decided to ignore most >of them and just fix the most glaring bugs that prevented the product >from working, gone were the command line, macros, the editing shortcuts, >and a few other features that made Workview+ an above average CAD tool. >At the same time, their tech support competency disappeared. Viewoffice >is now an average to a below average CAD tool. >As a consultant, I am asked what CAD tool do I recommend, and used to say >Viewlogic. In 96, five of my clients have purchased more than 15 seats >of Viewoffice, but no more, now its welcome to Viewlogic HELL. >One of these clients decided to get Viewsynthesis against my advice, because >Viewlogic made hime a deal he could not refuse. So we set on designing >three FPGAs and two ASICs with it, after about three months of trying >to debug the logic generated by ViewSynthesis, he wised up and >purchased Synopsys. >In summary: > - Viewsynthesis is BAD! > - Viewoffice is usable but less user friendly than the older > products. > - Viewlogic tech support is non-existent. > - I will not recommend ViewOffice to any of my clients anymore. >IMHO, Viewlogic decided that they had to compete with Orcad and some >of the other low end tools at the same time they were trying to compete >with Mentor and Cadence, and they missed the boat. They changed the sales >channel, by focusing on distributors (Trilogic in Mass.) for small companies >and direct sales for large corp. >So my question is: > Does Mentor Graphics and or Cadence have CAD tools for Win/NT or > a Sparc at a competitive price? >Tools I use today are: > - Viewdraw and Viewsim (until I find a replacement) > - Modeltech for VHDL simulation > - FPGA Express for FPGA synthesis > - DC for ASIC synthesis >Alain Arnaud (arnaud@ecla.com) >ECLA Inc.Article: 5764
ecla@world.std.com (alain arnaud) wrote: >A viewlogic story... >I have been using Viewlogic since the late 80s. Workview 4.x for DOS, >Powerview for Unix and Workview/Plus for Win 3.1, were excellent >products, for both schematic entry and simulation, they even had >a decent hot line and knowlegeable tech support. All of the above >products were compatible,a schematic entered in Powerview could be >read and modifiedin Workview and Workview+, and vice versa. >There was support for command line and macros. >I would say the only problem with Workview+ was the lack of support of >windows printers, but it came with a set of drivers for many printers. >Workview+ and Powerview shared the same GUI. >In 93/94, they came out with the ProSeries, the only reason to purchase >these tools is that they were cheaper than Workview+ and they were >windows compliant. They were buggy and lacked many features. >In 95/96, ViewOffice was announced and delivered, everyone using Workview+ >had a choice of either getting an upgrade for Win3.1 and for Win95/NT, with >the understanding that the Win3.1 upgrade would be the last one, with no >further product enhancements. >When ViewOffice was in beta, Viewlogic received dozens if not hundred >of bug reports and enhancements requests,, they decided to ignore most >of them and just fix the most glaring bugs that prevented the product >from working, gone were the command line, macros, the editing shortcuts, >and a few other features that made Workview+ an above average CAD tool. >At the same time, their tech support competency disappeared. Viewoffice >is now an average to a below average CAD tool. >As a consultant, I am asked what CAD tool do I recommend, and used to say >Viewlogic. In 96, five of my clients have purchased more than 15 seats >of Viewoffice, but no more, now its welcome to Viewlogic HELL. >One of these clients decided to get Viewsynthesis against my advice, because >Viewlogic made hime a deal he could not refuse. So we set on designing >three FPGAs and two ASICs with it, after about three months of trying >to debug the logic generated by ViewSynthesis, he wised up and >purchased Synopsys. >In summary: > - Viewsynthesis is BAD! > - Viewoffice is usable but less user friendly than the older > products. > - Viewlogic tech support is non-existent. > - I will not recommend ViewOffice to any of my clients anymore. >IMHO, Viewlogic decided that they had to compete with Orcad and some >of the other low end tools at the same time they were trying to compete >with Mentor and Cadence, and they missed the boat. They changed the sales >channel, by focusing on distributors (Trilogic in Mass.) for small companies >and direct sales for large corp. >So my question is: > Does Mentor Graphics and or Cadence have CAD tools for Win/NT or > a Sparc at a competitive price? >Tools I use today are: > - Viewdraw and Viewsim (until I find a replacement) > - Modeltech for VHDL simulation > - FPGA Express for FPGA synthesis > - DC for ASIC synthesis >Alain Arnaud (arnaud@ecla.com) >ECLA Inc. FYI, I have recently evaluated the PC version of VCS. The compiler is OK, but they insist on using Viewwave instead of XVCS like the Unix version. The PC version is unusable - mostly due to bugs with the VCS-Viewave interface. Let's hope Viewlogic doesn't ruin a great product like VCS. --TimArticle: 5765
On Tue, 11 Mar 1997 16:54:56 -0700, Peter Alfke <peter@xilinx.com> wrote: -- snip >If you use the mode pins as outputs during the normal operation, then >you can easily, for configuration, establish the Low level with a >pull-down resistor ( make it 2.7 kilohm to get a nice low voltage ) >Aside from a little wasted current, these resistors cause no harm during >operation. > -- more snipped This would have been handy if it had been in the data book. I called tech support a year or so ago with this very question for a 5210 and after some checking the Xilinx rep. suggested 6k8. Well guess what happened? Some boards programmed and others didn't. My own measurements led me to use 3k0 instead. On the subject of configuration pins it would be very useful if one could associate signals with dedicated pins at the schematic level. I know you can do this with pin numbers but that only works for a specific package. For example, I have an output which is an active low reset. I want to tie this signal to the LDC pin so I would like to add an attribute LOC=LDC (or something similar) to the OPAD. The same could be done with the data pins. I use express mode programming and I always worry that I have miss read the data book and have not transposed the pin numbers for the data bus correctly when I create the CST file. So adding a LOC=D0 etc. would eliminate one more error prone operation. What do you think? Alan Weir Sphere Communications Inc. Alan Weir Sphere Communications Inc.Article: 5766
Insight & Xilinx present a VHDL training course. When: April 10 & 11 1997 Time: 8:00AM - 5:00PM Where: CompUSA, (301)816-4710 1776 East Jefferson St. Rockville,MD Who Should Attend? Attending an Insight/Esperan Training Course is one of the fastest, most efficient ways to learn how to design with VHDL and target your design for devices from Xilinx. For design engineers recently tasked with designing in VHDL, these courses are excellent introductions to VHDL concepts and techniques. They are also helpful courses for engineers with previous FPGA design experience who are now starting to design with VHDL. The Benefits Reduce your learning time Get to market faster Make fewer design iterations Increase design quality Curriculum VHDL Introduction, Signals: Types and Operators, Concurrent and Sequential Statements, The Synthesis Process, Definition of RTL Code, VHDL Coding Style Issues, Synthesis of Mathematical Operators, Labs, Issues in Synthesizing to the Xilinx Architecture Tuition: $795.00 Remit to: Insight Electronics 6925 Oakland Mills Rd Suite D Columbia, MD 21045 Lunch and breaks are included. *** Tuition costs may be applied toward the purchase of a development system*** Reservations: Call 410-381-3131 or 800-677-7716 Say you "saw it on the web"Article: 5767
Insight & Xilinx present a Schematic based training course. When: April 7 & 8 & 9 1997 Time: 8:00AM - 5:00PM Where: CompUSA, (301)816-4710 1776 East Jefferson St. Rockville,MD Course Outline: Introduction: Development Systems Overview Architecture Overview Xilinx Design Flow Schematic Entry Guidelines Foundation Software Design Manager Flow Engine Automatic Implementation Timing Specifications Xact-Performance Delay Specification Static Timing Analyzer Designing for Xilinx FPGAs Combinatorial Logic Registered Logic Memory Design I/O Design X-BLOX Module Generation Designing for Xilinx CPLDs Text Entry Guidelines Xilinx-ABEL Software Floorplanning Incremental Design XACT-Floorplanner Relationally-Placed Macros Timing Analysis Good Design Practices Simulation Guidelines Configuration Programming Modes Bitstream Generator PROM File Formatter Hardware Debugger Downloading & Readback Tuition: $495.00 Remit to: Insight Electronics 6925 Oakland Mills Rd Suite D Columbia, MD 21045 Lunch and breaks are included. *** Tuition costs may be applied toward the purchase of a development system*** Reservations: Call 410-381-3131 or 800-677-7716 Say you "saw it on the web"Article: 5768
Unfortunately, the VHDL parser in Synopsys can't handle a function
call to detect a rising ege or falling edge inference. It must see:
X'EVENT and X='0'
The only way I can see for you to be able to use the functions rising_edge() or
falling_edge() is to pre-process the code before reading into synopsys.
In the synopsys script you could have:
sh cat FILE | perl -pe 's/rising_edge\(\s*(\w+)\s*\)/$1\047EVENT and $1=\0471\047/' > NEW_FILE
read -for vhdl NEW_FILE
For non perl hackers, the above line probably looks grim. But it does work. The \047
part of the substitution represents '. \047 is needed because otherwise perl thinks
that ' is string delimiter and gets a bit confused.
So \0471\047 is really '1', but I guess this is all very confusing for non-perl
hackers.
Andrew
Ben Twijnstra (bentw@pi.net) wrote:
: TswvXyooj wrote:
: > Has anyone run into this problem. Does anyone have a "set"
: > script (or something like that) that will allow me to
: > continue using Rising_Edge(clk) and Falling_Edge(clk)
: > functions with Synopsys' tools? Thank-you in advance.
: Although I'm not very familiar with Synopsys, you could use a function
: like this (off the cuff, after a few glasses of wine at home, so expect
: some error messages):
: FUNCTION Falling_edge(signal clock : std_ulogic) : BOOLENA
: BEGIN
: IF (Clock'EVENT and Clock = '0') then
: return TRUE
: ELSE
: return FALSE
: END IF;
: END;
: Rising_edge should be trivial. If you define these in a package which
: you include you should be fine.
: Regards,
: Ben Twijnstra
Article: 5769Dear Gerhard, Are you generate your circuit using synthesis tools like ViewSynthesis 5.2 or using schematics capture ? Cheers HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH | | | Humberto Honda | | Mestrado em Eletronica de Potencia | | CPDEE - UFMG | | e-mail: honda@cpdee.ufmg.br | | Home-page:www.lecom.dcc.ufmg.br/~honda | | tel: 225-2337 | HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHArticle: 5770
Peter Alfke <peter@xilinx.com> wrote in article <peter-1203970955240001@appsmac-1.xilinx.com>... > In article <331F5B0F.10E8@Boeing.com>, Mark.E.Osterud@Boeing.com wrote: > > > Can someone point out a study that evaluates the reliability aspects of > > an FPGA as opposed to discrete logic? > > This is a very broad question, and I would suggest to narrow it down to: > > 1. Hard failures > 2. Soft errors > 2a. Soft errors as a result of radiation ( single-event upset ) > > Regarding 1, Xilinx devices ( and I can only speak for my company, but I > assume that our competitors are not very much worse, otherwise they would > be out of business ) have an excellent recod of reliability, expressed in > sigle-digit FIT numbers. > You can ( and most likely do ) receive a quarterly reliability brochure > update from Xilinx. We are very proud of our record, which is partly the > result of using state-of-the-art, but otherwise plain-vanilla CMOS > processing.No strange voltages, no exotic structures, no untestable > circuitry. ( Do you detect a slight bias against antifuses here ?) > > 2. We have never heard of configuration bits getting corrupted under > normal operating conditions. We make the configuration latches out of > active inverters, -no polysilicon pullups here- so we expect the > configuration to be far more robust than the information stored in > standard SRAMs. > > 2a. Considering the business your company is in, this may be important to > you, but I don't have data here. You may read a very, very long thread in > this newsgroup a few months ago. > > Peter Alfke, Xilinx Applications > Peter, probably for 'radiation' effects you should break things down a bit more. there are several different effects, with several different mechanisms and impacts on the chip. these include (in general - may need to talk about xilinx internal architecture specifically which would be interesting) : a. single event upset to configuration memory b. single event upset to chip state (i.e., is chip programmed?, jtag tap controller state, various counters, checksum computations, etc.) c. single event upset to user storage for look up tables for logic implementation d. single event upset to user memory (flip-flops, latches) e. single event latchup f. total ionizing dose effects those are the major ones. others like nuetron exposure generally aren't a problem for standard cmos. and prompt dose upset, latchup, etc., are used by the military guys and are separate tests (those i generally don't deal with too much) with separate limits. since only active inverters are used for configuration memories, stuck bits shouldn't be a problem like they are in 4T commercial sram cells and haven't yet been observed in tests of fpgas. looking through the xilinx data book, i didn't see the optional hard reset pin for the jtag tap controller, which figures into the seu results, and tap controller upsets have been observed on other manufacturer's chips with jtag with no hard reset. having gone through a number of data books, i only saw that quicklogic implemented the hard reset on their parts. personally, with like 200+ pins on these parts, for military and space and other critical apps, i like the hard reset on the tap controller and would give up the 1 i/o pin. as for exotic structures, strange voltages and biases, test data that i have seen (and some of which i took myself) on device reliability also show good results for devices with certain classes of antifuses. for some other types, reliability has been not up to speed, from what i've heard and read. it would be interesting to read any published or available reliability info on the xilinx antifuse product project for comparison. one antifuse based part that i have seen only quotes a 10 year limit on the parts, not good enough for many military systems and spacecraft. anyways, the stuff that makes the fpga's re-programmable contributes to the radiation-based reliability - likewise, the 'exotic and strange' stuff for dielectric antifuse fpga's contributes to their radiation-based reliability, particularly for the commercial/military products. there are published reports on the radiation effects on things like charge pumps and antifuses, which definitely are susceptible, and for the most part, limit the radiation performance of these devices. radiation-hardened versions (with incorporated design changes) help quite a bit in contrast to most off the shelf products but do not bring the failure rate to zero for these structure and they will have an error rate measured in FITs, based on the rad environment. there's a running summary of radiation effects, along with other things on fpga's at http://arioch.gsfc.nasa.gov/eee_links/eeeintro.html which is updated quarterly. additional info and insights are always accepted. in particular to the xilinx parts, there is data on the xc3090. rkArticle: 5771
has anyone ever duplicated a 74hc195 with a pld? i've a need
to add a 195 and some other circuitry in a single chip.
thanks for the reply.
roger
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Article: 5772>Another example -- why isn't > PCI spec designed so to make it easy to build a high-performance interface > out of FPGA (eg, IRDY and TRDY should have been made to mean readiness > to transfer data in the NEXT clock cycle). Could it be that the consortium > members want no challenges from those who are not big enough to do hardwired > gate arrays? > Actually, you are almost correct. PCI was designed to be implemented only in gate arrays. When 'invented' (and I use that term loosely...) there were no FPGAs that were really applicable to be used in PCI interfaces. The original intention of PCI was to make custom silicone chips that contained both the PCI interface and the back end, say ethernet, or graphics etc, and given this single chip solution, be quite inexpensive. Look at PCI 100M ethernet cards, or PCI graphics cards...they are substantially cheaper than their ISA counterparts (or EISA for that matter) and provide much more speed and functionality. FPGAs at the time of PCI conception, were very expensive. Austin Franklin ..darkroom@ix.netcom.com.Article: 5773
In message <33248F6B.5563@mail.mei.com> - Scott Kroeger
<Scott.Kroeger@mail.mei.com>Mon, 10 Mar 1997 16:47:08 -0600 writes:
:>
:>Mike Williams wrote:
:><snip>
:>
:>> I'm looking to update my NT OS CAD tool set. I was looking at ORCAD
:>> but was told by some old school VIEWlogic users that VIEWlogic was
:>> superior. Now I'm not so sure.
:>>
:>> Any suggestions. I need schematic entry for PCB design. I don't need
:>> to actually do the PC layout, just produce the schematics, parts
:>> list and netlist.
:>
Protel for Windows Advanced Schematic is worth looking at. Its not expensive
and will export netlists in a dozen formats. One thing to check is for NT
compatability problems. Aparently there are a few with the Adv. PCB package
but I'm not sure about the Schematic because its newer than the PCB package.
P.S. I think Protel don't support NT 4.0 yet. But neither do a lot of Windows
3.11 CAD suppliers so don't be too surprised if they can't help if something
strange happens in NT 4 that doesn't happen in older versions of NT
you can but ask about such things.
I communicate mostly with this guy:
matthew@protel.com.au
if you have questions about protel & NT ask protel
--
Simon Peacock Telephone: +64-4-388-8964 (home)
simon@digitech.co.nz +64-4-389-8909 (work)
simon@actrix.gen.nz Fax: +64-4-389-9901 (work)
http://www.digitech.co.nz
Work address: 102-112 Daniell Street, Newtown
(PO Box 20-002, Wellington South)
Wellington, New Zealand
Article: 5774>Could it be that the consortium >members want no challenges from those who are not big enough to do hardwired >gate arrays? Even if your hypothesis might be wrong, your observation is entirely correct. One just cannot make a cheap PCI card, without an ASIC.
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